TI1 LM4936MHX/NOPB Boomerâ ¢ audio power amplifier series stereo 2w audio power amplifiers with volume control and selectable control interface (spi or i2c) Datasheet

LM4936
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LM4936 Boomer™ Audio Power Amplifier Series Stereo 2W Audio Power Amplifiers with
Volume Control and Selectable Control Interface (SPI or I2C)
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FEATURES
DESCRIPTION
1
•
•
•
23
•
•
•
•
2
Selectable SPI or I C Control Interface
System Beep Detect
Stereo Switchable Bridged/Single-Ended
Power Amplifiers
Selectable Internal/External Gain and Bass
Boost
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection Circuitry
Headphone Sense
APPLICATIONS
•
•
•
Portable and Desktop Computers
Multimedia Monitors
Portable Radios, PDAs, and Portable TVs
KEY SPECIFICATIONS
•
•
•
PO at 1% THD+N
– into 3Ω, 2.2W (Typ)
– into 4Ω, 2.0W (Typ)
– into 8Ω, 1.25W (Typ)
Single-ended mode - THD+N at 90mW into
32Ω, 1% (Typ)
Shutdown current, 0.7µA (Typ)
The LM4936 is a monolithic integrated circuit that
provides volume control, and stereo bridged audio
power amplifiers capable of producing 2W into 4Ω (1)
with less than 1% THD or 2.2W into 3Ω (2) with less
than 1% THD.
Boomer audio integrated circuits were designed
specifically to provide high quality audio while
requiring a minimum amount of external components.
The LM4936 incorporates a SPI or I2C Control
Interface that runs the volume control, stereo bridged
audio power amplifiers and a selectable gain or bass
boost. All of the LM4936's features (i.e. SD, Mode,
Mute, Gain Sel) make it optimally suited for
multimedia monitors, portable radios, desktop, and
portable computer applications.
The LM4936 features an externally controlled, lowpower consumption shutdown mode, and both a
power amplifier and headphone mute for maximum
system flexibility and performance.
(1)
(2)
When properly mounted to the circuit board, LM4936MH will
deliver 2W into 4Ω. See Application Information section
HTSSOP PACKAGE PCB MOUNTING CONSIDERATIONS
for more information.
An LM4936MH that has been properly mounted to the circuit
board and forced-air cooled will deliver 2.2W into 3Ω.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM4936
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Connection Diagram
GND
2
I C/SPI Select
ID/CE
SCL/CLK
SDA/DATA
2
I C/SPI VDD
VDD
GND
Right Dock
Right In
Beep In
Left In
Left Dock
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
Right Out+
VDD
Right Out Right Gain 2
Right Gain 1
GND
Bypass
HP Sense
GND
Left Gain 1
Left Gain 2
Left OutVDD
Left Out+
Figure 1. HTSSOP Package
(Top View)
See Package Number PWP0028A for HTSSOP
Block Diagram
Left Dock
2
SPI/I C Select
Left Gain 1
20 k:
Left Gain 2
20 k:
2
SPI/I C VDD
ADDR/EN
SCL/CLK
SDA/Data
20 k:
2
SPI/I C
Control
10 k:
10 k:
0.068 PF
HP Sense
+
20 k:
20 k:
200 k:
Left In
0.33 PF
Beep In
200 k:
Right In
20 k:
0.33 PF
+
Beep
Detect
Bias
+
-
GND
+
-
+Left Out
HP Sense
+Right Out
20 k:
+
-
Power
Management
10 k:
Bypass
Headphone
Jack
Stereo
20 k:
+
Volume
Control
32 steps
20 k:
VDD
-Left Out
-Right Out
10 k:
Click and Pop
Suppression
Circuitry
20 k:
0.068 PF
Right Dock
20 k:
Right Gain 1
20 k:
Right Gain 2
Figure 2. LM4936 Block Diagram
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
Storage Temperature
-65°C to +150°C
−0.3V to VDD +0.3V
Input Voltage
(3)
Internally limited
ESD Susceptibility (4)
2000V
ESD Susceptibility (5)
200V
Power Dissipation
Junction Temperature
Soldering Information
150°C
Vapor Phase (60 sec.)
Small Outline Package
215°C
Infrared (15 sec.)
220°C
θJC (typ) - PWP0028A
2°C/W
θJA (typ) - PWP0028A (HTSSOP) (6)
41°C/W
θJA (typ) - PWP0028A (HTSSOP) (7)
54°C/W
θJA (typ) - PWP0028A (HTSSOP) (8)
59°C/W
(9)
93°C/W
θJA (typ) - PWP0028A (HTSSOP)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θ JA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA )/θJA. For the LM4936, TJMAX = 150°C, and the typical junction-toambient thermal resistance for each package can be found in the Absolute Maximum Ratings section above.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF – 240pF discharged through all pins.
The θJA given is for an PWP0028A package whose HTSSOP is soldered to a 2in2 piece of 1 ounce printed circuit board copper on a
bottom side layer through 21 8mil vias.
The θJA given is for an PWP0028A package whose HTSSOP is soldered to an exposed 2in 2 piece of 1 ounce printed circuit board
copper.
The θJA given is for an PWP0028A package whose HTSSOP is soldered to an exposed 1in 2 piece of 1 ounce printed circuit board
copper.
The θJA given is for an PWP0028A package whose HTSSOP is not soldered to any copper.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤TMAX
−40°C ≤ TA ≤ 85°C
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (1)
I2C/SPI VDD ≤ VDD
2.4V ≤ I2C/SPI VDD ≤ 5.5V
(1)
I2C/SPI VDD must not be larger than VDD at any time or damage to the IC may occur. During power up and power down, I2C/SPI VDD
must remain equal to VDD or lower.
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Electrical Characteristics for Entire IC (1) (2)
The following specifications apply for VDD = 5V unless otherwise noted. Limits apply for TA = 25°C.
Symbol
VDD
Parameter
Conditions
LM4936
Typical
(3)
Limit (4)
Supply Voltage
Units
(Limits)
2.7
V (min)
5.5
V (max)
mA (max)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A
10
25
ISD
Shutdown Current
Vshutdown = VDD
0.7
2.0
VIH
Headphone Sense High Input Voltage
4
V (min)
VIL
Headphone Sense Low Input Voltage
0.8
V (max)
(1)
(2)
(3)
(4)
μA (max)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 2.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are specified
by design, test, or statistical analysis.
Electrical Characteristics for Volume Control (1) (2)
The following specifications apply for VDD = 5V. Limits apply for TA = 25°C.
Symbol
CRANGE
Parameter
Volume Control Range
Conditions
0
±0.75
dB (max)
-75
dB (min)
0.35
-78
dB (min)
fIN = 1kHz
Mute Attenuation
Mute Mode
4
Units
(Limits)
-91
Channel to Channel Gain Mismatch
(3)
(4)
Limit (4)
Minimum gain setting
AM
(2)
Typical
Maximum gain setting
ACh-Ch
(1)
LM4936
(3)
dB
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 2.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are specified
by design, test, or statistical analysis.
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Electrical Characteristics for Control Interface
(1) (2)
The following specifications apply for VDD = 5V, VDD = 3V and 2.4V ≤ I2C/SPI VDD ≤ 5.5V. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4936
Typical
(3)
Limit (4)
Units
(Limits)
t1
SCL period
2.5
μs (min)
t2
SDA Set-up Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
VIH
Digital Input High Voltage
0.7 X
I2C/SPIVDD
V (min)
VIL
Digital Input Low Voltage
0.3 X
I2C/SPIVDD
V (max)
tES
SPI ENABLE Setup Time
50
ns (min)
tEH
SPI ENABLE Hold Time
50
ns (min)
tEL
SPI ENABLE High Time
50
ns (min)
tDS
SPI DATA Setup Time
50
ns (min)
tDH
SPI DATA HOLD Time
50
ns (min)
tCS
SPI CLOCK Setup Time
50
ns (min)
tCH
SPI CLOCK High Pulse Width
100
ns (min)
tCL
SPI CLOCK Low Pulse Width
100
ns (min)
fCLK
SPI CLOCK Frequency
5
MHz (max)
(1)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 2.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are specified
by design, test, or statistical analysis.
(2)
(3)
(4)
Electrical Characteristics for Single-Ended Mode Operation (1) (2)
The following specifications apply for VDD = 5V. Limits apply for TA = 25°C.
Symbol
PO
Parameter
Output Power
Conditions
LM4936
Typical (3)
Limit (4)
Units
(Limits)
THD = 1%; f = 1kHz; RL = 32Ω
90
mW
THD = 10%; f = 1 kHz; RL = 32Ω
110
mW
0.02
%
THD+N
Total Harmonic Distortion+Noise
POUT = 20mW, f = 1kHz, RL = 32Ω,
AVD = 1, 80kHz BW
PSRR
Power Supply Rejection Ratio
CB = 1μF, f = 120Hz,
Input Terminated
VRIPPLE = 200mVp-p
57
dB
NOUT
Output Noise
A-Wtd Filter
18
µV
f = 1kHz, CB = 1μF
63
dB
Xtalk
(1)
(2)
(3)
(4)
(5)
Channel Separation
(5)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 2.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are specified
by design, test, or statistical analysis.
PCB design will affect Crosstalk performance.
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Electrical Characteristics for Bridged Mode Operation (1) (2)
The following specifications apply for VDD = 5V, unless otherwise noted. Limits apply for TA = 25°C.
Symbol
Parameter
LM4936
Conditions
Typical
(3)
Limit (4)
Units
(Limits)
50
mV (max)
VOS
Output Offset Voltage
VIN = 0V, No Load
10
PO
Output Power
THD + N = 1%; f = 1kHz; RL = 3Ω (5)
2.2
W
THD + N = 1%; f = 1kHz; RL = 4Ω (6)
2
W
THD+N = 1% (max); f = 1kHz;
RL = 8Ω
1.25
1.0
W (min)
THD+N = 10%; f = 1kHz; RL = 8Ω
1.6
W
THD+N
Total Harmonic Distortion+Noise
PO = 0.4W, f = 1kHz
RL = 8Ω, AVD = 2, 80kHz BW
0.06
%
PSRR
Power Supply Rejection Ratio
CB = 1µF, f = 120Hz,
Input Terminated
VRIPPLE = 200mVp-p; RL = 8Ω
55
dB
NOUT
Output Noise
A-Wtd Filter
36
µV
Xtalk
Channel Separation (7)
f = 1kHz, CB = 1μF
63
dB
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 2.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL ( Average Outgoing Quality Level). Datasheet min/max specification limits are specified
by design, test, or statistical analysis.
When driving 3Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board and forced-air cooled. The demo board
shown in the datasheet has planes for heat sinking. The top layer plane is 1.05 in2 (675mm2), the inner two layers each have a 1.03 in2
(667mm2) plane and the bottom layer has a 3.32 in2 (2143mm2) plane. The planes are electrically GND and interconnected through six
15 mil vias directly under the package and eight 28 mil vias in various locations.
When driving 4Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board. The demo board shown in the datasheet
has planes for heat sinking. The top layer plane is 1.05 in2 (675mm2), the inner two layers each have a 1.03 in2 (667mm2) plane and the
bottom layer has a 3.32 in2 (2143mm2) plane. The planes are electrically GND and interconnected through six 15 mil vias directly under
the package and eight 28 mil vias in various locations.
PCB design will affect Crosstalk performance.
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Typical Application
Figure 3. Typical Application Circuit
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Table 1. I2C/SPI Interface Controls (1)
B7
B6
B5
B4
B3
B2
B1
B0
I2C
Address
1
1
0
1
1
0
ID
0
Mode
Control
Register
0
0
0
HP
Control
Gain Sel
Mode
Mute
Shutdown
Volume
Control
Register
(See Table
4)
1
0
0
V4
V3
V2
V1
V0
(1)
If system beep is detected on the Beep In pin, the system beep will be passed through the bridged amplifier regardless of the logic of
the Mute and HP Control bits (B1, B4) and HP Sense pin.
Table 2. Headphone Control
HP Sense Pin
I2C/SPI HP Control (B4)
Output Stage Configuration
0
0
BTL
0
1
SE
1 (VDD)
0
SE
1 (VDD)
1
SE
Table 3. Logic Controls
8
Logic Level
B3 (Gain Sel)
B2 (Mode)
B1 (Mute)
B0 (Shutdown)
I2C/SPI Select
0
Internal Gain
Fixed Volume, 0dB
Mute Off (Play)
Device Shutdown
I2C mode
1
External Gain
Adjustable Volume
Mute On
Device Active
SPI mode
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Typical Performance Characteristics
THD+N vs Output Power/Channel
VDD = 5V, RL = 3Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 3Ω, AV-BTL = 2V/V
POUT = 1.5W/Channel, 80kHz BW
Figure 4.
Figure 5.
THD+N vs Output Power/Channel
VDD = 5V, RL = 4Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 4Ω, AV-BTL = 2V/V
POUT = 1.5W/Channel, 80kHz BW
Figure 6.
Figure 7.
THD+N vs Output Power/Channel
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
POUT = 1W/Channel, 80kHz BW
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
10
THD+N vs Output Power/Channel
VDD = 5V, RL = 8Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 8Ω, AV-SE = 1V/V
POUT = 100mW/Channel, 80kHz BW
Figure 10.
Figure 11.
THD+N vs Output Power/Channel
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
POUT = 40mW/Channel, 80kHz BW
Figure 12.
Figure 13.
THD+N vs Output Power/Channel
VDD = 3V, RL = 3Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 3Ω, AV-SE = 2V/V
POUT = 500mW/Channel, 80kHz BW
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
THD+N vs Output Power/Channel
VDD = 3V, RL = 4Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 4Ω, AV-BTL = 2V/V
POUT = 450mW/Channel, 80kHz BW
Figure 16.
Figure 17.
THD+N vs Output Power/Channel
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
f = 1kHz, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
POUT = 250mW/Channel, 80kHz BW
Figure 18.
Figure 19.
THD+N vs Output Power/Channel
VDD = 3V, RL = 8Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 8Ω, AV-SE = 1V/V
POUT = 50mW/Channel, 80kHz BW
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
12
THD+N vs Output Power/Channel
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
f = 1kHz, COUT = 220µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
POUT = 20mW/Channel, 80kHz BW
Figure 22.
Figure 23.
THD+N vs Output Voltage
VDD = 5V, RLDOCK = 10kΩ, Dock Pins
f = 1kHz, CO = 1µF, 80kHz BW
THD+N vs Frequency
VDD = 5V, RLDOCK = 10kΩ, Dock Pins
VIN = 1Vp-p, CO = 1µF, 80kHz BW
Figure 24.
Figure 25.
THD+N vs Output Voltage
VDD = 3V, RLDOCK = 10kΩ, Dock Pins
f = 1kHz, CO = 1µF, 80kHz BW
THD+N vs Frequency
VDD = 3V, RLDOCK= 10kΩ, Dock Pins
VIN = 1Vp-p, CO = 1µF, 80kHz BW
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 5V, VRIPPLE = 200mVp-p
Inputs Terminated, 80kHz BW
PSRR vs Frequency
VDD = 3V, VRIPPLE = 200mVp-p
Inputs Terminated, 80kHz BW
Figure 28.
Figure 29.
Crosstalk vs Frequency
VDD = 5V, RL = 8Ω, AV-BTL = 2V/V
POUT = 1W, 80kHz BW
Crosstalk vs Frequency
VDD = 3V, RL = 8Ω, AV-BTL = 2V/V
POUT = 250mW, 80kHz BW
Figure 30.
Figure 31.
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, AV-SE = 1V/V
POUT = 40mW, 80kHz BW
Crosstalk vs Frequency
VDD = 3V, RL = 32Ω, AV-SE = 1V/V
POUT = 20mW, 80kHz BW
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
14
Headphone Sense Threshold vs Supply Voltage
RL = 8Ω, AV-SE = 1V/V
COUT = 220µF, 80kHz BW
Output Level vs Frequency
External Gain with Bass Boost
Figure 34.
Figure 35.
Output Power/Channel vs Supply Voltage
RL = 3Ω, AV-BTL = 2V/V, 80kHz BW
Output Power/Channel vs Supply Voltage
RL = 4Ω, AV-BTL = 2V/V, 80kHz BW
Figure 36.
Figure 37.
Output Power/Channel vs Supply Voltage
RL = 8Ω, AV-BTL = 2V/V, 80kHz BW
Output Power/Channel vs Supply Voltage
RL = 8Ω, AV-SE = 1V/V, 80kHz BW
Figure 38.
Figure 39.
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Typical Performance Characteristics (continued)
Output Power/Channel vs Supply Voltage
RL = 32Ω, AV-SE = 1V/V, 80kHz BW
Power Derating Curve
These curves show the thermal dissipation ability of the LM4936MH at
different ambient temperatures given these conditions:
500LFPM + 2in2: The part is soldered to a 2in2, 1 oz. copper plane
with 500 linear feet per minute of forced-air flow across it.
2in2on bottom: The part is soldered to a 2in2, 1oz. copper plane that
is on the bottom side of the PC board through 21 8 mil vias.
2in2: The part is soldered to a 2in2, 1oz. copper plane.
1in2: The part is soldered to a 1in2, 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air
cooled.
Figure 41.
Figure 40.
Power Dissipation vs Output Power/Channel
VDD = 5V, AV-BTL = 2V/V, THD+N ≤ 1%, 80kHz BW
Power Dissipation vs Output Power/Channel
VDD = 3V, AV-BTL = 2V/V, THD+N ≤ 1%, 80kHz BW
Figure 42.
Figure 43.
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Typical Performance Characteristics (continued)
16
Power Dissipation vs Output Power/Channel
VDD = 5V, AV-SE = 1V/V, THD+N ≤ 1%, 80kHz BW
Power Dissipation vs Output Power/Channel
VDD = 3V, AV-SE = 1V/V, THD+N ≤ 1%, 80kHz BW
Figure 44.
Figure 45.
Supply Current vs Supply Voltage
RL = 8Ω
Dropout Voltage
Figure 46.
Figure 47.
Output Power/Channel vs Load Resistance
Output Power/Channel vs Load Resistance
Figure 48.
Figure 49.
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Typical Performance Characteristics (continued)
Output Power/Channel vs Load Resistance
Output Power/Channel vs Load Resistance
Figure 50.
Figure 51.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM4936 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4936.
The I2C address for the LM4936 is determined using the ID/CE pin. The LM4936's two possible I2C chip
addresses are of the form 110110X10 (binary), where X1 = 0, if ID/CE is logic low; and X1 = 1, if ID/CE is logic
high. If the I2C interface is used to address a number of chips in a system, the LM4936's chip address can be
changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 53. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4936 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4936.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4936 received the
data.
If the master has more data bytes to send to the LM4936, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I2C/SPI INTERFACE POWER SUPPLY PIN (I2C/SPI VDD)
The LM4936's I2C/SPI interface is powered up through the I2C/SPI VDD pin. The LM4936's I2C/SPI interface
operates at a voltage level set by the I2C/SPI VDD pin which can be set independent to that of the main power
supply pin VDD. This is ideal whenever logic levels for the I2C/SPI interface are dictated by a microcontroller or
microprocessor that is operating at a lower supply voltage than the main battery of a portable system.
HTSSOP PACKAGE PCB MOUNTING CONSIDERATIONS
HTSSOP (die attach paddle) packages provide a low thermal resistance between the die and the PCB to which
the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper
traces, ground plane and, finally, surrounding air. The result is a low voltage audio power amplifier that produces
2.1W at ≤ 1% THD with a 4Ω load. This high power is achieved through careful consideration of necessary
thermal design. Failing to optimize thermal design may compromise the LM4936's high power performance and
activate unwanted, though necessary, thermal shutdown protection.
The packages must have their exposed DAPs soldered to a grounded copper pad on the PCB. The DAP's PCB
copper pad is connected to a large grounded plane of continuous unbroken copper. This plane forms a thermal
mass heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided
PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer
or backside copper heat sink area with vias. The via diameter should be 0.012in–0.013in with a 1.27mm pitch.
Ensure efficient thermal conductivity by plating-through and solder-filling the vias.
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Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load.
Heatsink areas not placed on the same PCB layer as the LM4936 should be 5in2 (min) for the same supply
voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase
the area to compensate for ambient temperatures above 25°C. In systems using cooling fans, the LM4936MH
can take advantage of forced air cooling. With an air flow rate of 450 linear-feet per minute and a 2.5in2 exposed
copper or 5.0in2 inner layer copper plane heatsink, the LM4936MH can continuously drive a 3Ω load to full
power. In all circumstances and conditions, the junction temperature must be held below 150°C to prevent
activating the LM4936's thermal shutdown protection. The LM4936's power de-rating curve in the Typical
Performance Characteristics shows the maximum power dissipation versus temperature. Example PCB layouts
are shown in the LM4936 MH HTSSOP Board Artwork section. Further detailed and specific information
concerning PCB layout, fabrication, and mounting is available in Texas Instruments' AN1187.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 2.1W to 2.0W. This problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 3, the LM4936 output stage consists of two pairs of operational amplifiers, forming a twochannel (channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies
equally to channel B.)
Figure 3 shows that the first amplifier's negative (-) output serves as the second amplifier's input. This results in
both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase
difference, a load is placed between −OUTA and +OUTA and driven differentially (commonly referred to as
“bridge mode”). This results in a differential gain of
AVD = 2 * (Rf/R i)
(1)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. This produces four
times the output power when compared to a single-ended amplifier under the same conditions. This increase in
attainable output power assumes that the amplifier is not current limited or that the output signal is not clipped.
To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the AUDIO
POWER AMPLIFIER DESIGN section.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing channel A's and channel B's outputs at half-supply. This eliminates the coupling capacitor that single
supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
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PDMAX = (VDD)2/(2π2RL)
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Single-Ended
(2)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions.
The LM4936 has two operational amplifiers per channel. The maximum internal power dissipation per channel
operating in the bridge mode is four times that of a single-ended amplifier. From Equation 3, assuming a 5V
power supply and a 4Ω load, the maximum single channel power dissipation is 1.27W or 2.54W for stereo
operation.
PDMAX = 4 * (VDD)2/(2π2RL)
Bridge Mode
(3)
The LM4936's power dissipation is twice that given by Equation 2 or Equation 3 when operating in the singleended mode or bridge mode, respectively due to stereo operation. Twice the maximum power dissipation point
given by Equation 3 must not exceed the power dissipation given by Equation 4:
PDMAX′ = (TJMAX − TA)/θJA
(4)
The LM4936's TJMAX = 150°C. In the MH package soldered to a DAP pad that expands to a copper area of 2in2
on a PCB, the LM4936MH's θJA is 41°C/W. At any given ambient temperature TA, use Equation 4 to find the
maximum internal power dissipation supported by the IC packaging. Rearranging Equation 4 and substituting
PDMAX for PDMAX′ results in Equation 5. This equation gives the maximum ambient temperature that still allows
maximum stereo power dissipation without violating the LM4936's maximum junction temperature.
TA = TJMAX – 2*PDMAX θJA
(5)
For a typical application with a 5V power supply and an 4Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 45°C
for the MH package.
TJMAX = PDMAX θJA + TA
(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4936's 150°C TJMAX,
reduce the maximum junction temperature by reducing the power supply voltage or increasing the load
resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point.
If the result of Equation 3 multiplied by 2 for stereo operation is greater than that of Equation 4, then decrease
the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are
insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area
around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder
attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat
sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-tosink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the Typical Performance
Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitor to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1µF tantalum bypass capacitance connected
between the LM4936's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so
may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4936's power
supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage's stability and the amplifier's PSRR. The PSRR improvements increase
as the BYPASS pin capacitor value increases. Too large a capacitor, however, increases turn-on time and can
compromise the amplifier's click and pop performance. The selection of bypass capacitor values, especially CB,
depends on desired PSRR requirements, click and pop performance (as explained in the following section,
SELECTING PROPER EXTERNAL COMPONENTS), system cost, and size constraints.
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SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the LM4936's performance requires properly selecting external components. Though the LM4936
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
The LM4936 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-tonoise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain circuits
demand input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal
sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the AUDIO POWER
AMPLIFIER DESIGN section for more information on selecting the proper gain.
INPUT CAPACITOR VALUE SELECTION
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (0.33µF in Figure 3), but
high value capacitors can be expensive and may compromise space efficiency in portable designs. In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150 Hz. Applications using speakers with this limited frequency response reap little
improvement by using a large input capacitor.
Besides affecting system cost and size, the input coupling capacitor has an effect on the LM4936's click and pop
performance. When the supply voltage is first applied, a transient (pop) is created as the charge on the input
capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional to the input
capacitor's size. Higher value capacitors need more time to reach a quiescent DC voltage (VDD/2) when charged
with a fixed current. The amplifier's output charges the input capacitor through the feedback resistor, Rf. Thus,
pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired
−6dB frequency.
As shown in Figure 3, the input resistor (RIR, RIL = 20kΩ) and the input capacitor (CIR, CIL = 0.33µF) produce a
−6dB high pass filter cutoff frequency that is found using Equation 7.
(7)
As an example when using a speaker with a low frequency limit of 150Hz, the input coupling capacitor, using
Equation 7, is 0.053µF. The 0.33µF input coupling capacitor shown in Figure 3 allows the LM4936 to drive a high
efficiency, full range speaker whose response extends below 30Hz.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4936 contains circuitry that minimizes turn-on and shutdown transients or “clicks and pops”. For this
discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the LM4936's internal amplifiers are configured as unity gain
buffers. An internal current source changes the voltage of the BYPASS pin in a controlled, linear manner. Ideally,
the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains
unity until the voltage on the BYPASS pin reaches 1/2 VDD . As soon as the voltage on the BYPASS pin is
stable, the device becomes fully operational. Although the BYPASS pin current cannot be modified, changing the
size of CB alters the device's turn-on time and the magnitude of “clicks and pops”. Increasing the value of CB
reduces the magnitude of turn-on pops. However, this presents a tradeoff: as the size of CB increases, the turnon time increases. There is a linear relationship between the size of CB and the turn-on time. Below are some
typical turn-on times for various values of CB:
CB
TON
0.01µF
2ms
0.1µF
20ms
0.22µF
44ms
0.47µF
94ms
1.0µF
200ms
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DOCKING STATION INTERFACE
Applications such as notebook computers can take advantage of a docking station to connect to external devices
such as monitors or audio/visual equipment that sends or receives line level signals. The LM4936 has two
outputs, Right Dock and Left Dock, which connect to outputs of the internal input amplifiers that drive the volume
control inputs. These input amplifiers can drive loads of >1kΩ (such as powered speakers) with a rail-to-rail
signal. Since the output signal present on the RIGHT DOCK and LEFT DOCK pins is biased to VDD/2, coupling
capacitors should be connected in series with the load when using these outputs. Typical values for the output
coupling capacitors are 0.33µF to 1.0µF. If polarized coupling capacitors are used, connect their "+" terminals to
the respective output pin, see Figure 3.
Since the DOCK outputs precede the internal volume control, the signal amplitude will be equal to the input
signal's magnitude and cannot be adjusted. However, the input amplifier's closed-loop gain can be adjusted
using external resistors. These 20kΩ (RDOCK1, RDOCK2) are shown in Figure 3 and they set each input amplifier's
gain to -1. Use Equation 8 to determine the input and feedback resistor values for a desired gain.
- AVR = RDOCK1/RIN1 and - AVL = RDOCK2/RIN2
(8)
Adjusting the input amplifier's gain sets the minimum gain for that channel. Although the single ended output of
the Bridge Output Amplifiers can be used to drive line level outputs, it is recommended that the R & L Dock
Outputs simpler signal path be used for better performance.
BEEP DETECT FUNCTION
Computers and notebooks produce a system “beep“ signal that drives a small speaker. The speaker's auditory
output signifies that the system requires user attention or input. To accommodate this system alert signal, the
LM4936's beep input pin is a mono input that accepts the beep signal. Internal level detection circuitry at this
input monitors the beep signal's magnitude. When a signal level greater than VDD/2 is detected on the BEEP IN
pin, the bridge output amplifiers are enabled. The beep signal is amplified and applied to the load connected to
the output amplifiers. A valid beep signal will be applied to the load even when MUTE is active. Use the input
resistors connected between the BEEP IN pin and the stereo input pins to accommodate different beep signal
amplitudes. These resistors (RBEEP) are shown as 200kΩ values in Figure 3. Use higher value resistors to reduce
the gain applied to the beep signal. The resistors must be used to pass the beep signal to the stereo inputs. The
BEEP IN pin is used only to detect the beep signal's magnitude: it does not pass the signal to the output
amplifiers. The LM4936's shutdown mode must be deactivated before a system alert signal is applied to BEEP
IN pin.
MICRO-POWER SHUTDOWN
Shutdown mode is activated when a digital 0 is loaded into the Shutdown bit, B0. When active, the LM4936's
micro-power shutdown feature turns off the amplifier's bias circuitry reducing supply current to a typical 0.7μA.
Loading a digital 1 into B0 disables shutdown mode. When the LM4936 has power applied, all register bits will
have a default value of 0. Because of this, the LM4936 will be in shutdown mode when power is applied.
MODE FUNCTION
The LM4936's Mode function has two states controlled by bit B2. A digital 0 in bit B2 disables the volume control
and forces the LM4936 to function as a fixed gain amplifier. The gain selection is determined by the GAIN SEL
bit (B3) While in the fixed gain mode the volume setting has no effect on the output. When a digital 1 is loaded
into B2 the output level is determined by the volume control bits. See Table 4 for volume settings.
MUTE FUNCTION
The LM4936 mutes the amplifier and DOCK outputs when a digital 1 is loaded in bit B1. Even while muted, the
LM4936 will amplify a system alert (beep) signal whose magnitude satisfies the BEEP DETECT circuitry. Loading
a digital 0 into B1 returns the LM4936 to normal operation.
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Figure 52. Headphone Sensing Circuit
HP SENSE FUNCTION ( Headphone In )
Applying a voltage between the VIH threshold shown in the graph found in the Typical Performance
Characteristics and VDD to the LM4936's HP SENSE control pin or loading a digital 1 into the HP Control bit (B4)
will change the output mode. The '+' outputs will change to be in phase with the '-' outputs instead of 180
degrees out of phase. This action mutes a bridged-connected load since the differential voltage across the load
is now close to 0V. The HP SENSE pin over rides the HP Control bit. See Table 2 for more info. Quiescent
current consumption is reduced when the IC is in this single-ended mode.
Figure 52 shows the implementation of the LM4936's headphone control function. With no headphones
connected to the headphone jack, the R1-R2 voltage divider sets the voltage applied to the HP SENSE pin at
approximately 50mV. This 50mV puts the LM4936 into bridged mode operation. The output coupling capacitor
blocks the amplifier's half supply DC voltage, protecting the headphones.
The HP SENSE threshold is set so the output signal cannot cause an output mode change. While the LM4936
operates in bridge mode, the DC potential across the load is essentially 0V. Connecting headphones to the
headphone jack disconnects the headphone jack contact pin from R2 and allows R1 to pull the HP SENSE pin
up to VDD through R4. This enables the headphone function and mutes the bridged speaker. The single-ended '-'
outputs then drive the headphones, whose impedance is in parallel with resistors R2 and R3. These resistors
have negligible effect on the LM4936's output drive capability since the typical impedance of headphones is 32Ω.
Figure 52 also shows the suggested headphone jack electrical connections. The jack is designed to mate with a
three-wire plug. The plug's tip and ring should each carry one of the two stereo output signals, whereas the
sleeve should carry the ground return. A headphone jack with one control pin contact is sufficient to drive the HPIN pin when connecting headphones.
GAIN SELECT FUNCTION (Bass Boost)
The LM4936 features selectable gain, using either internal or external feedback resistors. The GAIN SEL bit (B3)
controls which gain is selected. Loading a digital 0 into the GAIN SEL bit sets the gain to internal resulting in a
gain of 6dB for BTL mode or unity for singled-ended mode. Loading a digital 1 into the GAIN SEL bit sets the
gain to be determined by the external resistors, RI and RF.
In some cases a designer may want to improve the low frequency response of the bridged amplifier or
incorporate a bass boost feature. This bass boost can be useful in systems where speakers are housed in small
enclosures. A resistor, RBS, and a capacitor, CBS, in parallel, can be placed in series with the feedback resistor of
the bridged amplifier as seen in Figure 3.
At low, frequencies CBS is a virtual open circuit and at high frequencies, its nearly zero ohm impedance shorts
RBS. The result is increased bridge-amplifier gain at low frequencies. The combination of RBS and CBS form a 6dB corner frequency at
fC = 1/(2πRBSCBS)
(9)
The bridged-amplifier low frequency differential gain is:
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AVD = 2(RF + RBS) / Ri
(10)
Using the component values shown in Figure 3 (RF = 20kΩ, RBS = 20kΩ, and CBS = 0.068µF), a first-order, -6dB
pole is created at 120Hz. Assuming R i = 20kΩ, the low frequency differential gain is 4V/V or 12dB. The input (Ci)
and output (COUT) capacitor values must be selected for a low frequency response that covers the range of
frequencies affected by the desired bass-boost operation.
VOLUME CONTROL
The LM4936 has an internal stereo volume control whose setting is a function of the digital values in the V4 – V0
bits. See Table 4.
The LM4936 volume control consists of 31 steps that are individually selected. The range of the steps, are from
0dB - 78dB. The gain levels are 1dB/step from 0dB to -6dB, 2dB/step from -6dB to -36dB, 3dB/step from -36dB
to -47dB, 4dB/step from -47dB to -51dB, 5dB/step from -51dB to -66dB, and 12dB to the last step at -78dB.
Table 4. Volume Control Table
24
Serial Number
V4
V3
V2
V1
V0
Gain (dB)
0
0
0
0
0
0
–90
1
0
0
0
0
1
–90
2
0
0
0
1
0
–68
3
0
0
0
1
1
–63
4
0
0
1
0
0
–57
5
0
0
1
0
1
–51
6
0
0
1
1
0
–47
7
0
0
1
1
1
–45
8
0
1
0
0
0
–42
9
0
1
0
0
1
–39
10
0
1
0
1
0
–36
11
0
1
0
1
1
–34
12
0
1
1
0
0
–32
13
0
1
1
0
1
–30
14
0
1
1
1
0
–28
15
0
1
1
1
1
–26
16
1
0
0
0
0
–24
17
1
0
0
0
1
–22
18
1
0
0
1
0
–20
19
1
0
0
1
1
–18
20
1
0
1
0
0
–16
21
1
0
1
0
1
–14
22
1
0
1
1
0
–12
23
1
0
1
1
1
–10
24
1
1
0
0
0
–8
25
1
1
0
0
1
–6
26
1
1
0
1
0
–5
27
1
1
0
1
1
–4
28
1
1
1
0
0
–3
29
1
1
1
0
1
–2
30
1
1
1
1
0
–1
31
1
1
1
1
1
0
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SNAS269A – APRIL 2005 – REVISED APRIL 2013
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8Ω Load
The following are the desired operational parameters:
Power Output:
1 WRMS
Load Impedance:
8Ω
Input Level:
1 VRMS
Input Impedance:
20 kΩ
Bandwidth:
100 Hz−20 kHz ± 0.25 dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way, using Equation 10, is to calculate the peak output voltage
necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout
voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result obtained by Equation 10. The result is Equation 11.
(11)
(12)
VDD ≥ (VOUTPEAK+ (VODTOP + VODBOT))
The Output Power vs Supply Voltage graph for an 8Ω load indicates a minimum supply voltage of 4.6V. This is
easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom,
allowing the LM4936 to produce peak output power in excess of 1W without clipping or other audible distortion.
The choice of supply voltage must also not create a situation that violates of maximum power dissipation as
explained above in the POWER DISSIPATION section.
After satisfying the LM4936's power dissipation requirements, the minimum differential gain needed to achieve
1W dissipation in an 8Ω load is found using Equation 12.
(13)
Thus, a minimum overall gain of 2.83 allows the LM4936's to reach full output swing and maintain low noise and
THD+N performance.
The last step in this design example is setting the amplifier's −6dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB desired limit. The results are
an
fL = 100Hz/5 = 20Hz
(14)
and an
fH = 20kHz x 5 = 100kHz
(15)
As mentioned in the SELECTING PROPER EXTERNAL COMPONENTS section, Ri (Right & Left) and Ci (Right
& Left) create a highpass filter that sets the amplifier's lower bandpass frequency limit. Find the input coupling
capacitor's value using Equation 14.
Ci≥ 1/(2πRifL)
(16)
The result is
1/(2π*20kΩ*20Hz) = 0.397μF
(17)
Use a 0.39μF capacitor, the closest standard value.
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The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD,
determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth
product (GBWP) is 300kHz. This is less than the LM4936's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance,restricting bandwidth
limitations.
SPI TIMING DIAGRAM
SPI OPERATIONAL REQUIREMENTS
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (tCH ) after the rising edge of CLK, and CLK must remain logiclow for at least 100ns (tCL ) after the falling edge of CLK.
3. Data bits are written to the DATA pin with the most significant bit (MSB) first.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 50ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 50ns (tDH) after the
rising edge of CLK and stabilize before the next rising edge of CLK.
5. ENABLE should be logic-low only during serial data transmission.
6. ENABLE must be logic-low at least 50ns (tES ) before the first rising edge of CLK, and ENABLE has to
remain logic-low at least 50ns (tEH ) after the eighth rising edge of CLK.
7. If ENABLE remains logic-high for more than 50ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ENABLE is logic-low for more than 8 CLK pulses then only the first 8 data bits will be latched and activated
at rising edge of eighth CLK.
9. ENABLE must remain logic-high for at least 50ns (tEL ).
10. Coincidental rising or falling edges of CLK and ENABLE are not allowed. If CLK is to be held logic-high after
the data transmission, the falling edge of CLK must occur at least 50ns (tCS ) before ENABLE transitions to
logic-low for the next set of data.
I2C TIMING DIAGRAMS
Figure 53. I2C Bus Format
26
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Figure 54. I2C Timing Diagram
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LM4936
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LM4936 MH HTSSOP Board Artwork (1) (2)
(1)
(2)
28
Composite View
Silk Screen
Top Layer
Internal Layer 1
Internal Layer 2
Bottom Layer
When driving 3Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board and forced-air cooled. The demo board
shown in the datasheet has planes for heat sinking. The top layer plane is 1.05 in2 (675mm2), the inner two layers each have a 1.03 in2
(667mm2) plane and the bottom layer has a 3.32 in2 (2143mm2) plane. The planes are electrically GND and interconnected through six
15 mil vias directly under the package and eight 28 mil vias in various locations.
When driving 4Ω loads from a 5V supply the LM4936MH must be mounted to the circuit board. The demo board shown in the datasheet
has planes for heat sinking. The top layer plane is 1.05 in2 (675mm2), the inner two layers each have a 1.03 in2 (667mm2) plane and the
bottom layer has a 3.32 in2 (2143mm2) plane. The planes are electrically GND and interconnected through six 15 mil vias directly under
the package and eight 28 mil vias in various locations.
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SNAS269A – APRIL 2005 – REVISED APRIL 2013
Table 5. LM4936 Board Bill of Materials
Designator
Value
Tolerance
Part Description
RIN1, RIN2
20kΩ
1%
1/10W, 0805 Resistor
RI1, RI2
20kΩ
1%
1/10W, 0805 Resistor
RF1, RF2
20kΩ
1%
1/10W, 0805 Resistor
RDOCK1, RDOCK2
20kΩ
1%
1/10W, 0805 Resistor
RBS1, RBS2
20kΩ
1%
1/10W, 0805 Resistor
RBEEP1, RBEEP2
200kΩ
1%
1/10W, 0805 Resistor
RL1, RL2
1.5kΩ
1%
1/10W, 0805 Resistor
RS, RPU
100kΩ
1%
1/10W, 0805 Resistor
CIN1, CIN2, CIN3
0.33μF
10%
10V, Ceramic 1206 Capacitor
CBS1, CBS2
0.068μF
10%
10V, Ceramic 1206 Capacitor
CS1
10μF
10%
10V, Tantalum 1210 Capacitor
CS2, CS3, CS4
0.1μF
10%
10V, Tantalum 1206 Capacitor
CO1, CO2
1μF
10%
10V, Electrolytic 1210 Capacitor
CB
1μF
10%
10V, Tantalum 1210 Capacitor
COUT1, COUT2
220μF
10%
16V, Electrolytic 2220 Capacitor
Comment
J1
0.100 1x2 header, vertical mount
Docking Outputs
J2, J3, J4
RCA Input Jack, PCB Mount
Mouser: 16PJ097
J5A
Banana-Jack Red, Analog VDD
Mouser: 164–6219
J5B
Banana-Jack Blck, GND
Mouser: 164–6218
J6A
Banana-Jack Red, Right Out +
Mouser: 164–6219
J6B
Banana-Jack Black, Right Out -
Mouser: 164–6218
J7A
Banana-Jack Red, Left Out +
Mouser: 164–6219
J7B
Banana-Jack Black, Left Out -
Mouser: 164–6218
J8
0.100” 2x3 header, vertical mount
I2C/SPI Inputs
J9
3.5mm Stereo Headphone Jack
Shogyo: SJS–0354–5P
J10
0.100” 1x3 header, vertical mount
Digital Select
J11
Banana Jack — Red, Digital VDD
Mouser: 164–6219
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LM4936
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
30
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 29
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM4936MH/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM4936MH
LM4936MHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM4936MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM4936MHX/NOPB
Package Package Pins
Type Drawing
SPQ
HTSSOP
2500
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.8
B0
(mm)
K0
(mm)
P1
(mm)
10.2
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4936MHX/NOPB
HTSSOP
PWP
28
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0028A
PowerPAD TM - 1.1 mm max height
SCALE 1.800
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
A
SEATING PLANE
PIN 1 ID
AREA
28
1
9.8
9.6
NOTE 3
0.1 C
26X 0.65
2X
8.45
14
B
15
4.5
4.3
NOTE 4
0.30
0.19
0.1
C A
28X
1.1 MAX
B
0.20
TYP
0.09
SEE DETAIL A
3.15
2.75
0.25
GAGE PLANE
5.65
5.25
THERMAL
PAD
0 -8
0.10
0.02
0.7
0.5
(1)
DETAIL A
TYPICAL
4214870/A 10/2014
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-153, variation AET.
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EXAMPLE BOARD LAYOUT
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
(3)
SOLDER
MASK
OPENING
28X (1.5)
28X (0.45)
SOLDER MASK
DEFINED PAD
1
28X (0.45)
28X (1.3)
28
26X
(0.65)
SYMM
(5.5)
(9.7)
SOLDER
MASK
OPENING
(1.3) TYP
14
15
( 0.2) TYP
VIA
(1.3)
SEE DETAILS
SYMM
(0.9) TYP
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214870/A 10/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.127 THICK
STENCIL
28X (1.5)
28X (0.45)
METAL COVERED
BY SOLDER MASK
1
28X (1.3)
28
26X (0.65)
28X (0.45)
(5.5)
BASED ON
0.127 THICK
STENCIL
SYMM
14
15
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SYMM
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.127
0.152
0.178
3.55 X 6.37
3.0 X 5.5 (SHOWN)
2.88 X 5.16
2.66 X 4.77
4214870/A 10/2014
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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