High Voltage, Latch-Up Proof, 4-Channel Multiplexer ADG5204 FEATURES FUNCTIONAL BLOCK DIAGRAM Latch-up proof 3 pF off source capacitance 26 pF off drain capacitance −0.6 pC charge injection Low leakage: 0.4 nA maximum at 85°C ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range ADG5204 S1 S2 D S3 S4 A0 A1 EN 09768-001 1 OF 4 DECODERS Figure 1. APPLICATIONS Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG5204 is a complementary metal oxide semiconductor (CMOS) analog multiplexer, comprising four single channels. 1. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed together with high signal bandwidth make the ADG5204 suitable for video signal switching. 2. 3. The ADG5204 is designed on a trench process, which guards against latch-up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 4. The ADG5204 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. 5. 6. Trench Isolation Guards Against Latch-Up. A dielectric trench separates the P and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. Ultralow Capacitance and <1 pC Charge Injection. Dual-Supply Operation. For applications where the analog signal is bipolar, the ADG5204 can be operated from dual supplies up to ±22 V. Single-Supply Operation. For applications where the analog signal is unipolar, the ADG5204 can be operated from a single rail power supply up to 40 V. 3 V Logic-Compatible Digital Inputs. VINH = 2.0 V, VINL = 0.8 V. No VL Logic Power Supply Required. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADG5204 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................8 Applications....................................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ............................9 General Description ......................................................................... 1 Truth Table .....................................................................................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Test Circuits..................................................................................... 14 Specifications..................................................................................... 3 Terminology .................................................................................... 16 ±15 V Dual Supply ....................................................................... 3 Trench Isolation.............................................................................. 17 ±20 V Dual Supply ....................................................................... 4 Applications Information .............................................................. 18 12 V Single Supply........................................................................ 5 Outline Dimensions ....................................................................... 19 36 V Single Supply........................................................................ 6 Ordering Guide .......................................................................... 19 Continuous Current per Channel, Sx or D............................... 7 REVISION HISTORY 5/11—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG5204 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 160 200 4.5 8 38 50 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V max Ω typ Ω max Ω typ VS = ±10 V, IS = −1 mA, see Figure 24 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −1 mA 250 280 9 10 65 70 tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD nA typ ISS 0.2 0.4 nA max nA typ 0.1 0.02 0.2 0.4 1.2 VS = VD = ±10 V, see Figure 26 0.5 1.2 nA max nA typ nA max V min V max μA typ μA max pF typ VIN = VGND or VDD 2.0 0.8 0.002 3 175 230 155 205 150 175 80 285 320 255 285 200 215 −0.6 −80 −80 136 −6.8 3 26 30 45 55 0.001 VDD/VSS 1 VS = VS = ±10 V, VD = ∓10 V, see Figure 23 0.1 0.01 30 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD VS = ±10 V, IS = −1 mA VDD = +16.5 V, VSS = −16.5 V 0.01 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Ω max Ω typ Ω max 70 1 ±9/±22 Guaranteed by design; not subject to production test. Rev. 0 | Page 3 of 20 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ μA typ μA max μA typ μA max V min/max VS = VS = ±10 V, VD = ∓10 V, see Figure 23 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 29 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V, see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V ADG5204 ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) 25°C 140 160 4.5 8 33 45 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V max Ω typ Ω max Ω typ VS = ±15 V, IS = −1 mA, see Figure 24 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −1 mA 200 230 9 10 55 60 Ω max Ω typ Ω max VS = ±15 V, IS = −1 mA nA typ VS = ±15 V, VD = ∓15 V, see Figure 23 LEAKAGE CURRENTS Source Off Leakage, IS (Off) 0.01 0.1 0.01 0.2 0.4 Drain Off Leakage, ID (Off) nA max nA typ 0.1 0.02 0.2 0.4 1.2 VS = VD = ±15 V, see Figure 26 0.5 1.2 nA max nA typ nA max V min V max μA typ μA max pF typ VIN = VGND or VDD Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH VDD = +22 V, VSS = −22 V 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 Break-Before-Make Time Delay, tD 160 215 150 185 150 175 75 Charge Injection, QINJ Off Isolation −0.6 −80 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ −80 150 −6 3 26 30 dB typ MHz typ dB typ pF typ pF typ pF typ tON (EN) tOFF (EN) 260 290 225 255 195 210 30 Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD ISS 50 70 0.001 VDD/VSS 1 110 1 ±9/±22 Guaranteed by design; not subject to production test. Rev. 0 | Page 4 of 20 μA typ μA max μA typ μA max V min/max VS = ±15 V, VD = ∓15 V, see Figure 23 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 29 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V, see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz, see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V ADG5204 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 340 500 5 20 145 280 0.01 0.1 0.01 0.1 0.02 0.2 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V max Ω typ Ω max Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 24 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −1 mA 610 700 21 22 335 370 0.2 0.4 0.4 1.2 0.5 1.2 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 3 240 350 250 335 160 195 140 445 515 420 485 220 240 60 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD −1.2 −80 −80 106 −11 3.5 29 33 40 VDD 1 65 9/40 Guaranteed by design; not subject to production test. Rev. 0 | Page 5 of 20 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ μA typ μA max V min/max VS = 0 V to 10 V, IS = −1 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 23 VS = VD = 1 V/10 V, see Figure 26 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 29 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V, see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V ADG5204 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 150 170 4.5 8 35 50 0.01 0.1 0.01 0.1 0.02 0.2 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V max Ω typ Ω max Ω typ VS = 0 V to 30 V, IS = −1 mA, see Figure 24 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −1 mA 215 245 9 10 60 65 0.2 0.4 0.4 1.2 0.5 1.2 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD 3 180 250 170 220 170 210 80 275 305 251 285 215 220 30 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD −0.6 −80 −80 136 −6.7 3 26 30 85 100 VDD 1 130 9/40 Guaranteed by design; not subject to production test. Rev. 0 | Page 6 of 20 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ μA typ μA max V min/max VS = 0 V to 30 V, IS = −1 mA VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23 VS = 1 V/30 V, VD = 30 V/1 V, see Figure 23 VS = VD = 1 V/30 V, see Figure 26 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 29 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V, see Figure 30 VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, see Figure 27 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 27 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V ADG5204 CONTINUOUS CURRENT PER CHANNEL, Sx OR D Table 5. Parameter CONTINUOUS CURRENT, Sx OR D PINS VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 24.5 35.7 7.5 7.7 2.8 2.8 mA max mA max 26 37 7.5 7.7 2.8 2.8 mA max mA max 18 28 7 7.7 2.8 2.8 mA max mA max 30 41 7.7 7.7 2.8 2.8 mA max mA max Rev. 0 | Page 7 of 20 ADG5204 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, Sx or D Pins Continuous Current, Sx or D 2 Operating Temperature Range Storage Temperature Range Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP, θJA Thermal Impedance (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free 1 2 Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 81 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% −40°C to +125°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 112.6°C/W 30.4°C/W 260(+0/−5)°C Overvoltages at the Sx and D pins are clamped by internal diodes. Limit current to the maximum ratings given. See Table 5. Rev. 0 | Page 8 of 20 ADG5204 14 A1 13 NC 16 EN 15 A0 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A0 1 14 A1 EN 2 13 GND VSS 3 12 VDD S1 4 11 S3 NC 2 ADG5204 11 VDD S2 5 10 S4 S1 3 TOP VIEW (Not to Scale) 10 S3 D 6 9 NC S2 4 NC 7 8 NC 12 GND NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 2. TSSOP Pin Configuration 09768-003 NC 7 S4 NC 8 9 D 6 NC = NO CONNECT VSS 1 NC 5 TOP VIEW (Not to Scale) 09768-002 ADG5204 Figure 3. LFCSP Pin Configuration Table 7. Pin Function Descriptions TSSOP 1 2 3 4 5 6 7 to 9 10 11 12 13 14 N/A1 1 Pin No. LFCSP 15 16 Mnemonic A0 EN 1 3 4 6 2, 5, 7, 8, 13 9 10 11 12 14 EP Description Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. Most Negative Power Supply Potential. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. No Connect. These pins are open. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. VSS S1 S2 D NC S4 S3 VDD GND A1 Exposed Pad N/A means not applicable. TRUTH TABLE Table 8. EN 0 1 1 1 1 1 A1 X1 0 0 1 1 A0 X1 0 1 0 1 S1 Off On Off Off Off X is don’t care. Rev. 0 | Page 9 of 20 S2 Off Off On Off Off S3 Off Off Off On Off S4 Off Off Off Off On ADG5204 TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C 140 VDD = +18V VSS = –18V ON RESISTANCE (Ω) 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 0 0 TA = 25°C 5 10 15 20 25 30 35 40 VS, VD (V) Figure 4. RON as a Function of VD or VS, Dual Supply 250 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 0 –25 VDD = 32.4V VSS = 0V 120 09768-104 ON RESISTANCE (Ω) 120 TA = 25°C 140 09768-107 160 Figure 7. RON as a Function of VD or VS, Single Supply 250 VDD = +9V VSS = –9V 200 VDD = +15V VSS = –15V 200 ON RESISTANCE (Ω) 150 VDD = +13.2V VSS = –13.2V 100 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V 100 TA = –40°C 50 –15 –10 –5 0 5 10 15 20 VS, VD (V) 0 –15 09768-105 0 –20 500 0 5 10 15 Figure 8. RON as a Function of VD or VS, for Different Temperatures, ±15 V Dual Supply VDD = 9V VSS = 0V 180 VDD = 10.8V VSS = 0V 400 160 300 ON RESISTANCE (Ω) VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V 350 250 200 150 140 TA = +25°C 80 TA = –40°C 60 20 6 8 10 12 VS, VD (V) 14 09768-106 50 4 TA = +85°C 100 40 0 TA = +125°C 120 100 2 –5 200 TA = 25°C 450 0 –10 VS, VD (V) Figure 5. RON as a Function of VD or VS, Dual Supply ON RESISTANCE (Ω) TA = +25°C 09768-108 50 TA = +85°C 150 VDD = +20V VSS = –20V 0 –20 –15 –10 –5 0 5 10 15 20 VS, VD (V) Figure 9. RON as a Function of VD or VS, for Different Temperatures, ±20 V Dual Supply Figure 6. RON as a Function of VD or VS, Single Supply Rev. 0 | Page 10 of 20 09768-109 ON RESISTANCE (Ω) TA = +125°C ADG5204 100 500 I I (ON) + + IS (OFF) + – D, S TA = +125°C 340 TA = +85°C 50 300 TA = +25°C 250 200 TA = –40°C 150 100 0 IS (OFF) – + –50 ID (OFF) + – –100 ID, IS (ON) – – –150 50 VDD = 12V VSS = 0V 0 2 4 6 8 10 12 VS, VD (V) 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 10. RON as a Function of VD or VS for Different Temperatures, 12 V Single Supply 250 VDD = +20V VSS = –20V VBIAS = +15V/–15V –200 09768-110 0 ID (OFF) – + 09768-113 400 LEAKAGE CURRENT (pA) ON RESISTANCE (Ω) 450 Figure 13. Leakage Current vs. Temperature, ±20 V Dual Supply 40 VDD = 36V VSS = 0V IS (OFF) + – ID (OFF) – + 20 LEAKAGE CURRENT (pA) ON RESISTANCE (Ω) 200 TA = +125°C 150 TA = +85°C TA = +25°C 100 TA = –40°C 0 IS (OFF) – + –20 ID, IS (ON) + + –40 ID (OFF) + – –60 ID, IS (ON) – – –80 5 10 15 20 25 30 35 VS, VD (V) ID (OFF) – + ID, IS (ON) + + 50 IS (OFF) + – ID (OFF) – + LEAKAGE CURRENT (pA) IS (OFF) – + ID (OFF) + – ID, IS (ON) – – –30 –40 –50 120 ID, IS (ON) + + IS (OFF) + – –50 IS (OFF) – + –100 ID (OFF) + – –150 –200 60 80 100 120 TEMPERATURE (°C) 09768-112 LEAKAGE CURRENT (pA) 100 0 –10 –60 VDD = +15V VSS = –15V VBIAS = +10V/–10V –70 0 20 40 80 Figure 14. Leakage Current vs. Temperature, 12 V Single Supply 0 –20 60 TEMPERATURE (°C) Figure 11. RON as a Function of VD or VS for Different Temperatures, 36 V Single Supply 10 40 Figure 12. Leakage Current vs. Temperature, ±15 V Dual Supply ID, IS (ON) – – VDD = 36V VSS = 0V VBIAS = 1V/30V –250 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 15. Leakage Current vs. Temperature, 36 V Single Supply Rev. 0 | Page 11 of 20 09768-115 0 09768-111 0 –100 VDD = 12V VSS = 0V VBIAS = 1V/10V –120 0 20 09768-114 50 ADG5204 300 250 –60 200 150 VDD = +15V VSS = –15V –80 VDD = +20V VSS = –20V 100 –100 50 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 –40 09768-116 –120 10k 0 20 40 60 80 100 120 Figure 19. Transition Time vs. Temperature 0 TA = 25°C VDD = +15V VSS = –15V TA = 25°C VDD = +15V VSS = –15V –20 –40 –40 ACPSRR (dB) CROSSTALK (dB) –20 –20 TEMPERATURE (°C) Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply 0 VDD = +36V VSS = 0V VDD = +12V VSS = 0V –40 TIME (ns) OFF ISOLATION (dB) –20 350 TA = 25°C VDD = +15V VSS = –15V 09768-120 0 BETWEEN S1 AND S2 –60 NO DECOUPLING CAPACITORS –60 –80 –80 BETWEEN S1 AND S4 –100 –100 –120 10k –120 1k 1M 10M 100M 1G FREQUENCY (Hz) VDD = +20V VSS = –20V 35 CAPACITANCE (pF) 0.5 VDD = +36V VSS = 0V VDD = +12V VSS = 0V –0.5 –1.0 DRAIN OFF 25 20 15 10 –1.5 –10 0 10 20 30 VS (V) 40 0 –15 –10 –5 0 5 10 VS (V) Figure 21. Capacitance vs. Source Voltage, Dual Supply Figure 18. Charge Injection vs. Source Voltage Rev. 0 | Page 12 of 20 15 09768-123 –2.5 –20 SOURCE OFF 5 –2.0 09768-119 CHARGE INJECTION (pC) SOURCE/DRAIN ON 30 1.0 0 10M TA = 25°C VDD = +15V VSS = –15V 1.5 VDD = +15V VSS = –15V 1M Figure 20. ACPSRR vs. Frequency, ±15 V Dual Supply 40 TA = 25°C 2.0 100k FREQUENCY (Hz) Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply 2.5 10k 09768-121 100k 09768-117 DECOUPLING CAPACITORS ADG5204 0 TA = 25°C –2 VDD = +15V VSS = –15V –6 –8 –10 –12 –14 –16 –18 –20 100k 1M 10M FREQUENCY (Hz) 100M 1G 09768-125 ATTENUATION (dB) –4 Figure 22. Bandwidth Rev. 0 | Page 13 of 20 ADG5204 TEST CIRCUITS A Sx D ID (OFF) NC VD 09768-006 VS ID (ON) A Sx D A VD NC = NO CONNECT Figure 23. Off Leakage 09768-007 IS (OFF) Figure 26. On Leakage VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx VS D V Sx RL 50Ω GND D VOUT 09768-005 VOUT WITH SWITCH VOUT WITHOUT SWITCH INSERTION LOSS = 20 log Figure 27. Bandwidth Figure 24. On Resistance VDD VSS VDD 09768-009 IDS VS VSS 0.1µF 0.1µF 0.1µF 0.1µF VDD NETWORK ANALYZER NETWORK ANALYZER VSS VOUT 50Ω Sx 50Ω VDD S1 VSS RL 50Ω D S2 VS RL 50Ω D VOUT VS VS GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 25. Off Isolation VOUT VS Figure 28. Channel-to-Channel Crosstalk Rev. 0 | Page 14 of 20 09768-010 OFF ISOLATION = 20 log VOUT 09768-008 RL 50Ω GND ADG5204 VDD VSS 0.1µF VDD VSS S1 A1 S2 A0 S3 S4 VIN 2.4V EN GND 3V ADDRESS DRIVE (VIN) VS1 VS4 50% VOUT tTRANSITION CL 35pF RL 300Ω 90% 90% VOUT D 50% 0V 09768-012 0.1µF tTRANSITION Figure 29. Address to Output Switching Times VIN 300Ω 2.4V 0.1µF VDD VSS S1 S2 S3 S4 EN VOUT D GND 0V VOUT CL 35pF RL 300Ω 3V ADDRESS DRIVE (VIN) VS1 A1 A0 80% 80% 09768-013 0.1µF VDD VSS tD Figure 30. Break-Before-Make Time Delay, tD VDD VSS 0.1µF VDD VSS S1 A1 S2 A0 S3 S4 EN VS 3V 50% VOUT VOUT D RL 300Ω 300Ω 50% 0V 0.9VOUT OUTPUT 0.1VOUT 0V CL 35pF tON (EN) tOFF (EN) Figure 31. Enable-to-Output Switching Delay VDD VSS VDD VSS Sx D VOUT RS VS DECODER ∆VOUT QINJ = CL × ∆VOUT VOUT VIN CL 1nF SW OFF SW OFF SW ON GND VIN A1 A2 SW OFF SW OFF 09768-015 VIN GND ENABLE DRIVE (VIN) 09768-014 0.1µF EN Figure 32. Charge Injection Rev. 0 | Page 15 of 20 ADG5204 TERMINOLOGY IDD The positive supply current. CIN The digital input capacitance. ISS The negative supply current. tTRANSITION The delay time between the 50% and 90% points of the digital input and switch-on condition when switching from one address state to another. VD, VS The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 31. tOFF (EN) The delay between applying the digital control input and the output switching off. See Figure 31. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (On) The channel leakage current with the switch on. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINL The maximum input voltage for Logic 0. Bandwidth The frequency at which the output is attenuated by 3 dB. VINH The minimum input voltage for Logic 1. On Response The frequency response of the on switch. IINL, IINH The input current of the digital input. Insertion Loss The loss due to the on resistance of the switch. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD (On), CS (On) The on switch capacitance, which is measured with reference to ground. ACPSRR (AC Power Supply Rejection Ratio) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pins to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. Rev. 0 | Page 16 of 20 ADG5204 TRENCH ISOLATION In the ADG5204, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P WELL N WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 33. Trench Isolation Rev. 0 | Page 17 of 20 09768-004 In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. By using trench isolation, this diode is removed, and the result is a latch-up proof switch. NMOS ADG5204 APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5204 high voltage multiplexer allows single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. Rev. 0 | Page 18 of 20 ADG5204 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 34. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 08-16-2010-C TOP VIEW Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG5204BRUZ ADG5204BRUZ-RL7 ADG5204BCPZ-RL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. 0 | Page 19 of 20 Package Option RU-14 RU-14 CP-16-17 ADG5204 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09768-0-5/11(0) Rev. 0 | Page 20 of 20