CY62146DV30 4-Mbit (256K x 16) Static RAM Features an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). • Very high speed: 45 ns • Wide voltage range: 2.20V–3.60V • Pin-compatible with CY62146CV30 • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). — Typical active current: 8 mA @ f = fmax • Ultra low standby power • Easy memory expansion with CE, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. • Packages offered 48-ball BGA and 44-pin TSOPII • Also available in Lead-free packages Functional Description[1] The CY62146DV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has The CY62146DV30 is available in a 48-ball VFBGA, 44-pin TSOPII packages. Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 BHE WE CE OE BLE A17 A13 A14 A15 A16 A11 A12 COLUMN DECODER Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05339 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 2, 2005 CY62146DV30 Pin Configuration[2, 3, 4] VFBGA (Top View) 44 TSOP II (Top View) 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 H 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Operating ICC (mA) VCC Range (V) Product CY62146DV30L f = 1MHz f = fmax Standby ISB2 (µA) Min. Typ.[5] Max. Speed (ns) Typ.[5] Max. Typ.[5] Max. Typ.[5] Max. 2.20V 3.0 3.60 45 1.5 3 10 20 2 12 CY62146DV30LL CY62146DV30L 8 2.20V 3.0 3.60 55 1.5 3 8 15 2 CY62146DV30LL CY62146DV30L 12 8 2.20V 3.0 3.60 70 1.5 3 8 15 2 CY62146DV30LL 12 8 Notes: 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating or tied to VSS to ensure proper application. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05339 Rev. *A Page 2 of 11 CY62146DV30 DC Input Voltage[6, 7] ..................... –0.3V to VCC(MAX) + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Supply Voltage to Ground Potential ......................................–0.3V to + VCC(MAX) + 0.3V Device DC Voltage Applied to Outputs in High-Z State[6, 7] .........................–0.3V to VCC(MAX) + 0.3V Ambient Temperature (TA) Range CY62146DV30L VCC[8] Industrial –40°C to +85°C 2.20V to 3.60V CY62146DV30LL Electrical Characteristics Over the Operating Range CY62146DV30-45 Parameter Description VOH VOL VIH VIL Test Conditions Output HIGH IOH = –0.1 mA VCC = 2.20V Voltage IOH = –1.0 mA VCC = 2.70V Min. Typ.[5] Input LOW Voltage CY62146DV30-55 Min. Typ.[5] Max. CY62146DV30-70 Min. Typ.[5] Max. Unit 2.0 2.0 2.0 V 2.4 2.4 2.4 V Output LOW IOL = 0.1 mA VCC = 2.20V Voltage IOL = 2.1 mA VCC = 2.70V Input HIGH Voltage Max. 0.4 0.4 0.4 V 0.4 0.4 0.4 V VCC = 2.2V to 2.7V 1.8 VCC + 0.3V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 –0.3 0.6 V VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 –0.3 0.8 V IIX Input Leakage GND < VI < VCC Current –1 +1 –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 –1 +1 µA ICC VCC Operating Supply Current f = fMAX = 1/tRC Automatic CE Power-down Current — CMOS Inputs ISB1 ISB2 10 20 8 15 8 15 mA 1.5 3 1.5 3 1.5 3 mA CE > VCC−0.2V, L VIN>VCC–0.2V, VIN<0.2V) LL f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60V 2 12 2 12 2 12 µA CE > VCC – 0.2V, Automatic L CE VIN > VCC – 0.2V or VIN < LL Power-down 0.2V, Current — f = 0, VCC = 3.60V CMOS Inputs 2 f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels 8 12 8 2 12 8 8 8 2 12 µA 8 Notes: 6. VIL(min.) = –2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 8. Full device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. Document #: 38-05339 Rev. *A Page 3 of 11 CY62146DV30 Capacitance (for all packages)[9] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VCC = VCC(typ) Unit 10 pF 10 pF Thermal Resistance[9] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions BGA TSOP II Unit 72 75.13 °C/W 8.86 8.95 °C/W Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms[10] R1 VCC OUTPUT 50 pF ALL INPUT PULSES 90% 90% 10% VCC R2 10% GND Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.50V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current Typ.[5] Max. Unit L 9 µA LL 6 Conditions Min. 1.5 VCC= 1.5V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V tCDR[9] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time V 0 ns tRC ns Data Retention Waveform VCC VCC(min) DATA RETENTION MODE VDR > 1.5 V tCDR VCC(min) tR CE Notes: 9. Tested initially and after any design or process changes that may affect these parameters. 10. Test condition for the 45 ns part is a load capacitance of 30 pF. 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05339 Rev. *A Page 4 of 11 CY62146DV30 Switching Characteristics Over the Operating Range [12] 45 ns[10] Parameter Description Min. Max. 55 ns Min. 70 ns Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 70 ns tDOE OE LOW to Data Valid 25 25 35 ns 25 ns 45 [13] tLZOE OE LOW to LOW Z tHZOE OE HIGH to High Z[13, 14] tLZCE CE LOW to Low Z[13] tHZCE CE HIGH to High 55 10 55 10 5 10 ns 10 20 ns 25 tPU CE LOW to Power-Up CE HIGH to Power-Down 45 55 70 ns tDBE BLE/BHE LOW to Data Valid 25 25 35 ns tLZBE tHZBE BLE/BHE LOW to Low BLE/BHE HIGH to HIGH 10 Z[13, 14] 0 ns tPD Z[13] 0 ns ns 5 10 0 70 20 20 ns 10 5 15 Z[13, 14] 70 10 15 ns 10 20 ns 25 ns Write Cycle[15] tWC Write Cycle Time 45 55 70 ns tSCE CE LOW to Write End 40 40 60 ns tAW Address Set-up to Write End 40 40 60 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 35 40 45 ns tBW BLE/BHE LOW to Write End 40 40 60 ns tSD Data Set-up to Write End 25 25 30 ns tHD Data Hold from Write End 0 0 0 ns tHZWE tLZWE WE LOW to High-Z[13, 14] [13] WE HIGH to Low-Z 15 10 20 10 25 10 ns ns Notes: 12. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05339 Rev. *A Page 5 of 11 CY62146DV30 Switching Waveforms Read Cycle 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled)[17, 18] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE and BHE, BLE transition LOW. Document #: 38-05339 Rev. *A Page 6 of 11 CY62146DV30 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[15, 19, 20] tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 21 tHZOE Write Cycle No. 2 (CE Controlled)[15, 19, 20] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 21 tHZOE Notes: 19. Data I/O is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 21. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05339 Rev. *A Page 7 of 11 CY62146DV30 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[20] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 21 tHD DATAIN tHZWE tLZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 21 tSD tHD DATAIN tLZWE Document #: 38-05339 Rev. *A Page 8 of 11 CY62146DV30 Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (ISB) L X X H H High Z Output Disabled Active (ICC) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62146DV30LL-45BVI Package Name BV48A CY62146DV30LL-45BVXI 55 Package Type 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) CY62146DV30LL-45ZSXI ZS-44 44-pin TSOP II (Pb-free) CY62146DV30L-55BVI BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) CY62146DV30L-55BVXI Industrial 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) CY62146DV30LL-55BVI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) CY62146DV30LL-55BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) CY62146DV30L-55ZSXI Operating Range ZS-44 44-pin TSOP II (Pb-free) BV48A 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) CY62146DV30LL-55ZSXI 70 CY62146DV30L-70BVI CY62146DV30L-70BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) CY62146DV30LL-70BVI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) CY62146DV30LL-70BVXI 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) CY62146DV30L-70ZSXI Industrial ZS-44 44-pin TSOP II (Pb-free) Industrial CY62146DV30LL-70ZSXI Document #: 38-05339 Rev. *A Page 9 of 11 CY62146DV30 Package Diagram 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 44-Pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05339 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62146DV30 Document History Page Document Title:CY62146DV30 MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 38-05339 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 213251 See ECN AJU New Data Sheet *A 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #10 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-lead TSOP-II package name on page 10 from Z44 to ZS44 Standardized Icc values across ‘L’ and ‘LL’ bins Document #: 38-05339 Rev. *A Page 11 of 11