IRF IRLHS6242PBF Hexfet power mosfet Datasheet

PD - 97582B
IRLHS6242PbF
HEXFET® Power MOSFET
±12
RDS(on) max
11.7
mΩ
(@VGS = 4.5V)
RDS(on) max
D
6
A
G
'
(@TC (Bottom) = 25°C)
d
6
12
*
ID
mΩ
'
(@VGS = 2.5V)
D
D
'
15.5
D
'
VGS
V
V
:
,(
9
3
2
7
20
'
VDS
D
S
S
2mm x 2mm PQFN
Applications
• Charge and discharge switch for battery application
• System/Load Switch
Features and Benefits
Features
Low RDSon (≤ 11.7mΩ)
Low Thermal Resistance to PCB (≤ 13°C/W)
Low Profile (≤ 1.0mm)
Industry-Standard Pinout
Compatible with Existing Surface Mount Techniques
RoHS Compliant Containing no Lead, no Bromide and no Halogen
Orderable part number
Package Type
IRLHS6242TRPBF
IRLHS6242TR2PBF
PQFN 2mm x 2mm
PQFN 2mm x 2mm
results in
⇒
Resulting Benefits
Lower Conduction Losses
Enable better thermal dissipation
Increased Power Density
Multi-Vendor Compatibility
Easier Manufacturing
Environmentally Friendlier
Standard Pack
Form
Quantity
Tape and Reel
4000
Tape and Reel
400
Note
Absolute Maximum Ratings
Parameter
Max.
VDS
Drain-to-Source Voltage
20
VGS
±12
ID @ TA = 25°C
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 4.5V
ID @ TA = 70°C
Continuous Drain Current, VGS @ 4.5V
ID @ TC(Bottom) = 25°C
Continuous Drain Current, VGS @ 4.5V
Continuous Drain Current, VGS @ 4.5V
8.3
22
ID @ TC(Bottom) = 70°C
i
i
Continuous Drain Current, VGS @ 4.5V (Package Limited)
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
c
PD @TC(Bottom) = 25°C
g
Power Dissipation g
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
d
d
12d
18
A
88
1.98
g
V
10
IDM
ID @ TC(Bottom) = 25°C
Units
9.6
0.016
-55 to + 150
W
W/°C
°C
Notes  through ‡ are on page 2
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1
02/23/2011
IRLHS6242PbF
Static @ TJ = 25°C (unless otherwise specified)
Min.
Typ.
Drain-to-Source Breakdown Voltage
Parameter
20
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
6.8
9.4
–––
11.7
Gate Threshold Voltage
–––
0.5
12.4
0.8
15.5
1.1
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
-4.2
–––
–––
–––
1.0
150
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
100
-100
gfs
Qg
Qgs
Forward Transconductance
36
–––
–––
14
–––
–––
S
VDS = 10V, ID = 8.5A
VDS = 10V
Gate-to-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
–––
–––
1.5
6.3
–––
–––
nC
Qgd
VGS = 4.5V
ID = 8.5A (See Fig.17 & 18)
–––
–––
–––
2.1
5.8
15
–––
–––
–––
Ω
Turn-Off Delay Time
Fall Time
–––
–––
19
13
–––
–––
Input Capacitance
Output Capacitance
–––
–––
1110
260
–––
–––
Reverse Transfer Capacitance
–––
180
–––
Min.
Typ.
BVDSS
ΔΒVDSS/ΔTJ
RDS(on)
VGS(th)
ΔVGS(th)
IDSS
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
h
Total Gate Charge
Gate-to-Source Charge
h
h
Max. Units
V
Conditions
VGS = 0V, ID = 250μA
mV/°C Reference to 25°C, ID = 1mA
VGS = 4.5V, ID = 8.5A
mΩ
VGS = 2.5V, ID = 8.5A
V
VDS = VGS, ID = 10μA
mV/°C
VDS = 16V, VGS = 0V
μA
VDS = 16V, VGS = 0V, TJ = 125°C
ed
ed
nA
ns
pF
VGS = 12V
VGS = -12V
d
d
VDD = 10V, VGS = 4.5V
ID = 8.5A
d
e
RG=1.8Ω
See Fig.15
VGS = 0V
VDS = 10V
ƒ = 1.0MHz
Diode Characteristics
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
Qrr
ton
–––
Max. Units
–––
22
A
–––
c
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
Conditions
MOSFET symbol
88
–––
–––
1.2
V
–––
–––
15
12
23
18
ns
nC
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 8.5A , VGS = 0V
d
d
TJ = 25°C, IF = 8.5A , V
di/dt = 210A/μs e
DD
S
e
= 10V
Time is dominated by parasitic Inductance
Thermal Resistance
RθJC (Bottom)
RθJC (Top)
RθJA
RθJA (<10s)
g
g
Junction-to-Case
Junction-to-Case
Junction-to-Ambient
Junction-to-Ambient
Parameter
f
f
Typ.
–––
–––
–––
–––
Max.
13
94
63
46
Units
°C/W
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Package is limited to 12A by die-source to lead-frame bonding technology.
ƒ Pulse width ≤ 400μs; duty cycle ≤ 2%.
„ When mounted on 1 ich square copper board.
Rθ is measured at TJ of approximately 90°C.
† For DESIGN AID ONLY, not subject to production testing.
‡ Calculated continuous current based on maximum allowable junction temperature.
2
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IRLHS6242PbF
100
100
10
BOTTOM
1
0.1
1.4V
BOTTOM
10
≤60μs PULSE WIDTH
1
10
0.1
100
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
100
1.6
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
Tj = 150°C
1
0.01
T J = 150°C
TJ = 25°C
10
VDS = 10V
≤60μs PULSE WIDTH
1.0
ID = 8.5A
VGS = 4.5V
1.4
1.2
1.0
0.8
0.6
1.0
1.5
2.0
2.5
3.0
3.5
-60 -40 -20 0
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
10000
20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 8.5A
C oss = C ds + C gd
C, Capacitance (pF)
≤60μs PULSE WIDTH
1.4V
Tj = 25°C
0.1
VGS
10V
4.5V
3.0V
2.5V
2.0V
1.8V
1.5V
1.4V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
4.5V
3.0V
2.5V
2.0V
1.8V
1.5V
1.4V
Ciss
1000
Coss
Crss
12.0
VDS= 16V
VDS= 10V
10.0
VDS= 4.0V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
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0
5
10
15
20
25
30
35
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
3
IRLHS6242PbF
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
T J = 150°C
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100μsec
10msec
10
Limited by
Wire Bond
1
Tc = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
1.0
DC
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
1
VSD, Source-to-Drain Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
25
VGS(th), Gate threshold Voltage (V)
1.6
Limited By Package
20
ID, Drain Current (A)
1msec
15
10
5
0
1.4
1.2
1.0
ID = 25μA
ID = 250μA
ID = 1.0mA
ID = 1.0A
0.8
0.6
0.4
0.2
25
50
75
100
125
150
-75 -50 -25
T C , Case Temperature (°C)
0
25
50
75 100 125 150
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case (Bottom) Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC ) °C/W
100
10
D = 0.50
0.20
0.10
0.05
1
0.02
0.01
0.1
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)
4
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25
RDS(on), Drain-to -Source On Resistance ( mΩ)
RDS(on) , Drain-to -Source On Resistance (mΩ)
IRLHS6242PbF
ID = 8.5A
20
15
T J = 125°C
10
TJ = 25°C
5
0
2
4
6
8
10
12
14
30
25
20
Vgs = 2.5V
15
Vgs = 4.5V
10
5
16
0
10
20
30
40
50
60
70
ID, Drain Current (A)
VGS, Gate -to -Source Voltage (V)
Fig 13. Typical On-Resistance vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
600
70
ID
TOP
2.2A
4.3A
BOTTOM 8.5A
60
50
500
Single Pulse Power (W)
EAS , Single Pulse Avalanche Energy (mJ)
35
40
30
20
400
300
200
100
10
0
1E-5
0
25
50
75
100
125
150
1E-4
Starting T J , Junction Temperature (°C)
Driver Gate Drive
-
‚
-
P.W.
+
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
D.U.T. ISD Waveform
Reverse
Recovery
Current
V DD
D=
Period
*

RG
1E+0
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
„
-
1E-1
Fig 15. Typical Power vs. Time
+
ƒ
+
1E-2
Time (sec)
Fig 14. Maximum Avalanche Energy vs. Drain Current
D.U.T
1E-3
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
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5
IRLHS6242PbF
Id
Vds
Vgs
L
VCC
DUT
0
1K
Vgs(th)
S
Qgs1 Qgs2
Qgd
Qgodr
Fig 17b. Gate Charge Waveform
Fig 17a. Gate Charge Test Circuit
V(BR)DSS
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
A
I AS
0.01Ω
tp
Fig 18a. Unclamped Inductive Test Circuit
V DS
V GS
RG
RD
VDS
90%
D.U.T.
+
-V DD
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1
Fig 19a. Switching Time Test Circuit
6
Fig 18b. Unclamped Inductive Waveforms
10%
VGS
td(on)
tr
td(off)
tf
Fig 19b. Switching Time Waveforms
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IRLHS6242PbF
PQFN 2x2 Outline Package Details
For footprint and stencil design recommendations, please refer to application note AN-1154 at
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 2x2 Outline Part Marking
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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7
IRLHS6242PbF
PQFN 2x2 Outline Tape and Reel
8
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IRLHS6242PbF
Qualification information†
Qualification level
Moisture Sensitivity Level
RoHS compliant
†
††
†††
Cons umer
(per JE DE C JE S D47F
PQFN 2mm x 2mm
††
†††
guidelines )
MS L1
†††
(per JE DE C J-S T D-020D
Yes
)
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/2011
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