SUTEX HV860K7-G Low noise, dimmable el lamp driver Datasheet

HV860
Low Noise, Dimmable
EL Lamp Driver
Features
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The HV860 has two internal oscillators, a switching
MOSFET, and a high voltage EL lamp driver H-bridge. The
frequency for the switching MOSFET is set by an external
resistor connected between the RSW-Osc pin and the
supply pin VDD. The EL lamp driver frequency is set by
an external resistor connected between REL-Osc pin and
VDD pin. An external inductor is connected between the LX
and VDD pins or VIN for split supply applications. A 3.0nF
capacitor is connected between CS and ground. The EL
lamp is connected between VA and VB.
Adjustable output regulation for dimming
220VPP output voltage for higher brightness
Single cell lithium ion compatible
150nA shutdown current
Separately adjustable lamp and converter frequencies
3x3mm 12-Lead QFN package
Split supply capability
Applications
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The switching MOSFET charges the external inductor and
discharges it into the capacitor at CS. The voltage at CS will
start to increase. Once the voltage at CS reaches a nominal
value of 110V, the switching MOSFET is turned OFF to
conserve power. The outputs VA and VB are configured as
an H bridge and are switching in opposite states to achieve
±110V across the EL lamp.
Mobile cellular phone keypads
PDAs
Handheld wireless communication products
Global Positioning Systems (GPS)
General Description
EL lamp dimming can be accomplished by changing the
input voltage to the VREG pin. The VREG pin allows an
external voltage source to control the VCS amplitude. The
VCS voltage is approximately 87 times the voltage seen on
VREG.
The Supertex HV860 is a high voltage driver designed for
driving Electroluminescent, (EL), lamps of up to 5 square
inches. The input supply voltage range is from 2.5 to 4.5V.
The device uses a single inductor and a minimum number of
passive components. Using the internal reference voltage,
the regulated output voltage is at a nominal voltage of 110V.
The EL lamp will therefore see ±110V. An enable pin, (EN),
is available to turn the device on and off via a logic signal.
Typical Application Circuit
VIN
CIN
LX
D
RREG
VDD
CDD
10
RSW
12
1
1.5V = On
0V = Off
2
3
VREG
VREF
5
LX
CS
VDD
RSW-Osc
VA
REL-Osc
REL 11
EN
GND
4
CS
7
9
VB 8
EL
Lamp
HV860
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV860
Pin Configuration
Ordering Information
RSW-Osc EN
12-Lead QFN
Device
3.00x3.00mm body
0.80mm height (max)
0.50mm pitch
HV860
HV860K7-G
12
1
9
VA
VREG
2
8
VB
VREF
3
7
CS
Absolute Maximum Ratings
-40°C to +85°C
Storage temperature
-65°C to +150°C
Power dissipation:
H860
YWLL
-0.5V to +120V
VREG External input voltage
6
GND
LX
NC
Product Marking
1.6W
VCS, Output voltage
5
(top view)
Note:
Pads are at the bottom of the package. Center heat slug is at ground
potential.
-0.5V to 6.0V
Operating temperature
4
12-Lead QFN (K7)
Value
VDD, Supply voltage
10
REL-Osc
-G indicates package is RoHS compliant (‘Green’)
Parameter
11
VDD
1.33V
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
12-Lead QFN (K7)
Thermal Resistance
Package
θja
12-Lead QFN (K7)
60 °C/W
Recommended Operating Conditions
Sym
Parameter
Min
Typ
Max
Units
VDD
Supply voltage
2.5
-
4.5
V
---
fSW
Switching frequency
40
-
200
kHz
---
fEL
EL output frequency
150
-
500
Hz
---
0
-
20
nF
---
-40
-
+85
°C
---
Min
Typ
Max
Units
CLOAD
TA
EL lamp capacitance load
Operating temperature
Conditions
Electrical Characteristics
(Over recommended operating conditions unless otherwise specified TA = 25°C)
Sym
Parameter
Conditions
RDS(ON)
On-resistance of switching transistor
-
-
6.0
Ω
I = 100mA
VCS
Maximum output regulation voltage
90
-
120
V
VDD = 2.5V to 4.5V
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2
HV860
Electrical Characteristics (cont.)
Sym
VCS
Parameter
Min
Typ
Max
-
95
-
-
75
-
-
55
-
0
-
1.33
V
VDD = 2.5 to 4.5V
1.18
1.26
1.33
V
VDD = 2.5 to 4.5V
Output regulation voltage
VREG
External input voltage range
VREFH
VREF output high voltage
Units
Conditions
VDD = 2.5 to 4.5V, VREG = 1.092V
V
VDD = 2.5 to 4.5V, VREG = 0.862V
VDD = 2.5 to 4.5V, VREG = 0.632V
IDDQ
Quiescent VDD supply current
-
-
150
nA
EN = Low
IDD
Input current going into the VDD pin
-
-
250
µA
VDD = 2.5 to 4.5V, REL = 2.0MΩ,
RSW = 1.0MΩ
IIN
Input current including inductor
current
-
16
30
mA
VIN = 3.0V. See Figure 1.
IINQ
Quiescent VIN supply current
-
-
200
nA
VIN = 4.2V. EN = Low.
See Figure 1.
fEL
EL lamp frequency
160
200
240
Hz
REL = 2.0MΩ
fSW
Switching transistor frequency
76
90
104
kHz
RSW = 1.0MΩ
D
Switching transistor duty cycle
-
-
88
%
---
VIH
Enable input logic high voltage
1.5
-
VDD
V
VDD = 2.5 to 4.5V
VIL
Enable input logic low voltage
0
-
0.2
V
VDD = 2.5 to 4.5V
IIH
Enable input logic high current
-
-
100
µA
VIH = VDD = 2.5 to 4.5V
IIL
Enable input logic low current
-
-
-1.0
µA
VIL = 0V, VDD = 2.5 to 4.5V
CIN
Enable input capacitance
-
-
15
pF
---
Block Diagram
LX
VDD
EN
CS
Device Enable
100kΩ
RSW-Osc
PWM Switch
Oscillator
0 to 88%
+
VREG
-
C
60pF
VREF
REL-Osc
GND
VSENSE
1.26V
VREF
2x EL
Freq.
VA
Output
Drivers
VCS
VB
EL
Frequency
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV860
Figure 1: Typical Application / Test Circuit
+
-
220μH
(Cooper Inductor SD3814-221)
4.7μF
VIN
3.3MΩ
3
2
10
VDD
1.0MΩ 12
0.1μF
2.0MΩ 1
1.5V = ON
11
0V = Off
VREG
VDD
5
VREF
BAS21
LX
CS
RSW-Osc
VA
REL-Osc
EN
GND
4
VB
7
3.3nF
200V
9
3.0in2
EL Lamp
8
HV860
Typical Performance
VDD
3.0V
Lamp Size
3.0in2
VIN
IIN
3.3V
19.42mA
3.7V
17.95mA
4.2V
16.02mA
VCS
fEL
Brightness
20.32cd/m2
110V
194Hz
21.40cd/m2
21.81cd/m2
Typical Waveform on VA, VB, and Differential Waveform VA - VB
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4
HV860
Split Supply Configuration
The HV860 can also be used for handheld devices operating
from a battery where a regulated voltage is available. This
is shown in Figure 2. The regulated voltage can be used to
run the internal logic of the HV860. The amount of current
necessary to run the internal logic is 250µA max. Therefore,
the regulated voltage could easily provide the current without
being loaded down.
Enable/Disable Configuration
microprocessor signal is high the device is enabled, and
when the signal is low, it is disabled.
The HV860 can be easily enabled and disabled via a logic
control signal on the EN pin as shown in Figure 2. The
control signal can be from a microprocessor. When the
Figure 2: Split Supply and Enable/Disable Configuration
+
-
CIN
VIN
2
Regulated Voltage = VDD
RSW
CDD
1
REL 11
On = 1.5V
Off = 0V
3
VREG
10
VDD
12
LX
RREG
D
5
VREF
LX
CS
RSW-Osc
VA
REL-Osc
EN
GND
4
Audible Noise Reduction
The EL lamp, when lit, emits an audible noise. This is due
to EL lamp construction. The audible noise generated by the
EL lamp can be a major problem for applications where the
EL lamp is held close to the ear, such as cellular phones.
VB
CS
7
9
EL
Lamp
8
HV860
The HV860 employs a proprietary circuit to help minimize
the EL lamp’s audible noise by using a single resistor, RREG,
as shown in Figure 3.
Figure 3: Typical Application Circuit for Audible Noise Reduction
VIN
CIN
2
10
VDD
CDD
RSW
12
1
1.5V = On
0V = Off
REL 11
LX
RREG
3
VREG
VDD
VREF
D
5
LX
CS
RSW-Osc
VA
REL-Osc
EN
GND
4
How to Minimize EL Lamp Audible Noise
The audible noise from the EL lamp can be minimized with
the proper selection of RREG. RREG is connected between the
VREF and VREG pins. VREG has an internal 60pF capacitor
VB
7
CS
9
8
EL
Lamp
HV860
to ground. EL lamp noise can be minimized without much
loss in brightness by setting the RC time constant to be
approximately 1/12 of the EL frequency’s period.
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5
HV860
EL Lamp Dimming using PWM
This section describes the method of dimming the EL lamp.
Reducing the voltage amplitude at the VREG pin will reduce
the voltage on the CS pin, which will effectively reduce the
peak to peak voltage the EL lamp sees. Figure 4 shows a
circuit to dim the lamp by changing the duty cycle of a PWM
signal. A 10kΩ resistor is connected in series with a 3.3MΩ
resistor. An N-channel open drain PWM signal is used to pull
the 10kΩ resistor to ground. The effective voltage on the
VREG pin will be proportional to the duty cycle of the PWM
signal. The PWM operating frequency can be anywhere
between 20kHz to 100kHz.
Figure 4: PWM Dimming Circuit
+
-
VIN
4.7μF
Open Drain
n-channel
PWM Signal
3.3MΩ 10kΩ
3
2
+
-
10
VDD
On = 1.5V
Off = 0V
0.1μF
220μH
(Cooper Inductor SD3814-221)
VREG
VDD
1.0MΩ 12
RSW-Osc
2.0MΩ 1
11
REL-Osc
EN
5
VREF
GND
4
LX
CS
VA
VB
BAS21
7
3.3nF
200V
9
8
EL Lamp
HV860
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
6
HV860
Pin Configuration and External Component Description
Pin #
Name
1
REL-Osc
2
VREG
Description
External resistor from REL-Osc to VDD sets the EL frequency. The EL frequency is inversely
proportional to the external REL resistor value. Reducing the resistor value by a factor of two will
result in increasing the EL frequency by two.
Input voltage to set VCS regulation voltage. This pin allows an external voltage source to control
the VCS amplitude. EL lamp dimming can be accomplished by varying the input voltage at VREG.
The VCS voltage is approximately 87 times the voltage seen on VREG.
External resistor RREG, connected between VREG and VREF pins controls the VCS charging rate.
The charging rate is inversely proportional to the RREG resistor value.
3
VREF
Switched internal reference voltage.
4
GND
Device ground.
Drain of internal switching MOSFET. Connection for an external inductor.
5
LX
The inductor LX is used to boost the low input voltage by inductive flyback. When the internal
switch is on, the inductor is being charged. When the internal switch is off, the charge stored in
the inductor will be transferred to the high voltage capacitor CS. The energy stored in the capacitor
is transferred to the internal H-bridge, and therefore to the EL lamp. In general, smaller value
inductors, which can handle more current, are more suitable to drive larger size lamps. As the
inductor value decreases, the switching frequency of the inductor (controlled by RSW) should be
increased to avoid saturation.
A 220µH Cooper (SD3814-221) inductor with 5.5Ω series DC resistance is typically recommended.
For inductors with the same inductance value, but with lower series DC resistance, lower RSW
resistor value is needed to prevent high current draw and inductor saturation.
6
NC
No internal connections to the device.
7
CS
High voltage regulated output. Connection for an external high voltage capacitor to ground
8
VB
VB side of the EL lamp driver H-bridge. Connection for one of the EL lamp terminals.
9
VA
VA side of the EL lamp driver H-bridge. Connection for one of the EL lamp terminals.
10
VDD
11
EN
Logic input pin. Logic high will enable the device. This pin has an 100kΩ internal pull-down resistor
connected to GND.
12
RSW-Osc
External resistor from RSW-Osc to VDD sets the switch converter frequency. The switch converter
frequency is inversely proportional to the external RSW resistor value. Reducing the resistor value
by a factor of two will result in increasing the switch converter frequency by two.
Low voltage input supply pin.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
HV860
12-Lead QFN Package Outline (K7)
3.00x3.00mm body, 0.80mm height (max), 0.50mm pitch
D2
D
12
1
Note 1
(Index Area
D/2 x E/2)
12
1
Note 1
(Index Area
D/2 x E/2)
e
E
E2
b
View B
Top View
Bottom View
Note 3
θ
A
A3
A1
L
Seating
Plane
L1
Note 2
Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
Dimension
(mm)
A
A1
MIN
0.70
0.00
NOM
0.75
0.02
MAX
0.80
0.05
A3
0.20
REF
b
D
D2
E
E2
0.18
2.85*
1.25
2.85*
1.25
0.25
3.00
-
3.00
-
0.30
3.15*
1.65
3.15*
1.65
e
0.50
BSC
L
L1
θ
0.30
0.00
0O
0.40
-
-
0.50
0.15
14O
JEDEC Registration MO-220, Variation WEED-5, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-12QFNK73X3P050, Version B041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009
All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV860
C081209
8
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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