MUSIC MU9C3480A-70DC Lancam a/l sery Datasheet

Data Sheet
LANCAM A/L series
(not recommended for new designs)
APPLICATION BENEFITS
DISTINCTIVE CHARACTERISTICS
The 256x64 to 4Kx64 LANCAM A/L series facilitate
numerous operations:
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(Use functional compatible LANCAM B family for new designs)
DQ (15—0)
I/O BUFFERS
DATA (16)
(16)
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DATA (64)
MUX
VCC
GND
DATA (16)
TRANSLATE
802.3 / 802.5
COMMANDS &
STATUS (16)
DATA (16)
DEMUX
COMPARAND
SOURCE AND
DESTINATION
SEGMENT
COUNTERS
MASK 1
MASK 2
/E
INSTRUCTION (W/O)
/W
ADDRESS
CONTROL
CONTROL
/RESET
16
/EC
N
NEXT FREE ADDRESS (R/O)
/CM
SEGMENT CONTROL
PAGE ADDRESS (LOCAL)
DEVICE SELECT (GLOBAL)
STATUS (15-0) (R/O)
STATUS (31-16) (R/O)
DATA (64)
MATCH ADDR &
/MA FLAG
/MM, /FL
CAM ARRAY
2N WORDS
X 64 BITS
PRIORITY ENCODER
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2N X 2 VALIDITY BITS
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ADDRESS DECODER
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Fast speed allows processing of both DA and SA
within 450 ns, equivalent to 138 ports of 10 Base-T or
13 ports of 100 Base-T Ethernet (50 ns device)
Full CAM features allow all operations to be masked
on a bit-by-bit basis
Powerful instruction set for any list processing need
Shiftable Comparand and Mask registers assist in
proximate matching algorithms
Cascadable to any practical length with no
performance penalties
Industrial temperature grades for harsh environments
Available in 3.3 Volt for lower power systems
High density CMOS Content Addressable Memory
(CAM)
Available in the following depths: 256 (3480), 512
(5480), 1K (1480), 2K (2480) and 4K (4480) words.
64-bit per word memory organization
16-bit I/O
Fast 50 ns compare speed (1480A and 2480A)
Dual configuration register set for rapid context
switching
16-bit CAM/RAM segments with MUSIC’s patented
partitioning
/MA and /MM output flags to enable faster system
performance
Readable Device ID
Selectable faster operating mode with no wait states
after a no-match
Validity bit setting accessible from the Status register
Single cycle reset for Segment Control register
5 Volt (A series) or 3.3 Volt (L series) operation
44-pin PLCC package
(also available in Lead-Free package upon request)
/MA
/MM
2
N+1
2
REGISTER SET
/FF
MATCH
AND
FLAG
LOGIC
/FI
/MF
/MI
Figure 1: LANCAM B Family Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
April 18, 2005 Rev. 1
LANCAM A/L series (not recommended for new designs)
General Description
GENERAL DESCRIPTION
the database. The ability to search data words up to 64 bits
wide allows large address spaces to be searched rapidly
and efficiently. A patented architecture links each CAM
entry to associated data and makes this data available for
use after a successful compare operation.
The LANCAM A/L series consists of various depths of
64-bit Content Addressable Memories (CAMs), with a
16-bit wide interface.
CAMs, also known as associative memories, operate in the
converse way to random access memories (RAM). In
RAM, the input to the device is an address and the output
is the data stored at that address. In CAM, the input is a
data sample and the output is a flag to indicate a match and
the address of the matching data. As a result, CAM
searches large databases for matching data in a short,
constant time period, no matter how many entries are in
The MUSIC LANCAMs are ideal for address filtering and
translation applications in LAN switches and routers. The
LANCAMs are also well suited to encryption, database
accelerators, and image processing.
OPERATIONAL OVERVIEW
data to the Control, Comparand, and Mask registers
automatically triggers a compare. Compares also may be
initiated by a command to the device. Associated RAM
data is available immediately after a successful compare
operation. The Status register reports the results of
compares including all flags and addresses. Two Mask
registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The
RAM validity type allows additional masks to be stored in
the CAM array where they may be retrieved rapidly.
To use the LANCAM, the user loads the data into the
Comparand register, which is automatically compared to
all valid CAM locations. The device then indicates
whether or not one or more of the valid CAM locations
contains data that matches the target data. The status of
each CAM location is determined by two validity bits at
each memory location. The two bits are encoded to render
four validity conditions: Valid, Empty, Skip, and RAM,
shown in Status Register Bits on page 24 (bits 29:28). The
memory can be partitioned into CAM and associated
RAM segments on 16-bit boundaries, but by using one of
the two available Mask registers, the CAM/RAM
partitioning can be set at any arbitrary size between zero
and 64 bits.
A simple four-wire control interface and commands
loaded into the Instruction decoder control the device. A
powerful instruction set increases the control flexibility
and minimizes software overhead. Additionally, dedicated
pins for match and multiple-match flags enhance
performance when the device is controlled by a state
machine. These and other features make the LANCAM a
powerful associative memory that drastically reduces
search delays.
The LANCAM’s internal data path is 64 bits wide for
rapid internal comparison and data movement. Vertical
cascading of additional LANCAMs in a daisy chain
fashion extends the CAM memory depth for large
databases. Cascading requires no external logic. Loading
2
Rev. 1
Pin Descriptions
LANCAM A/L series (not recommended for new designs)
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good
layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 26 for more information.
/E (Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, and /EC. The
rising edge locks the daisy chain, turns off the DQ pins,
and clocks the Destination and Source Segment counters.
The four cycle types enabled by /E are shown in Table 1.
The /EC signal also enables the /MF–/MI daisy chain,
which serves to select the device with the highest-priority
match in a string of LANCAMs. Table 4 explains the
effect of the /EC signal on a device with or without a
match in both Standard and Enhanced modes. /EC must be
HIGH during initialization.
Table 1: I/O Cycles
/W
/CM
Cycle Type
LOW
LOW
Command Write Cycle
LOW
HIGH
Data Write Cycle
HIGH
LOW
Command Read Cycle
HIGH
HIGH
Data Read Cycle
DQ15–0 (Data Bus, I/O, TTL)
The DQ15–0 lines convey data, commands, and status to
and from the LANCAM. /W and /CM control the direction
and nature of the information that flows to or from the
device. When /E is HIGH, DQ15–0 go to HIGH-Z.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid
matches occur during a compare cycle. /MF becomes valid
after /E goes HIGH on the cycle that enables the daisy
chain (on the first cycle that /EC is registered LOW by the
previous falling edge of /E; see Figure 8 on page 14). In a
daisy chain, valid match(es) in higher priority devices are
passed from the /MI input to /MF. If the daisy chain is
enabled but the match flag is disabled in the Control
register, the /MF output only depends on the /MI input of
the device (/MF=/MI). /MF is HIGH if there is no match
or when the daisy chain is disabled (/E goes HIGH when
/EC was HIGH on the previous falling edge of /E). The
System Match flag is the /MF pin of the last device in the
daisy chain. /MF is reset when the active configuration
register set is changed.
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects
Command cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a
comparison, as shown in Figure 8 on page 14. If /EC is
LOW at the falling edge of /E in a given cycle, the /MF
output is enabled. Otherwise, the /MF output is held
HIGH.
Figure 2: PLCC Pinout
Rev. 1
3
LANCAM A/L series (not recommended for new designs)
Pin Descriptions
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied
LOW.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare
cycle. The /MA output is not qualified by /EC or /MI, and
reflects the match flag from that specific device’s Status
register. /MA is reset when the active register set is
changed.
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a
known state before operation, which resets the device to
the conditions shown in Table 3 on page 11. The /RESET
pin should be driven by TTL levels, not directly by an RC
timeout. /E must be kept HIGH during /RESET.
TEST1, TEST2 (Test, Input, TTL)
These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare
cycle. The /MM output is not qualified by /EC or /MI, and
reflects the multiple match flag from that specific device’s
Status register. /MM is reset when the active register set is
changed.
VCC, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the
LANCAM. VCC must meet the voltage supply
requirements in the Operating Conditions section relative
to the GND pins, which are at 0 volts (system reference
potential), for correct operation of the device. All the
ground and power pins must be connected to their
respective planes with adequate bulk and high frequency
bypassing capacitors in close proximity to the device.
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes
LOW when no empty memory locations exist within the
device (and in the daisy chain above the device as
indicated by the /FI pin). The System Full flag is the /FF
pin of the last device in the daisy chain, and the Next Free
address resides in the device with /FI LOW and /FF
HIGH. If disabled in the Control register, the /FF output
only depends on the /FI input (/FF = /FI).
4
Rev. 1
Functional Description
LANCAM A/L series (not recommended for new designs)
FUNCTIONAL DESCRIPTION
Data Movement (Read/Write)
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match or
Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also be
written directly to the memory from the DQ bus using any
of the above addressing modes. The Address register may
be directly loaded and may be set to increment or
decrement, allowing DMA-type reading or writing from
memory.
The LANCAM is a Content Addressable Memory (CAM)
with 16-bit I/O for network address filtering and
translation, virtual memory, data compression, caching,
and table lookup applications. The memory consists of
static CAM, organized in 64-bit data fields. Each data field
can be partitioned into a CAM and a RAM subfield on
16-bit boundaries. The contents of the memory can be
randomly accessed or associatively accessed by the use of
a compare. During automatic comparison cycles, data in
the Comparand register is automatically compared with
the “Valid” entries in the memory array. The Device ID
can be read using a TCO PS instruction (see Persistent
Source Register Bits on page 25).
Configuration Register Sets
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
typically would be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a
single instruction to change the current set of
configuration registers. The match condition of the device
is reset whenever the active register set is changed.
Data Input and Output Characteristics
The data inputs and outputs of the LANCAM are
multiplexed for data and instructions over a 16-bit I/O bus.
Internally, data is handled on a 64-bit basis, since the
Comparand register, the Mask registers, and each memory
entry are 64 bits wide. Memory entries are globally
configurable into CAM and RAM segments on 16-bit
boundaries, as described in US Patent 5,383,146 assigned
to MUSIC Semiconductors. Seven different CAM/RAM
splits are possible, with the CAM width going from one to
four segments, and the remaining RAM width going from
three to zero segments. Finer resolution on compare width
is possible by invoking a Mask register during a compare,
which allows global masking on a bit basis. The CAM
subfield contains the associative data, which enters into
compares, while the RAM subfield contains the associated
data, which is not compared. In LAN bridges, the RAM
subfield could hold, for example, port-address and aging
information related to the destination or source address
information held in the CAM subfield of a given location.
In a translation application, the CAM field could hold the
dictionary entries, while the RAM field holds the
translations, with almost instantaneous response.
Control Register
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning,
disable or select masking conditions, disable or select
auto-incrementing or auto-decrementing the Address
register, and select Standard or Enhanced mode. The
active Segment Control register contains separate counters
to control the writing of 16-bit data segments to the
selected persistent destination, and to control the reading
of 16-bit data segments from the selected persistent
source.
Validity Bits
Each entry has two validity bits associated with it to define
its particular type: Empty, Valid, Skip, or RAM. When
data is written to the active Comparand register, and the
active Segment Control register reaches its terminal count,
the contents of the Comparand register are automatically
compared with the CAM portion of all the valid entries in
the memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a time.
A Compare instruction then can be used to force another
compare between the Comparand register and the CAM
portion of memory entries of any one of the four validity
types. After a Read or Move from Memory operation, the
validity bits of the location read or moved are copied into
the Status register, where they can be read using
Command Read cycles.
Rev. 1
Mask Registers
There are two active Mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a
time. For masking comparisons, data stored in the active
selected Mask register determines which bits of the
comparand are compared against the valid contents of the
memory. If a bit is set HIGH in the Mask register, the same
bit position in the Comparand register becomes a “don’t
5
LANCAM A/L series (not recommended for new designs)
Functional Description
care” for the purpose of the comparison with all the
memory locations. During a Data Write cycle or a MOV
instruction, data in the specified active Mask register can
also determine which bits in the destination are updated. If
a bit is HIGH in the Mask register, the corresponding bit of
the destination is unchanged.
having the Highest-Priority match or the Next Free
address responds.
Cascading LANCAMs
A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM.
This register is loaded with a specific device address
during system initialization, which then serves as the
higher-order address bits. A Device Select register allows
the user to target a specific device within a vertically
cascaded system by setting it equal to the Page Address
Register value, or to address all the devices in a string at
the same time by setting the Device Select value to
FFFFH.
Highest Priority/Multiple Match
The match line associated with each memory address is
fed into a priority encoder where multiple responses are
resolved, and the address of the highest-priority responder
(the lowest numerical match address) is generated. In
LAN applications, a multiple response might indicate an
error. In other applications the existence of multiple
responders may be valid.
Figure 3 shows expansion using a daisy chain. Note that
system flags are generated without the need for external
logic. The Page Address register allows each device in the
vertically cascaded chain to supply its own address in the
event of a match, eliminating the need for an external
priority encoder to calculate the complete Match address
at the expense of the ripple-through time to resolve the
Highest-Priority match. The Full flag daisy-chaining
allows Associative writes using a Move to Next Free
Address instruction, which does not need a supplied
address.
Input Control Signals and Commands
Four input control signals and commands loaded into an
instruction decoder control the LANCAM. Two of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control,
Segment Control, Address, Next Free Address, etc.) are
accessed using Temporary Command Override
instructions. The data path from the DQ bus to/from data
resources (comparand, masks, and memory) within the
device are set until changed by Select Persistent Source
and Destination instructions.
Figure 4 shows an external PLD implementation of a
simple priority encoder that eliminates the daisy chain
ripple-through delays for systems requiring maximum
performance from many CAMs.
After a Compare cycle (caused by either a data write to the
Comparand or Mask registers, a write to the Control
register, or a forced compare), the Status register contains
the address of the Highest-Priority Matching location in
that device, concatenated with its page address, along with
flags indicating internal match, multiple match, and full.
When the Status register is read with a Command Read
cycle, the device with the Highest-Priority Match
responds, outputting the System Match address to the DQ
bus. The internal Match (/MA) and Multiple Match (/MM)
flags are also output on pins. Another set of flags (/MF and
/FF) that are qualified by the match and full flags of
previous devices in the system also are available directly
on output pins, and are independently daisy-chained to
provide System Match and Full flags in vertically
cascaded LANCAM arrays. In such arrays, if no match
occurs during a comparison, read access to the memory
and all the registers except the Next Free register is denied
to prevent device contention. In a daisy chain, all devices
respond to Command and Data Write cycles, depending on
the conditions shown in Table 4 unless the operation
involves the Highest-Priority Match address or the Next
Free address; in which case, only the specific device
6
Rev. 1
Functional Description
LANCAM A/L series (not recommended for new designs)
Vcc
16
DQ15–0
DQ15–0
/E
/E
/W
/W
/CM
/CM
/EC
/EC
/MI
/FI
LANCAM
/FF
/MF
DQ15–0
/MI
/E
/FI
LANCAM
/W
/CM
/FF
/EC
/MF
DQ15–0
/MI
/E
/W
/FI
LANCAM
/CM
/EC
/FF
SYSTEM FULL
/MF
SYSTEM MATCH
Figure 3: Vertical Cascading
Vcc
/MI
PLD
LANCAM
/MA
/MI
LANCAM
/MA
/MI
LANCAM
/MA
/MI
LANCAM
/MA
SYSTEM
MATCH
Figure 4: External Prioritizing
Rev. 1
7
LANCAM A/L series (not recommended for new designs)
Operational Characteristics
OPERATIONAL CHARACTERISTICS
Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit
binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order
bits (bits 15–0) and Segment 3 corresponds to the highest order bits (bits 63–48).
The Register Set
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set and the
other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
return to a foreground network filtering task from a
background housekeeping task.
Control Bus
Refer to Figure 1 on page 1 for the following discussion.
The inputs Chip Enable (/E), Write Enable (/W),
Command Enable (/CM), and Enable Daisy Chain (/EC)
are the primary control mechanism for the LANCAM. The
/EC input of the Control bus enables the /MF Match flag
output when LOW and controls the daisy chain operation.
Instructions are the secondary control mechanism. Logical
combinations of the Control Bus inputs, coupled with the
execution of Select Persistent Source (SPS), Select
Persistent Destination (SPD), and Temporary Command
Override (TCO) instructions allow the I/O operations to
and from the DQ15–0 lines to the internal resources, as
shown in Table 2.
Writing a value to the Control register or writing data to
the last segment of the Comparand or either Mask register
causes an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
The Comparand register is the default source and
destination for Data Read and Write cycles. This default
state can be overridden independently by executing a
Select Persistent Source or Select Persistent Destination
instruction, selecting a different source or destination for
data. Subsequent Data Read or Data Write cycles access
that source or destination until another SPS or SPD
instruction is executed. The currently selected persistent
source or destination can be read back through a TCO PS
or PD instruction. The sources and destinations available
for persistent access are those resources on the 64-bit bus:
Comparand register, Mask Register 1, Mask Register 2,
and the Memory array.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’s Address Field flag (bit 11)
is set to a 1, it is a two-cycle instruction that is not
executed immediately. For the next cycle only, the data
from a Command Write cycle is loaded into the Address
register and the instruction then completes at that address.
The Address register then increments, decrements, or stays
at the same value depending on the setting of Control
Register bits CT3 and CT2. If the Address Field flag is not
set, the memory access occurs at the address currently
contained in the Address register.
The default destination for Command Write cycles is the
Instruction decoder, while the default source for
Command Read cycles is the Status register.
Temporary Command Override (TCO) instructions
provide access to the Control register, the Page Address
register, the Segment Control register, the Address
register, the Next Free Address register, and Device Select
register. TCO instructions are active only for one
Command Read or Write cycle after being loaded into the
Instruction decoder.
Control Register (CT)
The Control register contains a number of switches that
configure the LANCAM, as shown in Control Register
Bits on page 23. It is written or read using a TCO CT
instruction. If bit 15 of the value written during a TCO CT
is a 0, the device is reset (and all other bits are ignored).
See Table 3 on page 11 for the Reset states. Bit 15 always
reads back as a 0. A write to the Control register causes an
automatic compare to occur (except in the case of a reset).
Either the Foreground or Background Control register is
active, depending on which register set has been selected,
and only the active Control register is written to or read
from.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When
writing to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are
registered by the falling edge of /E, and the Data outputs
are enabled while /E is LOW. When reading from the
persistently selected data source, the Source Segment
counter is clocked by the rising edge of /E.
If the Match Flag is disabled through bit 14 and bit 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Table 4 so that Case 6 is not possible, effectively
8
Rev. 1
Operational Characteristics
LANCAM A/L series (not recommended for new designs)
removing the device from the daisy chain. With the Match
Flag disabled, /MF=/MI and operations directed to
Highest-Priority Match locations are ignored. Normal
operation of the device is with the /MF enabled. The
Match Flag Enable field has no effect on the /MA or /MM
output pins or Status Register bits. These bits always
reflect the true state of the device.
Segment Control Register (SC)
The Segment Control register, as shown in Segment
Control Register Bits on page 23, is accessed using a TCO
SC instruction. On read cycles, D15, D10, D5, and D2
always read back as 0s. Either the Foreground or
Background Segment Control register is active, depending
on which register set is selected, and only the active
Segment Control register is written to or read from.
If the Full Flag is disabled through bit 12 and bit 11, the
device behaves as if it is full and ignores instructions to
Next Free address. Also, writes to the Page Address
register are disabled. All other instructions operate
normally. Additionally, with the /FF disabled, /FF=/FI.
Normal operation of the device is with the /FF enabled.
The Full Flag Enable field has no effect on the /FL Status
Register bit. This bit always reflects the true state of the
device.
The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and
one for data writes. These counters control which 16-bit
segment of the 64-bit internal resource is accessed during
a particular data cycle on the 16-bit data bus. The actual
destination for data writes and source for data reads (called
the persistent destination and source) are set independently
with SPD and SPS instructions, respectively.
The IEEE Translation control at bit 10 and bit 9 can be
used to enable the translation hardware for writes to 64-bit
resources in the device. When translation is enabled, the
bits are reordered as shown in Figure 5.
DQ15
DQ8 DQ7
DQ0
DQ15
DQ8 DQ7
DQ0
Each of the two counters consists of a start limit, an end
limit, and the current count value that points to the
segment to be accessed on the next data cycle. The current
count value can be set to any segment, even if it is outside
the range set by the start and end limits. The counters
count up from the current count value to the end limit and
then jump back to the start limit. If the current count is
greater than the end limit, the current count value
increments to three, rolls over to zero, continues
incrementing until the end limit is reached, and then jumps
back to the start limit.
If a sequence of data writes or reads is interrupted, the
Segment Control register can be reset to its initial start
limit values by using an RSC instruction. After the
LANCAM is reset, both Source and Destination counters
are set to count from Segment 0 to Segment 3 with an
initial value of 0.
Figure 5: IEEE 802.3/802.5 Format Mapping
Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments.
The RAM portion can be at either end of the 64-bit word.
Compare masks may be selected by bit 5 and bit 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bit 3 and bit 2, and may be set to increment,
decrement, or neither after a memory access. Bit 1 and bit
0 set the operating mode: Standard or Enhanced as shown
in Table 4 on page 12. The device resets to the Standard
mode, and follows the operating responses of the original
MU9C1480 in Table 4. When operating in Enhanced
mode, it is not necessary to unlock the daisy chain with a
NOP instruction before command or data writes after a
non-matching compare, as required in Standard mode.
Rev. 1
9
LANCAM A/L series (not recommended for new designs)
Operational Characteristics
Table 2: Input/Output Operations
Cycle Type
/E
/C
M
/
W
I/O Status
Cmd Write
L
L
L
IN
IN
IN
IN
IN
IN
IN
Cmd Read
L
L
H
SPS
SPD
3
3
3
3
3
3
3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
HIGH-Z
Data Write
L
H
L
IN
IN
IN
IN
IN
IN
IN
Data Read
L
H
H
OUT
OUT
OUT
OUT
OUT
HIGH-Z
H
X
X
HIGH-Z
TC
O
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Operation
Notes
Load Instruction decoder
Load Address register
Load Control register
Load Page Address register
Load Segment Control register
Load Device Select register
Deselected
1
2,3
3
3
3
3
10
Read Next Free Address register
Read Address register
Read Status Register bits 15–0
Read Status Register bits 31–16
Read Control register
Read Page Address register
Read Segment Control register
Read Device Select register
Read Current Persistent Source or Destination
Deselected
3
3
4
5
3
3
3
3
3,11
10
Load Comparand register
Load Mask Register 1
Load Mask Register 2
Write Memory Array at address
Write Memory Array at Next Free address
Write Memory Array at Highest-Priority match
Deselected
6,9
7,9
7,9
7,9
7,9
7,9
10
Read Comparand register
Read Mask Register 1
Read Mask Register 2
Read Memory Array at address
Read Memory Array at Highest-Priority match
Deselected
6, 9
8, 9
8, 9
8, 9
7, 8
10
Deselected
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Default Command Write cycle destination (does not require a TCO instruction).
Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the instruction loaded in the
previous cycle.
Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write or Read cycle only.
NFA register can not be loaded this way.
Default Command Read cycle source (does not require a TCO instruction).
Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of Status Register Bits 15–0.
If next cycle is not a Command Read cycle, any subsequent Command Read cycle accesses the Status Register Bits 15–0.
Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations, SPD CR or SPS CR restores
the Comparand register as the destination or source.
Selected by executing a Select Persistent Destination instruction.
Selected by executing a Select Persistent Source instruction.
Access may require multiple 16-bit Read or Write cycles. The Segment Control register controls the selection of the desired 16-bit segment(s) by
establishing the Segment counters’ start and end limits and count values.
Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device Select Register is set to
FFFFH, which allows only write access to the device. (Writes to the Device Select register are always active.) Device may also be deselected under
locked daisy chain conditions as shown in Table 4.
A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a persistent source or
destination. The TCO PS instruction also reads back the Device ID.
10
Rev. 1
Operational Characteristics
LANCAM A/L series (not recommended for new designs)
Table 3: Device Control State After Reset
CAM Status
/RESET Condition
Validity bits at all memory locations
Match and Full Flag outputs
IEEE 802.3–802.5 Input Translation
CAM/RAM Partitioning
Comparison Masking
Address register auto-increment or auto-decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Operating Mode
Configuration Register set
Skip = 0, Empty = 1 (empty)
Enabled
Not translated
64 bits CAM, 0 bits RAM
Disabled
Disabled
00B to 11B; loaded with 00B
Contain all 0s
Contain all 0s (no change on software reset)
Contains 0008H
Instruction decoder
Status register
Comparand register
Standard
Foreground
Page Address Register (PA)
The Page Address register is loaded using a TCO PA
instruction followed by a Command Write cycle of a user
selected 16-bit value (not FFFFH). The entry in the PA
register gives a unique address to the different devices in a
daisy chain. In a daisy chain, the PA value of each device
is loaded using the SFF instruction to advance to the next
device, shown in the Setting Page Address Register Values
on page 16. A software reset (using the Control register)
does not affect the Page Address register.
Control Register bits CT3 and CT2 set the Address
register to automatically increment or decrement (or not
change) during sequences of Command or Data cycles.
The Address register changes after executing an
instruction that includes M@[AR] or M@aaaH, or after a
data access to the end limit segment (as set in the Segment
Control register) when the persistent source or destination
is M@[AR] or M@aaaH.
Either the Foreground or Background Address register is
active, depending on which register set is selected, and
only the active Address register is written to or read from.
Device Select Register (DS)
The Device Select register selects a specific (target)
device. The TCO DS instruction sets the 16-bit DS register
to the value of the following Command Write cycle. The
DS register can be read. A device is selected when its DS
is equal to its PA value. In a daisy chain, setting DS =
FFFFH selects all devices. However, in this case, the
ability to read information out of the device is restricted as
shown in Table 4. A software reset (using the Control
register) does not affect the Device Select register.
Next Free Address Register (NF)
The LANCAM automatically stores the address of the first
empty memory location in the Next Free Address register,
which is then used as a memory address pointer for
M@NF operations. The Next Free Address register,
shown in Next Free Address Bits on page 24, can be read
using a TCO NF instruction. By taking /EC LOW during
the TCO NF instruction cycle, only the device with /FI
LOW and /FF HIGH outputs the contents of its Next Free
Address register, giving the Next Free address in a system
of daisy-chained devices. The Next Free address may be
read from a specific device in the chain by setting the
Device Select register to the value of the desired device’s
Page address and leaving /EC HIGH. The Full Flag daisy
chain causes only the device whose /FI input is LOW and
/FF output HIGH to respond to an instruction using the
Next Free address. After a reset, the Next Free Address
register is set to zero.
Address Register (AR)
The Address register points to the CAM memory location
to be operated upon when M@[AR] or M@aaaH is part of
the instruction. It can be loaded directly by using a TCO
AR instruction or indirectly by using an instruction
requiring an absolute address, such as MOV aaaH,CR,V.
After being loaded, the Address register value is the next
memory access referencing the Address register. A reset
sets the Address register to zero.
Rev. 1
11
LANCAM A/L series (not recommended for new designs)
Operational Characteristics
Table 4: Standard and Enhanced Mode Device Select Response
Standard Mode
Case
Internal
/EC(int)
Internal
/MA(int)
External
/MI
Device Select
Register
Command
Write1
Data
Write
Command
Read
Data
Read
1
1
X
X
DS = FFFFH
YES3
YES4
NO
NO
YES4
2
1
X
X
DS = PA
YES3
YES
YES
3
1
X
X
DS ≠ FFFFH and
DS ≠ PA
NO
NO
NO
NO
4
0
X
0
X
NO
NO
NO5
NO
NO
5
0
1
1
X
NO
NO
NO5
62
0
0
1
X
YES3
YES4
YES5
YES
Case
Internal
/EC(int)
Internal
/MA(int)
External
/MI
Device Select
Register
Command
Write1
Data
Write
Command
Read
Data
Read
1
1
X
X
DS = FFFFH
YES3
YES4
NO
NO
2
1
X
X
DS = PA
YES3
YES4
YES
YES
3
1
X
X
DS ≠ FFFFH and
DS ≠ PA
NO
NO
NO
NO
4
0
0
0
X
YES3,6
YES3,7
NO5
NO
5
0
1
X
X
YES3,6
YES3,7
NO5
NO
62
0
0
1
X
YES3
YES4
YES5
YES
Enhanced Mode
Notes:
1.
2.
3.
4.
5.
6.
7.
Exceptions are:
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain (i.e., /FI LOW and
/FF HIGH) and NO if it does not.
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
This is NO if the Persistent Destination is Memory at Highest-Priority match.
Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control
register to select which 16-bit segment of the Comparand
register is to be loaded or read out. The persistent source
and destination for data writes and reads can be changed to
the Mask registers or memory by SPS and SPD
instructions. During an automatic or forced compare, the
Comparand register is simultaneously compared against
the CAM portion of all memory locations with the correct
validity condition. Automatic compares always compare
against valid memory locations, while forced compares,
using CMP instructions, can compare against memory
locations tagged with any specific validity condition.
Status Register
The 32-bit Status register, shown in Status Register Bits on
page 24, is the default source for Command Read cycles.
Bit 31 (internal Full flag) goes LOW if the particular
device has no empty memory locations. Bit 30 is the
internal Multiple Match flag, which goes LOW if a
Multiple match was detected. Bit 29 and Bit 28 are the
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Validity bits read 11 until a
read or move from memory has occurred. The rest of the
Status register down to bit 1 contains the Page address of
the device and the address of the Highest-Priority match.
After a reset or a no-match condition, the match address
bits are all 1s. Bit 0 is the internal Match flag, which goes
LOW if a match was found in this particular device.
The Comparand register may be shifted one bit at a time to
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the
wrap-around determined by the CAM/RAM partitioning
12
Rev. 1
Operational Characteristics
LANCAM A/L series (not recommended for new designs)
set in the Control register. During shift rights, bits shifted
off the LSB of the CAM partition reappear at the MSB of
the CAM partition. Likewise, bits shifted off the MSB of
the CAM partition reappear at the LSB during shift lefts.
The Memory Array
Memory Organization
The Memory array is organized into 64-bit words with
each word having an additional two validity bits. By
default, all words are configured to be 64 CAM cells.
However, bits 8–6 of the Control register can divide each
word into a CAM field and a RAM field. The RAM field
can be assigned to the least-significant or most-significant
portion of each entry.
Mask Registers (MR1, MR2)
The Mask registers can be used in two different ways:
either to mask compares or to mask data writes and moves.
Either Mask register can be selected in the Control register
to mask every compare, or selected by instructions to
participate in data writes or moves to and from Memory. If
a bit in the selected Mask register is set to a 0, the
corresponding bit in the Comparand register enters into a
masked compare operation. If a Mask bit is a 1, the
corresponding bit in the Comparand register does not enter
into a masked compare operation. Bits set to 0 in the Mask
register cause corresponding bits in the destination register
or memory location to be updated when masking data
writes or moves, while a bit set to 1 prevents that bit in the
destination from being changed.
The CAM/RAM partitioning is allowed on 16-bit
boundaries, permitting selection of the configuration
shown in Control Register Bits on page 23, bits 8–6 (e.g.,
“001” sets the 48 MSBs to CAM and the 16 LSBs to
RAM). Memory Array bits designated as RAM can be
used to store and retrieve data associated with the CAM
content at the same memory location.
Memory Access
There are two general ways to get data into and out of the
Memory array: directly or by moving the data by means of
the Comparand or Mask registers.
Either the Foreground or Background MR1 can be set
active, but after a reset, the Foreground MR1 is active by
default. MR2 incorporates a sliding mask, where the data
can be replicated one bit at a time to the right or left with
no wrap-around by issuing a Shift Right or Shift Left
instruction. The right and left limits are determined by the
CAM/RAM partitioning set in the Control register. For a
Shift Right the upper limit bit is replicated to the next
lower bit, while for a Shift Left the lower limit bit is
replicated to the next higher bit.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct
access can be supplied directly; supplied from the Address
register, supplied from the Next Free Address register, or
supplied as the Highest-Priority Match address.
Additionally, all the direct writes can be masked by either
Mask register.
The second way is to move data by means of the
Comparand or Mask registers. This is accomplished by
issuing Data Move commands (MOV). Moves using the
Comparand register can also be masked by either of the
Mask registers.
/E
/W
/CM
/EC
DQ15-0
DATA OUT
Figure 6: Read Cycle
Rev. 1
13
LANCAM A/L series (not recommended for new designs)
Operational Characteristics
/E
/W
/CM
/EC
DQ15–0
Figure 7: Write Cycle
COMPARAND WRITE
CYCLE
STATUS READ
CYCLE
/E
ASSOCIATED DATA
READ CYCLE
/CM
/W
DQ15–0
DATA
DATA
DATA
/EC
/MF
MATCH FLAG VALID
/MA, /MM
/MA AND /MM FLAGS UPDATED
Figure 8: Cycle-to-Cycle Timing Example
I/O Cycles
The LANCAM supports four basic I/O cycles: Data Read,
Data Write, Command Read, and Command Write. The
states of the /W and /CM control inputs determine the type
of cycle. These signals are registered at the beginning of a
cycle by the falling edge of /E. Table 1 on page 3 shows
how the /W and /CM signals select the cycle type.
cycle prior to any cycle that requires a locked daisy chain,
such as a Status register or associated data read after a
match. If there is no match in Standard mode, the output
buffers stay High-Z, and the daisy chain must be unlocked
by taking /EC HIGH during a NOP or other
non-functioning cycle, as indicated in Table 4 on page 12.
Figure 8 on page 14 shows how the internal /EC timing
holds the daisy chain locking effect over into the next
cycle. In Enhanced mode, this NOP is not needed before
data or command writes following a non-matching
compare, as indicated by Table 4 on page 12. A
single-chip system does not require daisy-chained match
flag operation, hence /EC could be tied HIGH and the
/MA pin or flag in the Status register used instead of /MF,
allowing access to the device regardless of the match
condition.
During Read cycles, the DQ15–0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command
to be written is captured from DQ15–0 at the beginning of
the cycle by the falling edge of /E. Figure 9 on page 15 and
Figure 6 on page 13, show Read and Write cycles
respectively. Figure 7 on page 14, shows typical
cycle-to-cycle timing with the Match flag valid at the end
of the Comparand Write. Data writes and reads to the
comparand, Mask registers, or memory occur in one to
four 16-bit cycles, depending on the settings in the
Segment Control register. The Compare operation
automatically occurs during Data writes to the Comparand
or Mask registers when the destination segment counter
reaches the end count set in the Segment Control register.
If there was a match, the second cycle reads status or
associated data, depending on the state of /CM. For
cascaded devices, /EC needs to be LOW at the start of the
The minimum timings for the /E control signal are given
in Table 9 on page 28. Note that at minimum timings the
/E signal is non-symmetrical and that different cycle types
have different timing requirements, as given in Table 6 on
page 22.
14
Rev. 1
Operational Characteristics
LANCAM A/L series (not recommended for new designs)
Compare Operations
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any Mask register used during compares
must be selected beforehand in the Control register. There
are two ways compares are initiated: Automatic compare
and Forced compare.
second, to provide a system wide match flag; third, to lock
out all devices except the one with the Highest-Priority
match for instructions such as Status reads after a match.
The Match flag logic causes only the highest-priority
device to operate on its Highest-Priority Match location
while devices with lower-priority matches ignore
Highest-Priority Match operations. The lock-out feature is
enabled by the match flag cascading and the use of the /EC
control signal, as shown in Table 4.
Automatic compares perform a compare of the contents of
the Comparand register against Memory locations that are
tagged as “Valid,” and occur whenever the following
happens:
•
•
The ripple delay of the flags when connected in a daisy
chain requires the extension of the /E HIGH time until the
logic in all devices has settled out. In a string of “n”
devices, the /E HIGH time should be greater than
The Destination Segment counter in the Segment
Control register reaches its end limit during writes to
the Comparand or Mask registers.
tEHMFV + (n-2)· tMIVMFV
After a command write of a TCO CT is executed
(except for a software reset), so that a compare is
executed with the new settings of the Control register.
If the last device’s Match flag is required by external logic
or a state machine before the start of the next CAM cycle,
one additional tMIVMFV should be added to the /E HIGH
time along with the setup time and delays for the external
logic.
Forced compares are initiated by CMP instructions using
one of the four validity conditions: V, R, S, and E. The
forced compare against “Empty” locations automatically
masks all 64 bits of data to find all locations with the
validity bits set to “Empty,” while the other forced
compares are only masked as selected in the Control
register.
/E
/EC
Vertical Cascading
LANCAMs can be vertically cascaded to increase system
depth. Through the use of flag daisy-chaining, multiple
devices respond as an integrated system. The flag daisy
chain allows all commands to be issued globally, with a
response only in the device containing the Highest-Priority
Matching or Next Free location. When connected in a
daisy chain, the last device’s Full flag and Match flag
accurately report the condition for the whole string. A
system in which LANCAMs are vertically cascaded using
daisy-chaining of the flags is shown in Figure 3 on page 7.
/EC (INT)
/MF
Figure 9: /EC (Int) Timing Diagram
Locked Daisy Chain
In a locked daisy chain, the highest-priority device is the
one with /MI HIGH and /MF LOW. In Standard mode,
only this device responds to command and data reads and
writes, until the daisy chain has been unlocked by taking
/EC HIGH. This allows reading the associated data field
from only the Highest-Priority Match location anywhere
in a string of devices, or the Match address from the Status
register of the device with the match. It also permits
updating the entry stored at the Highest-Priority Match
location. In Enhanced mode, devices are enabled to
respond to some command and data writes, as noted in
Table 4 on page 12, but not command and data reads.
To operate the daisy chain, the Device Select registers are
set to FFFFH to enable all devices to execute Command
Write and Data Write cycles. In normal operation, read
cycles are enabled from the device with the
Highest-Priority match by locking the daisy chain (see the
Locked Daisy Chain section). An individual device in the
chain may be targeted for a read or write operation by
temporarily setting the Device Select registers to the Page
address of the target device. Setting the Device Select
registers back to FFFFH restores the operation of the
entire daisy chain.
Table 4 (Standard and Enhanced modes) show when a
device responds to reads or writes and when does not,
based on the state of /EC(int), the internal match
condition, and other control inputs. /EC is latched by the
falling edge of /E. /EC(int) is registered from the latched
/EC signal off the rising edge of /E, so it controls what
happens in the next cycle, as shown in Figure 9 on page
Match Flag Cascading
The Match Flag daisy chain cascading has three purposes:
first, to allow operations on Highest-Priority Match
addresses to be issued globally over the whole string;
Rev. 1
15
LANCAM A/L series (not recommended for new designs)
Operational Characteristics
15. When /EC is first taken LOW in a string of LANCAM
devices (and assuming the Device Select registers are set
to FFFFH), all devices respond to that command write or
data write.
Full Flag Cascading
The Full Flag daisy chain cascading has the following
three purposes:
From then on the daisy chain remains locked in each
subsequent cycle as long as /EC is held LOW on the
falling edge of /E in the current cycle. When the daisy
chain is locked in Standard mode, only the
Highest-Priority Match device responds (See Case 6 of
Table 4). If, for example, all of the CAM memory
locations were empty, there would be no match, and /MF
would stay HIGH. Since none of the devices could then be
the Highest-Priority Match device, none respond to reads
or writes until the daisy chain is unlocked by taking /EC
HIGH and asserting /E for a cycle.
•
Allow instructions that address Next Free locations to
operate globally
•
Provide a system wide Full flag
•
Allow the loading of the Page Address registers
during initialization using the SFF instruction
The full flag logic causes only the device containing the
first empty location to respond to Next Free instructions
such as MOV NF,CR,V, which moves the contents of the
Comparand register to the first empty location in a string
of devices and sets that location Valid, making it available
for the next automatic compare. With devices connected as
in Figure 3 on page 7, the /FF output of the last device in a
string provides a full indication for the entire string.
If there is a match between the data in the Comparand
register and one or more locations in memory, then only
the Highest-Priority Match device responds to any cycle,
such as an associated data or Status Register read. If there
is not a match, then a NOP with /EC HIGH needs to be
inserted before issuing any new instructions, such as Write
to Next Free Address instruction to learn the data. Since
Next Free operations are controlled by the /FI–/FF daisy
chain, only the device with the first empty location
responds. If an instruction is used to unlock the daisy
chain, it works only on the Highest-Priority Match device,
if one exists. If none exists, the instruction has no effect
except to unlock the daisy chain. To read the Status
registers of specific devices when there is no match
requires the use of the TCO DS command to set DS=PA of
each device. Single chip systems can tie /EC HIGH and
read the Status register or the /MA and /MM pins to
monitor match conditions, as the daisy chain lock-out
feature is not needed in this configuration. This removes
the need to insert a NOP in the case of a no-match.
IEEE 802.3/802.5 Format Mapping
To support the symmetrical mapping between the address
formats of IEEE 802.3 and IEEE 802.5, the LANCAM
provides a bit translation facility. Formally expressed, the
nth input bit, D(n), maps to the xth output bit, Q(x),
through the following expressions:
D(n) = Q(7–n) for 0 < n < 7,
D(n) = Q(23–n) for 8 < n < 15
Setting Control Register bit 10 and bit 9 selects whether to
persistently translate, or persistently not to translate, the
data written onto the 64-bit internal bus. The default
condition after a Reset command is not to translate the
incoming data. Figure 5 on page 9 shows the bit mapping
between the two formats.
Initializing the Lancam
Initialization of the LANCAM is required to configure the
various registers on the device. Since a Control register
reset establishes the operating conditions shown in Table 3
on page 11, restoration of operating conditions better
suited for the application may be required after a reset,
whether using the Control Register reset, or the /RESET
pin. When the device powers up, the memory and registers
are in an unknown state, so the /RESET pin must be
asserted to place the device in a known state.
When the Control register is set to Enhanced mode, you
can continue to write data to the Comparand register or
issue a Move to Next Free Address instruction without
first having to issue a NOP with /EC HIGH to unlock the
daisy chain after a Compare cycle with no match, as
indicated in cases 4 and 5 of Table 4 on page 12. In
Enhanced mode, data write cycles as well as command
write cycles are enabled in all devices even when /EC is
LOW. Exceptions are data writes, moves, or VBC
instructions involving HM, which occur only in the device
with the highest match; and data writes or move
instructions involving NF, which occur only in the device
with /FI LOW and /FF HIGH. Enhanced mode speeds up
system performance by eliminating the need to unlock the
daisy chain before Command or Data Write cycles.
Setting Page Address Register Values
In a vertically cascaded system, the user must set the
individual Page Address registers to unique values by
using the Page Address initialization mechanism. Each
Page Address register must contain a unique value to
prevent bus contention. This process allows individual
device selection. The Page Address register initialization
works as follows: Writes to Page Address registers are
only active for devices with /FI LOW and /FF HIGH. At
16
Rev. 1
Operational Characteristics
LANCAM A/L series (not recommended for new designs)
initialization, all devices are empty, thus the top device in
the string responds to a TCO PA instruction, and loads its
PA register. A Set Full Flag (SFF) instruction advances to
the next device in the string and is active only for the
device with /FI LOW and /FF HIGH. The SFF instruction
changes the first device’s /FF to LOW, although the device
really is empty, which allows the next device in the string
to respond to the TCO PA instruction and load its PA
register. The initialization proceeds through the chain in a
similar manner filling all the PA registers in turn. Each
device must have a unique Page Address value stored in
its PA register, or contention results. After all the PA
registers are filled, the entire string is reset through the
Control register, which does not change the values stored
in the individual PA registers. After the reset, the Device
Select registers usually are set to FFFFH to enable
operation in Case 1 of Table 4 on page 12. The Control
registers and the Segment Control registers are then set to
their normal operating values for the application.
Vertically Cascaded System Initialization
Table 5 shows an example of code that initializes a
daisy-chained string of LANCAM devices. The
initialization example shows how to set the Page Address
registers of each of the devices in the chain through the
use of the Set Full Flag instruction, and how the Control
registers and Segment counters of all the LANCAM
devices are set for a typical application. Each Page
Address register must contain a unique value (not FFFFH)
to prevent bus contention.
For typical daisy chain operation, data is loaded into the
Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH (except for the device with a
match), for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device to
be able to read from it. Refer to Table 4 on page 12 for
preconditions for reading and writing. Initialization for a
single LANCAM is similar. The Device Select register in
this case is usually set to equal the Page Address register
for normal operations. Also, the dedicated /MA flag output
can be used instead of /MF, allowing /EC to be tied HIGH.
Table 5: Initialization Routine Example
Cycle Type
Op-Code
on DQ Bus
Control Bus
Comments
/E
/C
M
/W
/EC
Command read
Command write
Command write
Command write
Command write
Command write
Command write
Command write
TCO DS
FFFFH
TCO CT
0000H
TCO PA
nnnnH
SFF
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Command write
Command write
Command write
Command write
Command write
Command write
TCO CT
0000H
TCO CT
8040H
TCO SC
3808H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Command write
SPS M@HM
L
L
L
H
Clear power-up anomalies
Target Device Select register to disable local device selection.
Disable Device Select feature.
Target Control register for reset.
Causes Reset.
Target Page Address register to set page for cascaded operation.
Page Address value.
Set Full flag; allows access to next device (repeat previous
two cycles plus this one for each device in chain.
Target Control register for reset of Full flags, but not Page address.
Causes Reset.
Target Control register for initial values.
Control register value.
Target Segment Count Control register
Set both Segment counters to write to Segment 1, 2, and 3, and read from
Segment 0.
Set Data reads from Segment 0 of the Highest-Priority match
Notes
1
2
2
2,3
1
1
4
4
4
Notes:
1.
2.
3.
4.
Toggling the /RESET pin generates the same effect as this reset of the Control register, but good programming practice dictates a software reset for
initialization to account for all possible prior conditions.
This instruction may be omitted for a single LANCAM application.
The last SFF causes the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA to read out a
particular chip prior to a match condition.
A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison masking; and
Enable address increment. See Table on page 23 for Control Register bit assignments
Rev. 1
17
LANCAM A/L series (not recommended for new designs)
Instruction Set Descriptions
INSTRUCTION SET DESCRIPTIONS
Notes: Instruction cycle lengths given in Table 6 on page 22. If f=1, the instruction requires an absolute address to be supplied on the
following cycle as a Command write. The value supplied on the second cycle of the instruction updates the address register. After
operations involving M@[AR] or M@aaaH, the Address register increments or decrements depending on the setting in the Control
register.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write
cycle, so a value can be loaded or read out of the register.
Subsequent Command Read or Write cycles revert to
reading the Status register and writing to the Instruction
decoder. All registers but the NF, PS, and PD can be
written to, and all can be read from. The Status register is
only available through non-TCO Command Read cycles.
Reading the PS register also outputs the Device ID on bits
15–4 as shown in Persistent Source Register Bits on page
25.
f
Address Field flag
sss
Selected source
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source is at aaaH, after which
the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
mm
ddd
vvv
Address Field flag
Mask Register select
Selected destination
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction
changes it or a reset occurs. The default destination for
Data Write cycles is the Comparand register after a reset.
When the destination is the Comparand register or the
Memory array, the data written may be masked by either
Mask Register 1 or Mask Register 2, so that only
destination bits corresponding to bits in the Mask register
set to 0 are modified. An automatic compare occurs after
writing the last segment of the Comparand or Mask
registers, but not after writing to Memory. Setting the
persistent destination to M@aaaH loads the Address
register with “aaaH,” and the first access to that persistent
destination is at aaaH, after which the AR value
increments or decrements as set in the Control register.
The SPD M@[AR] instruction does the same except the
current Address Register value is used.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
f
mm
ddd
sss
v
Address Field flag
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
The MOV instruction performs a 64-bit move of the data
in the selected source to the selected destination. If the
source or destination is aaaH, the Address register is set to
“aaaH.” For MOV instructions to or from aaaH or [AR],
the Address register increments or decrements from that
value after the move completes, as set in the Control
register. Data transfers between the Memory array and the
Comparand register may be masked by either Mask
Register 1 or Mask Register 2, in which case, only those
bits in the destination that correspond to bits in the
selected Mask register set to 0 are changed. A Memory
location used as a destination for a MOV instruction may
be set to Valid or left unchanged. If the source and
destination are the same register, no net change occurs (a
NOP).
18
Rev. 1
Instruction Set Descriptions
LANCAM A/L series (not recommended for new designs)
Instruction: Validity Bit Control (VBC)
Binary Op-Code: 0000 f100 00dd dvvv
An RSC instruction resets the Segment Control register
count values for both the Destination and Source counters
to the original Start limits.
f
Address Field flag
ddd
Destination of data
vvv
Validity setting for Memory location
The VBC instruction sets the Validity bits at the selected
memory locations to the selected state. This feature can be
used to find all valid entries by using a repetitive sequence
of CMP V through a mask of all 1s followed by a VBC
HM, S. If the VBC target is aaaH, the Address register is
set to “aaaH.” For VBC instructions to or from aaaH or
[AR], the Address register increments or decrements from
that value after the operation completes, as set in the
Control register.
The Shift instructions shift the designated register one bit
right or left. The right and left limits for shifting are
determined by the CAM/RAM partitioning set in the
Control register. The Comparand register is a
barrel-shifter, and for the example of a device set to 64 bits
of CAM executing a Shift Comparand Right instruction,
bit 0 is moved to bit 63, bit 1 is moved to bit 0, and bit 63
is moved to bit 62. For a Shift Comparand Left instruction,
bit 63 is moved to bit 0, bit 0 is moved to bit 1, and bit 62
is moved to bit 63. MR2 acts as a sliding mask, where for
a Shift Right instruction bit 1 is moved to bit 0, while bit 0
“falls off the end,” and bit 63 is replicated to bit 62. For a
Shift Mask Left instruction, bit 0 is replicated to bit 1, bit
62 is moved to bit 63, and bit 63 “falls off the end.” With
shorter width CAM fields, the bit limits on the right or left
move to match the width of CAM field.
Instruction: Compare (CMP)
Binary Op-Code: 0000 0101 0000 0vvv
vvv
Validity condition
A CMP V, S, or R instruction forces a Comparison of
Valid, Skipped, or Random entries against the Comparand
register through a Mask register, if one is selected. During
a CMP E instruction, the compare is only done on the
Validity bits and all data bits are automatically masked.
Instruction: Set Full Flag (SFF)
Binary Op-Code: 0000 0111 0000 0000
The SFF instruction is a special instruction used to force
the Full flag LOW to permit setting the Page Address
register in vertically cascaded systems.
Instruction: Special Instructions
Binary Op-Code: 0000 0110 00dd drrr
Instruction: No Operation (NOP)
Binary Op-Code: 0000 0011 0000 0000
ddd
Target resource
rrr
Operation
These instructions are a special set for the LANCAM to
accommodate the added features over the MU9C1480.
Two alternate sets of configuration registers can be
selected by using the Select Foreground and Select
Background Registers instructions. These registers are the
Control, Segment Control, Address, Mask Register 1, and
the PS and PD registers.
Rev. 1
The NOP (No-OP) belongs to the MOV instructions,
where a register is moved to itself. No change occurs
within the device. This instruction is useful in unlocking
the daisy chain in Standard mode.
19
LANCAM A/L series (not recommended for new designs)
Instruction Set Summary
INSTRUCTION SET SUMMARY
Mnemonic Format: INS dst, src[msk], val
Instruction: Select Persistent Destination (continued)
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Operation
Mnemonic
Mem. at Highest-Prio. Match, Skip
SPD M@HM,S
Operation
Mnemonic
SPD M@HM[MR1],S
016EH
Masked by MR2
SPD M@HM[MR2],S
01AEH
SPD M@HM,R
012FH
Masked by MR1
SPD M@HM[MR1],R
016FH
Masked by MR2
SPD M@HM[MR2],R
01AFH
Mem. at Next Free Addr., Valid
Op-Code
Comparand Register
SPS CR
0000H
Mask Register 1
SPS MR1
0001H
Mask Register 2
SPS MR2
0002H
Memory Array at Addr. Reg.
SPS M@[AR]
0004H
Memory Array at Address
SPS M@aaaH
0804H
Mem. at Highest-Priority Match
SPS M@HM
0005H
Masked by MR1
Masked by MR2
Mem. at Next Free Addr., Empty
Comparand Register
Mnemonic
0174H
SPD M@NF[MR2],V
01B4H
SPD M@NF,E
0135H
0175H
MaskedbyMR2
SPD M@NF[MR2],E
01B5H
Masked by MR1
Mem. at Next Free Addr., Random
Op-Code
0134H
SPD M@NF[MR1],V
SPD M@NF[MR1],E
Masked by MR2
Operation
SPD M@NF,V
MaskedbyMR1
Mem. at Next Free Addr., Skip
Instruction: Select Persistent Destination
012EH
Masked by MR1
Mem. at High.-Prio. Match, Random
Instruction: Select Persistent Source
Op-Code
SPD M@NF,S
0136H
SPD M@NF[MR1],S
0176H
SPD M@NF[MR2],S
01B6H
SPD M@NF,R
0137H
Masked by MR1
SPD M@NF[MR1],R
0177H
Masked by MR2
SPD M@NF[MR2],R
01B7H
SPD CR
0100H
Masked by MR1
SPD CR[MR1]
0140H
Masked by MR2
SPD CR[MR2]
0180H
Mask Register 1
SPD MR
0108H
Operation
Mnemonic
Mask Register 2
SPD MR2
0110H
Control Register
TCO CT
0200H
Mem. at Addr. Reg. set Valid
SPD M@[AR],V
0124H
Page Address Register
TCO PA
0208H
Instruction: Temporary Command Override
Op-Code
Masked by MR1
SPD M@[AR][MR1],V
0164H
Segment Control Register
TCO SC
0210H
Masked by MR2
SPD M@[AR][MR2],V
01A4H
Read Next Free Address
TCO NF
0218H
SPD M@[AR],E
0125H
Address Register
TCO AR
0220H
Masked by MR1
SPD M@[AR][MR1],E
0165H
Device Select Register
TCO DS
0228H
Masked by MR2
SPD M@[AR][MR2],E
01A5H
Read Persistent Source
TCO PS
0230H
SPD M@[AR],S
0126H
Read Persistent Destination
TCO PD
0238H
Mem. at Addr. Reg. set Empty
Mem. at Addr. Reg. set Skip
Masked by MR1
SPD M@[AR][MR1],S
0166H
Masked by MR2
SPD M@[AR][MR2],S
01A6H
SPD M@[AR],R
0127H
Instruction: Data Move
Mem. at Addr.Reg. set Random
Masked by MR1
SPD M@[AR][MR1],R
0167H
Operation
Masked by MR2
SPD M@[AR][MR2],R
01A7H
Comparand Register from:
Memory at Address set Valid
Mnemonic
Op-Code
SPD M@aaaH,V
0924H
No Operation
NOP
0300H
Masked by MR1
SPD M@aaaH[MR1],V
0964H
Mask Register 1
MOV CR,MR1
0301H
Masked by MR2
SPD M@aaaH[MR2],V
09A4H
Mask Register 2
MOV CR,MR2
0302H
SPD M@aaaH,E
0925H
Memory at Address Reg.
MOV CR,[AR]
0304H
0344H
Memory at Address set Empty
Masked by MR1
SPD M@aaaH[MR1],E
0965H
Masked by MR1
MOV CR,[AR][MR1]
Masked by MR2
SPD M@aaaH[MR2],E
09A5H
Masked by MR2
MOV CR,[AR][MR2]
0384H
SPD M@aaaH,S
0926H
Memory at Address
MOV CR,aaaH
0B04H
Memory at Address set Skip
Masked by MR1
SPD M@aaaH[MR1],S
0966H
Masked by MR1
MOV CR,aaaH[MR1]
0B44H
Masked by MR2
SPD M@aaaH[MR2],S
09A6H
Masked by MR2
MOV CR,aaaH[MR2]
0B84H
SPD M@aaaH,R
0927H
Masked by MR1
SPD M@aaaH[MR1],R
0967H
Masked by MR2
SPD M@aaaH[MR2],R
09A7H
SPD M@HM,V
012CH
Mask Register 1 from:
Memory at Address set Random
Mem. at Highest-Prio. Match, Valid
Mem. at Highest-Prio. Match
MOV CR,HM
0305H
MaskedbyMR1
MOV CR,HM[MR1]
0345H
MaskedbyMR2
MOV CR,HM[MR2]
0385H
Masked by MR1
SPD M@HM[MR1],V
016CH
Comparand Register
MOV MR1,CR
0308H
Masked by MR2
SPD M@HM[MR2],V
01ACH
No Operation
NOP
0309H
030AH
Mem. at Highest-Prio. Match, Emp.
SPD M@HM,E
012DH
Mask Register 2
MOV MR1,MR2
Masked by MR1
SPD M@HM[MR1],E
016DH
Memory at Address Reg.
MOV MR1,[AR]
030CH
Masked by MR2
SPD M@HM[MR2],E
01ADH
Memory at Address
MOV MR1,aaaH
0B0CH
Mem. at Highest-Prio. Match
MOV MR1,HM
030DH
20
Rev. 1
Instruction Set Summary
LANCAM A/L series (not recommended for new designs)
Instruction: Data Move (continued)
Instruction: Validity Bit Control
Operation
Mnemonic
Op-Code
Operation
Mask Register 2 from:
Mnemonic
Op-Code
0424H
Set Validity bits at Address Register
Comparand Register
MOV MR2,CR
0310H
Set Valid
VBC [AR],V
Mask Register 1
MOV MR2,MR1
0311H
Set Empty
VBC [AR],E
0425H
No Operation
NOP
0312H
Set Skip
VBC [AR],S
0426H
Set Random Access
VBC [AR],R
0427H
Set Valid
VBC aaaH,V
0C24H
Set Empty
VBC aaaH,E
0C25H
Set Skip
VBC aaaH,S
0C26H
Set Random Access
VBC aaaH,R
0C27H
Memory at Address Reg.
MOV MR2,[AR]
0314H
Memory at Address
MOV MR2,aaaH
0B14H
Mem. at Highest-Prio. Match
MOV MR2,HM
0315H
Set Validity bits at Address
Memory at Address Register, No Change to Validity bits, from:
Comparand Register
MOV [AR],CR
0320H
Masked by MR1
MOV [AR],CR[MR1]
0360H
Masked by MR2
MOV [AR],CR[MR2]
03A0H
Mask Register 1
MOV [AR],MR1
0321H
Set Valid
VBC HM,V
042CH
Mask Register 2
MOV [AR],MR2
0322H
Set Empty
VBC HM,E
042DH
Set Skip
VBC HM,S
042EH
Set Random Access
VBC HM,R
042FH
Set Validity bits at Highest-Priority Match
Memory at Address Register, Location set Valid, from:
Comparand Register
Masked by MR1
Masked by MR2
MOV [AR],CR,V
0324H
MOV [AR],CR[MR1],V
0364H
Set Validity bits at All Matching Locations
MOV [AR],CR[MR2],V
03A4H
Set Valid
VBC ALM,V
043CH
Mask Register 1
MOV [AR],MR1,V
0325H
Set Empty
VBC ALM,E
043DH
Mask Register 2
MOV [AR],MR2,V
0326H
Set Skip
VBC ALM,S
043EH
Set Random Access
VBC ALM,R
043FH
Operation
Mnemonic
Op-Code
Compare Valid Locations
CMP V
Compare Empty Locations
CMP E
0505H
Compare Skipped Locations
CMP S
0506H
Comp. Random Access Locations
CMP R
0507H
Memory at Address, No Change to Validity bits, from:
Comparand Register
MOV aaaH0,CR
0B20H
Masked by MR1
MOV aaaH,CR[MR1]
0B60H
Masked by MR2
MOV aaaH,CR[MR2]
0BA0H
Mask Register 1
MOV aaaH,MR1
0B21H
Mask Register 2
MOV aaaH,MR2
0B22H
Instruction: Compare
Memory at Address, Location set Valid, from:
Comparand Register
MOV aaaH,CR,V
0B24H
Masked by MR1
MOV aaaH,CR[MR1],V
0B64H
Masked by MR2
MOV aaaH,CR[MR2],V
0BA4H
Mask Register 1
MOV aaaH,MR1,V
0B25H
Mask Register 2
MOV aaaH,MR2,V
0B26H
Instruction: Special Instructions
Memory at Highest-Priority Match, No Change to Validity bits, from:
Comparand Register
Masked by MR1
Masked by MR2
MOV HM,CR
MOV HM,CR[MR1]
MOV HM,CR[MR2]
0328H
0368H
03A8H
Mask Register 1
MOV HM,MR1
0329H
Mask Register 2
MOV HM,MR2
032AH
Memory at Highest-Priority Match, Location set Valid, from:
Comparand Register
MOV HM,CR,V
032CH
Masked by MR1
MOV HM,CR[MR1],V
036CH
Masked by MR2
MOV HM,CR[MR2],V
03ACH
Mask Register 1
MOV HM,MR1,V
032DH
Mask Register 2
MOV HM,MR2,V
032EH
0504H
Operation
Mnemonic
Shift Comparand Right
SFT CR, R
Op-Code
Shift Comparand Left
SFT CR, L
0601H
Shift Mask Register 2 Right
SFT M2, R
0610H
Shift Mask Register 2 Left
SFT M2, L
0611H
Select Foreground Registers
SFR
0618H
Select Background Registers
SBR
0619H
Reset Seg. Cont. Reg. to Initial Val.
RSC
061AH
0600H
Instruction: Miscellaneous
Operation
Mnemonic
MOV NF,CR
0330H
No Operation
NOP
0300H
Masked by MR1
MOV NF,CR[MR1]
0370H
Set Full Flag
SFF
0700H
Masked by MR2
Memory at Next Free Address, No Change to Validity bits, from:
Comparand Register
MOV NF,CR[MR2]
03B0H
Mask Register 1
MOV NF,MR1
0331H
Mask Register 2
MOV NF,MR2
0332H
Memory at Next Free Address, Location set Valid, from:
Comparand Register
MOV NF,CR,V
0334H
Masked by MR1
MOV NF,CR[MR1],V
0374H
Masked by MR2
MOV NF,CR[MR2],V
03B4H
Mask Register 1
MOV NF,MR1,V
0335H
Mask Register 2
MOV NF,MR2,V
0336H
Rev. 1
21
Op-Code
LANCAM A/L series (not recommended for new designs)
Instruction Set Summary
Instruction Cycle Lengths
Table 6: Instruction Cycle Lengths
Cycle
Length
Short
Medium
Long
Cycle Type
Command Write
Command Read
Data Read
Comparand register
(not last segment)
Mask register
(not last segment)
MOV reg, reg (except -70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC
NOP (except -70)
SFT (8480B)
MOV reg, mem
MOV reg, reg (-70)
TCO CT (reset)
VBC (NFA invalid)
SFT (except 8480B)
NOP (-70)
Data Write
Status register or
16-bit register Sheets
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
VBC (NFA valid)
Memory array
(NFA invalid)
Comparand register
Mask register
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Memory array
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the
tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the first
cycle is short, and the second cycle is the length given.
22
Rev. 1
Register Bit Assignments
LANCAM A/L series (not recommended for new designs)
REGISTER BIT ASSIGNMENTS
Control Register Bits
Device
Bit(s)
Name
Description
RST
0 = Reset
14:13
Match Flag
00 = Enable
01 = Disable
10 = Reserved
11 = No Change
12:11
Full Flag
00 = Enable
01 = Disable
10 = Reserved
11 = No Change
10:9
Translation
00 = Input Not Translated
01 = Input Translated
10 = Reserved
11 = No Change
8:6
CAM/RAM Part
000 = 64 CAM/0 RAM
001 = 48 CAM/16 RAM
010 = 32 CAM/32 RAM
011 = 16 CAM/48 RAM
100 = 48 RAM/16 CAM
101 = 32 RAM/32 CAM
110 = 16 RAM/48 CAM
111 = No Change
5:4
Comp. Mask
00 = None
01 = MR1
10 = MR2
11 = No Change
3:2
AR Inc/Dec
00 = Increment
01 = Decrement
10 = Disable
11 = No Change
1:0
Mode
00 = Standard
01 = Enhanced
10 = Reserved
11 = No Change
15
All
Note: D15 reads back as 0.
Segment Control Register Bits
Device
Bit(s)
Name
Description
SDL
0 = Set Destination Segment Limits
1 = No Change
14:13
DCSL
00–11 = Destination Count Start Limit
12:11
DCEL
00–11 = Destination Count End Limit
SSL
0 = Set Source Segment Limits
1 = No Change
15
10
All
9:8
SCSL
00–11 = Source Count Start Limit
7:6
SCEL
00–11 = Source Count End Limit
5
LDC
0 = Load Destination Segment Count
1 = No Change
4:3
2
1:0
DSCV
00–11 = Destination Seg. Count Value
LSC
0 = Load Source Segment Count
1 = No Change
SSCV
00–11 = Source Segment Count Value
Note: D15, D10, D5, and D2 are read back as 0s.
Rev. 1
23
LANCAM A/L series (not recommended for new designs)
Register Bit Assignments
Next Free Address Bits
Device
3480A/L
5480A/L
1480A/L
2480A/L
4480A/L
Bit(s)
Name
Description
15:8
PA7–0
Page Address
7:0
NF7-0
Next Free Address
15:9
PA6-0
Page Address
8:0
NF8-0
Next Free Address
15:10
PA5–0
Page Address
9:0
NF9-0
Next Free Address
15:11
PA4-0
Page Address
10:0
NF10-0
Next Free Address
15:12
PA3–0
Page Address
11:0
NF11-0
Next Free Address
Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO
NF instruction.
Status Register Bits
Device
All
Bit(s)
Name
Description
31
/FL
0 = Internal CAM Full
30
/MM
0 = Internal Multiple Match
VB1-0
00 = Valid
01 = Empty
0
Reserved
26:16
PA15-5
Page Address (second read)
15:11
PA4-0
Page Address (first read)
10:9
0
Reserved
8:1
AM7-0
Match Address
29:28
27
3480A/L
27
5480A/L
1480A/L
2480A/L
4480A/L
All
10 = Skip
11 = RAM
0
Reserved
26:16
PA15-5
Page Address (second read)
15:11
PA4-0
Page Address (first read)
10
0
Reserved
9:1
AM8-0
Match Address
27
0
Reserved
26:16
PA15–5
Page Address (second read)
15:11
PA4–0
Page Address (first read)
10:1
AM9–0
Match Address
27:16
PA15–4
Page Address (second read)
15:12
PA3–0
Page Address (first read)
11:1
AM10–0
Match Address
27:16
PA14–3
Page Address (second read)
15:13
PA2–0
Page Address (first read)
12:1
AM11–0
Match Address
/MA
Match Flag
0
Note: The Status register is read only, and is accessed by performing Command Read cycles. On the first cycle, bits 15–0 are output,
and if a second Command Read cycle is issued immediately after the first Command Read cycle, bits 31–16 are output.
24
Rev. 1
Register Bit Assignments
LANCAM A/L series (not recommended for new designs)
Persistent Source Register Bits
Device
Bit(s)
Name
Description
3480A/L
15:4
DEVID
Device ID = 341H
5480A/L
15:4
DEVID
Device ID = 541H
1480A/L
15:4
DEVID
Device ID = 141H
2480A/L
15:4
DEVID
Device ID = 240H
4480A/L
15:4
DEVID
Device ID = 440H
All
3:0
PS
Persistent Source Setting
Note: The Persistent Source register is read only, and is accessed by performing a Command Read cycle immediately following a TCO
PS instruction.
Rev. 1
25
LANCAM A/L series (not recommended for new designs)
Electrical
ELECTRICAL
Absolute Maximum Ratings
Supply Voltage:
"A"
"L"
-0.5 to 7.0 Volts
-0.5 to 4.6 Volts
Voltage on all other pins
-0.5 to VCC +0.5 Volts
(-2 Volts for 10 ns, measured at the 50% point)
Temperature under bias
-55° C to 125° C
Storage Temperature
-55° C to 125° C
DC Output Current
20 mA (per output, one at a time, one second
duration)
Stresses exceeding those listed under Absolute Maximum
Ratings may induce failure. Exposure to absolute maximum
ratings for extended periods may reduce reliability.
Functionality at or above these conditions is not implied.
All voltages referenced to GND.
Operating Conditions
Voltages referenced to GND at the device pin.
Symbol
Parameter
Min.
Typical
Max.
Units
"A" parts
4.75
5.0
5.25
Volts
"L" parts
3.0
3.3
VCC
Operating supply voltage
3.6
Volts
VIH
Input voltage logic 1
2.0
VCC + 0.5
Volts
VIL
Input voltage logic 0
-0.5
0.8
Volts
TA
Ambient operating temperature
Commercial
0
70
°C
Industrial
-40
85
°C
Notes
1, 2
Still air
Notes:
1.
2.
1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 11 on page 27).
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.
Average Power Supply Current (mA)
-50
Device
Typ.
-70
Max.
-90
Typ.
Max.
Typ.
Max.
3480A
35
55
30
50
3480L
25
40
20
30
5480A
35
55
30
50
5480L
1480A
25
40
20
35
75
110
50
80
40
75
30
50
125
160
90
120
70
100
1480L
2480A
2480L
60
90
50
80
4480A
170
200
130
160
4480L
110
140
85
110
DC Electrical Characteristics
Symbol
Parameter
ICC(SB)
Stand-by power supply current
VOH
Output voltage logic 1
VOL
Output voltage logic 0
IIZ
Input leakage current
Min
.
Typical
Max.
Units
2
mA
/E = HIGH
Volts
IOH = -2.0 mA
Volts
IOL = 4.0 mA
2.4
0.4
Notes
Others
-2
+2
μA
/RESET
6
9
15
Kohms
VIN = 0 V
Test1,
Test2
6
10
13
Kohms
VIN = VCC;10
26
VSS ≤ VIN ≤ VCC
Rev. 1
Switching
Symbol
IOZ
LANCAM A/L series (not recommended for new designs)
Parameter
Min
.
Output leakage current
-10
Typical
Max.
Units
10
μA
Notes
VSS ≤ VOUT ≤ VCC
DQN = High Impedance
Capacitance
Symbol
CIN
COUT
Parameter
Max.
Units
Notes
Input capacitance
6
pF
f = 1 MHz, VIN = 0V
Output capacitance
7
pF
f = 1 MHz, VOUT = 0V
AC Test Conditions
Table 7: AC Test Conditions
Input Signal Transitions
0.0 Volts to 3.0 Volts
Input Signal Rise Time
< 3 ns
Input Signal Fall Time
< 3 ns
Input Timing Reference Level
1.5 Volts
Output Timing Reference Level
1.5 Volts
SWITCHING
Switching Test Figures
Vcc
R1
Input
Waveform
Device
Under Test
0V
V IL ( MIN)
C1
50% Amplitude
Point
R2
10ns
Figure 10: AC Test Load
Figure 11: Input Signal Waveform
Switching Test Figures Component Values
Table 8: Switching Test Figures Component Values
Parameter
"A" Devices
"L" Devices
Units
VCC
5.0
3.3
Volts
R1
961
635
Ohms
R2
510
702
Ohms
Test Load A
30
30
pF
Test Load B
5
5
pF
C1 (includes jig)
Rev. 1
27
LANCAM A/L series (not recommended for new designs)
Switching
Switching Characteristics
Table 9: Switching Characteristics
Cycle Time
No.
Symbol
Parameter
1
tELEL
Chip Enable Compare Cycle Time
2
tELEH
Chip Enable LOW Pulse Width
-50
Min.
-70
Max.
Min.
-90
Max.
Min.
Max
Notes
50
70
90
Short Cycle
15
15
25
4
Medium Cycle
30
35
50
4
Long Cycle
45
55
75
4
3
tEHEL
Chip Enable HIGH Pulse Width
5
15
15
4
tCVEL
Control Input to Chip Enable LOW Setup Time
2
2
2
5
5
tELCX
Control Input from Chip Enable LOW Hold Time
10
10
10
5
6
tELQX
Chip Enable LOW to Outputs Active
3
3
3
6
7
tELQV
Chip Enable LOW to Outputs Valid
8
tEHQZ
Chip Enable HIGH to Outputs HIGH-Z
3
9
tDVEL
Data to Chip Enable LOW Setup Time
2
2
2
10
tELDX
Data from Chip Enable LOW Hold Time
10
10
10
11
tFIVEL
Full In Valid to Chip Enable LOW Setup Time
0
0
0
12
tFIVFFV
Full In Valid to Full Flag Valid
5
5
7
13
tELFFV
Chip Enable LOW to Full Flag Valid
35
50
75
14
tMIVEL
Match in Valid to Chip Enable LOW Setup Time
0
0
0
15
tEHMFX
Chip Enable HIGH to /MF, /MA, /MM Invalid
0
0
0
16
tMIVMFV
17
Register Read
30
30
50
4,6
Memory Read
40
52
75
4,6
15
7
10
3
10
3
Match In Valid to /MF Valid, /MA, /MM
4
5
7
tEHMFV
Chip Enable HIGH to /MF Valid
16
16
25
18
tEHMXV
Chip Enable HIGH to /MA and /MM Valid
18
18
25
19
tRLRH
Reset LOW Pulse Width
50
100
100
8
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 11 on page 27).
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.
Over ambient operating temperature range and Vcc(min.) to Vcc(max.).
See Table 6 on page 22.
Control signals are /W, /CM, and /EC.
With load specified in Figure 10 on page 27, Test Load A.
With load specified in Figure 10 on page 27, Test Load B.
/E must be HIGH during this period to ensure accurate default values in the configuration registers.
With output and I/O pins unloaded.
TEST1 and/or TEST2 may not be implemented on all versions of these products.
28
Rev. 1
Timing Diagrams
LANCAM A/L series (not recommended for new designs)
TIMING DIAGRAMS
2
2
3
3
/E
/E
4
4
5
4
5
9
10
5
/W
/W
4
5
/CM
/C M
4
5
DQ15 - 0
/EC
11
7
8
/FI
DQ1 5 - 0
12
13
6
/FF
Figure 12: Read Cycle
Figure 13: Write Cycle
1
2
3
/E
4
5
4
5
/W
/CM
VALID
4
5
/EC
14
/MI
15
16
/MF
17
/MA, /MM
18
Figure 14: Compare Cycle
Rev. 1
29
LANCAM A/L series (not recommended for new designs)
PLCC Package
PLCC PACKAGE
44-Pin PLCC
Figure 15: 44-Pin PLCCPackage
Table 10: 44-Pin PLCC Dimensions
Dimensions are in inches:
44-PIN
PLCC
Dim. A
Dim. B
Dim. C
Dim. D
Dim. E
Dim. E1
Dim. F
Dim. F1
Dim. a
Dim. b
0.170
0.017
0.018
0.100
0.650
0.685
0.590
0.050
3°
43°
0.180
TYP
0.032
TYP
0.656
0.695
0.630
TYP
6°
47°
30
Rev. 1
Ordering Information
LANCAM A/L series (not recommended for new designs)
ORDERING INFORMATION
Part Number
Cycle Time
Package
Temperature
Voltage
MU9C4480A-70DC
MU9C4480A-90DC
MU9C4480A-70DI
MU9C4480A-90DI
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
-40–85° C
5.0 ± 0.25
MU9C2480A-50DC
MU9C2480A-70DC
MU9C2480A-90DC
MU9C2480A-70DI
MU9C2480A-90DI
50 ns
70 ns
90 ns
70 ns
90 bs
44-Pin PLCC
0–70° C
0–70° C
0–70° C
-40–85° C
-40–85° C
5.0 ± 0.25
MU9C1480A-50DC
MU9C1480A-70DC
MU9C1480A-90DC
MU9C1480A-70DI
MU9C1480A-90DI
50 ns
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
0–70° C
-40–85° C
-40–85° C
5.0 ± 0.25
MU9C5480A-70DC
MU9C5480A-90DC
MU9C5480A-70DI
MU9C5480A-90DI
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
-40–85° C
5.0 ± 0.25
MU9C3480A-70DC
MU9C3480A-90DC
MU9C3480A-70DI
MU9C3480A-90DI
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
-40–85° C
5.0 ± 0.25
MU9C4480L-70DC
MU9C4480L-90DC
MU9C4480L-70DI
MU9C4480L-90DI
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
-40–85° C
3.3 ± 0.3
MU9C2480L-70DC
MU9C2480L-90DC
MU9C2480L-70DI
MU9C2480L-90DI
70 ns
90 ns
70 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
-40–85° C
3.3 ± 0.3
MU9C1480L-90DC
MU9C1480L-90DI
90 ns
90 ns
44-Pin PLCC
0–70° C
-40–85° C
3.3 ± 0.3
MU9C5480L-70DC
MU9C5480L-90DC
MU9C5480L-90DI
70 ns
90 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
3.3 ± 0.3
MU9C5480L-70DC
MU9C5480L-90DC
MU9C5480L-90DI
70 ns
90 ns
90 ns
44-Pin PLCC
0–70° C
0–70° C
-40–85° C
3.3 ± 0.3
ORDERING INFORMATION FOR LEAD-FREE PRODUCTS:
For ordering Lead-Free products please add an "F" directly after the product name (in front of the speed grade).
Example: MU9C4480LF-90DC
Rev. 1
31
LANCAM A/L series (not recommended for new designs)
MUSIC Semiconductors’ agent or distributor:
Worldwide Headquarters
MUSIC Semiconductors
5850 T.G. Lee Blvd, Suite 345
Orlando, FL 32822
USA
Tel: 407 850-1035
Fax: 407 850-1063
Ordering Information
MUSIC Semiconductors reserves the right to make changes to its products and specifications at
any time in order to improve on performance, manufacturability or reliability. Information
furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC
Semiconductors for the use of said information, nor for any infringements of patents or of other
third-party rights which may result from said use. No license is granted by implication or
otherwise under any patent or patent rights of any MUSIC company.
© Copyright 2000 and 2002, MUSIC Semiconductors
North American Sales
MUSIC Semiconductors
121 Union Ave. , Suite 1
Middlesex, NJ 08846
USA
Tel: 732 469-1886
Fax: 732 469-2397
USA Only: 800 933-1550 Tech Support
888 226-6874 Product Info
Asian Headquarters
MUSIC Semiconductors
110 Excellence Ave., SEPZ 1
Carmelray Industrial Park
Canlubang, Laguna
Philippines 4028
Tel: +63 49 549-1480
Fax: +63 49 549-1024
Sales Tel/Fax: +632 723-6215
http: //www.musicsemi.com
European Headquarters
MUSIC Semiconductors
Raadhuisplein 10
6436 BW Amstenrade
The Netherlands
Tel: +31 43 455-2675
Fax: +31 43 455-1573
email: [email protected]
32
Rev. 1