Dual, 16-Bit, 125 MSPS Serial LVDS, 1.8 V Analog-to-Digital Converter AD9655 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AGND VINA+ VINA– PLL, SERIALIZER AND DDR LVDS DRIVERS AD9655 16 16-BIT PIPELINE ADC 16 VCM VINB+ VINB– 16 16-BIT PIPELINE ADC 16 REFERENCE SERIAL PORT INTERFACE 1 TO 8 CLOCK DIVIDER SCLK/ SDIO/ CSB DFS PDWN CLK+ CLK– D0A+ D0A– D1A+ D1A– D0B+ D0B– D1B+ D1B– DCO+ DCO– FCO+ FCO– 12737-001 1.8 V supply operation Low power: approximately 150 mW/channel at 125 MSPS, 2 V p-p input range (typical) SNR/SFDR at 69.5 MHz 77.5 dBFS/88 dBc, 2.0 V p-p input range (typical) 79.3 dBFS/84 dBc, 2.8 V p-p input range (typical) Linearity DNL = ±0.7 LSB; INL = ±4.0 LSB (typical, 2.0 V p-p input span) DNL = ±0.7 LSB; INL = ±3.4 LSB (typical, 2.8 V p-p input span) Serial LVDS, two data lanes per ADC channel 500 MHz full power analog bandwidth Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Standby mode Figure 1. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging and ultrasound Radar/LIDAR GENERAL DESCRIPTION The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. External reference or driver components are not required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Rev. 0 Individual channel power-down is supported. The AD9655 typically consumes less than 2 mW in serial port interface (SPI) power-down mode. The available digital test pat-terns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. The AD9655 is available in an RoHS-compliant, 32-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This device is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Two ADCs are contained in a small, space-saving package. Pin Compatible. The AD9655 is pin compatible to the AD9645 14-bit and AD9635 12-bit dual ADCs. Ease of Use. A DCO operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. 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AD9655 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 22 Applications ....................................................................................... 1 Power Dissipation and Power-Down Mode ........................... 23 General Description ......................................................................... 1 Digital Outputs and Timing ..................................................... 24 Functional Block Diagram .............................................................. 1 Output Test Modes ..................................................................... 27 Product Highlights ........................................................................... 1 Serial Port Interface (SPI) .............................................................. 28 Revision History ............................................................................... 2 Configuration Using the SPI ..................................................... 28 Specifications..................................................................................... 3 Hardware Interface ..................................................................... 29 DC Specifications ......................................................................... 3 Configuration Without the SPI ................................................ 29 AC Specifications.......................................................................... 5 SPI Accessible Features .............................................................. 29 Digital Specifications ................................................................... 7 Memory Map .................................................................................. 30 Switching Specifications .............................................................. 8 Reading the Memory Map Register Table............................... 30 Timing Specifications .................................................................. 8 Memory Map Register Table ..................................................... 31 Absolute Maximum Ratings .......................................................... 10 Memory Map Register Descriptions ........................................ 34 Thermal Resistance .................................................................... 10 Applications Information .............................................................. 36 ESD Caution ................................................................................ 10 Design Guidelines ...................................................................... 36 Pin Configuration and Function Descriptions ........................... 11 Power and Ground Guidelines ................................................. 36 Typical Performance Characteristics ........................................... 12 Clock Stability Considerations ................................................. 36 VREF = 1.0 V ................................................................................. 12 Exposed Pad Thermal Heat Slug Recommendations ............ 36 VREF = 1.4 V ................................................................................. 15 VCM ............................................................................................. 36 Equivalent Circuits ......................................................................... 18 Reference Bypassing................................................................... 36 Theory of Operation ...................................................................... 19 SPI Port ........................................................................................ 36 Analog Input Considerations.................................................... 19 Outline Dimensions ....................................................................... 37 Voltage Reference ....................................................................... 20 Ordering Guide .......................................................................... 37 REVISION HISTORY 1/15—Revision 0: Initial Version Rev. 0 | Page 2 of 37 Data Sheet AD9655 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p full-scale differential input mode, internal reference voltage (VREF) = 1.0 V, input amplitude (AIN) = −1.0 dBFS, 125 MSPS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Common-Mode Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD3 IDRVDD (ANSI-644 Mode)3 IDRVDD (Reduced Range Mode)3 TOTAL POWER CONSUMPTION Sine Wave Input (Two Channels, Including Output Drivers ANSI-644 Mode) Sine Wave Input (Two Channels, Including Output Drivers Reduced Range Mode) Power-Down Standby4 Temperature Min 16 Full 25°C 25°C 25°C 25°C 25°C 25°C Typ Max Guaranteed2 0.2 0.1 3.4 0.4 ±0.7 ±4.0 2 Rev. 0 | Page 3 of 37 % FSR % FSR % FSR % FSR LSB LSB Full Full −23 0.9 ppm/°C ppm/°C 25°C 25°C 25°C 1.0 2.9 7.5 V mV kΩ 25°C 2.7 LSB rms Full Full 25°C 25°C 25°C 2 0.9 V p-p V V kΩ pF Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 0.5 1.2 1.9 6.6 1.7 1.7 1.8 1.8 93 73 62 1.9 1.9 299 279 2 142 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. No missing codes guaranteed if Register 0x18 = 0x04 (default, no digital scaling of the output). 3 Measured with a low input frequency, −1 dBFS sine wave on both channels, DDR operation, and two-lane operation. 4 Standby mode can be controlled via the SPI. 1 Unit Bits V V mA mA mA mW mW mW mW AD9655 Data Sheet AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input mode, VREF = 1.4 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted. Table 2. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1.4 V Mode) Load Regulation at 1.0 mA (VREF = 1.4 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.4 V ANALOG INPUTS Differential Input Voltage (VREF = 1.4 V) Common-Mode Voltage Common-Mode Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD3 IDRVDD (ANSI-644 Mode)3 IDRVDD (Reduced Range Mode)3 TOTAL POWER CONSUMPTION Sine Wave Input (Two Channels, Including Output Drivers ANSI-644 Mode) Sine Wave Input (Two Channels, Including Output Drivers Reduced Range Mode) Power-Down Standby4 Temperature Min 16 Full Full Full Full Full Full 25°C Full 25°C Guaranteed2 −0.12 +0.2 +0.48 −0.2 +0.1 +0.33 −2.4 +2.8 +8.2 −1.2 +0.4 +1.9 −0.99 +1.43 ±0.7 −8.5 +8.5 ±3.4 Full Full −66 0.9 Full 25°C 25°C 1.37 Typ 1.38 186 7.5 Max 2 Rev. 0 | Page 4 of 37 % FSR % FSR % FSR % FSR LSB LSB LSB LSB ppm/°C ppm/°C 1.41 V mV kΩ 25°C 2 LSB rms Full Full 25°C 25°C 25°C 2.8 0.9 1.0 V p-p V V kΩ pF 1.8 1.8 101 73 62 1.9 1.9 111 79 68 V V mA mA mA 313 293 2 155 342 322 4 172 mW mW mW mW Full Full Full Full Full Full Full Full Full 0.7 1.9 6.6 1.7 1.7 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. No missing codes guaranteed if Register 0x18 = 0x04 (default, no digital scaling of the output). 3 Measured with a low input frequency, −1 dBFS sine wave on both channels, DDR operation, and two-lane operation. 4 Standby mode can be controlled via the SPI. 1 Unit Bits Data Sheet AD9655 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p full-scale differential input mode, VREF = 1.0 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted. Table 3. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 100.1 MHz, fIN2 = 102.1 MHz CROSSTALK2 CROSSTALK (OVERRANGE CONDITION)3 ANALOG INPUT BANDWIDTH, FULL POWER Temperature Min Typ Max Unit 25°C 25°C 25°C 25°C 25°C 25°C 77.9 77.9 77.5 76.6 75.6 71.0 dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 25°C 77.5 77.1 77.1 76.5 75.2 68.0 dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 25°C 12.6 12.5 12.5 12.4 12.2 11 Bits Bits Bits Bits Bits Bits 25°C 25°C 25°C 25°C 25°C 25°C 88 86 88 91 85 70 dBc dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 25°C 25°C −88 −86 −88 −91 −85 −70 dBc dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 25°C 25°C −95 −99 −92 −91 −89 −80 dBc dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 90 −104 −100 500 dBc dB dB MHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 69.5 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Measurements are taken using a less dense board to demonstrate the AD9655 crosstalk performance, not board limitations. 3 Overrange condition is specified as being 3 dB above the full-scale input range. 1 2 Rev. 0 | Page 5 of 37 AD9655 Data Sheet AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input mode, VREF = 1.4 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted. Table 4. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC) fIN = 9.7 MHz fIN = 19.7 MHz fIN = 69.5 MHz fIN = 100.5 MHz fIN = 139.5 MHz fIN = 301 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 100.1 MHz, fIN2 = 102.1 MHz CROSSTALK2 CROSSTALK (OVERRANGE CONDITION)3 ANALOG INPUT BANDWIDTH, FULL POWER Temperature 25°C 25°C Full 25°C 25°C 25°C Min Typ Max Unit 79.6 79.4 79.3 78.0 76.5 55.0 dBFS dBFS dBFS dBFS dBFS dBFS 79.1 78.3 77.8 77.0 75.8 54.8 dBFS dBFS dBFS dBFS dBFS dBFS 12.8 12.7 12.6 12.5 12.3 8.8 Bits Bits Bits Bits Bits Bits 88 85 84 83 82 68 dBc dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 25°C −88 −85 −84 −83 −82 −68 dBc dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 25°C −97 −98 −93 −91 −89 −72 25°C 25°C 25°C 25°C 85 −104 −103 500 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 78.0 77.2 12.5 80 −80 −85 dBc dBc dBc dBc dBc dBc dBc dB dB MHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 69.5 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Measurements are taken using a less dense board to demonstrate AD9655 crosstalk performance, not board limitations. 3 Overrange condition is specified as being 3 dB above the full-scale input range. 1 2 Rev. 0 | Page 6 of 37 Data Sheet AD9655 DIGITAL SPECIFICATIONS AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. Table 5. Parameter1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (SCLK/DFS) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/PDWN) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/PDWN)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temperature Min Full Full Full 25°C 25°C CMOS/LVDS/LVPECL 0.2 3.6 AGND − 0.2 AVDD + 0.2 0.9 15 4 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Typ Max V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF 26 2 26 5 1.79 0.05 2 Rev. 0 | Page 7 of 37 V V Full Full ±298 1.15 LVDS ±350 ±400 1.22 1.30 Twos complement mV V Full Full ±170 1.15 LVDS ±200 ±231 1.22 1.30 Twos complement mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO/PDWN pins sharing the same connection. 1 V p-p V V kΩ pF AVDD + 0.2 0.8 30 2 Full Full Unit AD9655 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. Table 6. Parameter1, 2 CLOCK3 Input Clock Rate Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD)4 Rise Time (tR)5 (20% to 80%) Fall Time (tF)5 (20% to 80%) FCO Propagation Delay (tFCO)4 DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA) 4, 6 FCO to DCO Delay (tFRAME) 4, 7 Data to Data Skew Wake-Up Time (Standby) Wake-Up Time (Power-Down)8 Pipeline Latency APERTURE Aperture Delay (tA)9 Aperture Uncertainty (Jitter, tJ5, 9) Out-of-Range Recovery Time Temperature Min Full Full Full Full 20 20 4.00 4.00 Full Full Full Full Full Full Full Full 25°C 25°C Full (tSAMPLE/4) + 5 (tSAMPLE/4) + 5 Typ (tSAMPLE/4) + 6.1 170 160 (tSAMPLE/4) + 6.1 tFCO + (tSAMPLE/16) + 0.2 (tSAMPLE/16) − 500 (tSAMPLE/16) + 10 ±37 250 250 16 25°C 25°C 25°C Max Unit 1000 125 MHz MSPS ns ns (tSAMPLE/4) + 7 ns ps ps ns ns ps ps ps ns ms Clock cycles (tSAMPLE/4) + 7 (tSAMPLE/16) + 100 (tSAMPLE/16) + 330 ±80 1 80 1 ns fs rms Clock cycles See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. The Output parameters can be adjusted via the SPI. The conversion rate is the clock rate after the divider. Valid for 2-lane operation. 4 tSAMPLE = tEH + tEL = 1/fS. tCPD, tDATA and tFRAME are adjustable with SPI Register 0x16. 5 This term does not appear in the Timing Diagrams section, which includes Figure 2 and Figure 3. 6 tDATA is the time from DCO rise or fall to output data rise or fall. 7 tFRAME is the time from FCO rise to DCO rise. 8 Wake-up time from power-down is defined as the time required to return to normal operation from SPI power-down mode. The value of 250 ms assumes a sample rate of 125 MSPS. About 31 × 106 sample clock cycles are required. 9 tA and tJ are with Register 0x09 = 0x04 (default, duty cycle stabilizer and clock divider are bypassed). 1 2 3 TIMING SPECIFICATIONS Table 7. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO1 tDIS_SDIO1 1 Description See Figure 68, unless otherwise noted Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge This parameter is not shown in Figure 68. Rev. 0 | Page 8 of 37 Limit Unit 4 2 40 2 2 10 10 10 ns min ns min ns min ns min ns min ns min ns min ns min 10 ns min Data Sheet AD9655 Timing Diagrams N–1 VINx± N tA tEH CLK– N+1 tEL CLK+ tCPD DCO– DDR DCO+ DCO– SDR DCO+ tFCO FCO– tFRAME FCO+ tPD D0A– BITWISE MODE tDATA D0A+ D14 N – 17 D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 D14 N – 16 D12 N – 16 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 MSB N – 17 D13 N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D13 N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 D07 N – 17 D06 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D2 N – 17 D01 N – 17 LSB N – 17 D07 N – 16 D06 N – 16 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 MSB N – 17 D14 N – 17 D13 N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D08 N – 17 MSB N – 16 D14 N – 16 D13 N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D1A– D1A+ FCO– FCO+ D0A– D0A+ D1A– D1A+ 12737-002 BYTEWISE MODE Figure 2. 16-Bit DDR/Single Data Rate (SDR), Two-Lane, 1× Frame Mode (Default) N–1 VINx± tA N tEL tEH CLK– CLK+ DCO– tCPD DCO+ FCO– tFCO tFRAME FCO+ tPD tDATA MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB D14 D13 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 D0x+ Figure 3. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode Rev. 0 | Page 9 of 37 12737-003 D0x– AD9655 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D0x±, D1x±, DCO±, FCO±) to AGND CLK+, CLK− to AGND VINx+, VINx− to AGND SCLK/DFS, SDIO/PDWN, CSB to AGND RBIAS to AGND VREF to AGND VCM to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The exposed pad is the only ground connection for the chip. The exposed pad must be soldered to the AGND plane of the circuit board. Soldering the exposed pad to the board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 9. Thermal Resistance Package Type 32-Lead LFCSP, 5 mm × 5 mm Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 37.1 32.4 29.1 θJC1, 3 3.1 N/A5 N/A5 θJB1, 4 20.7 N/A5 N/A5 ΨJT1, 2 0.3 0.5 0.8 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 5 N/A means not applicable. 1 2 Typical θJA is specified for a 4-layer printed circuit board (PCB) with a solid ground plane. As shown in Table 9, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA. ESD CAUTION Rev. 0 | Page 10 of 37 Data Sheet AD9655 32 31 30 29 28 27 26 25 AVDD VINB– VINB+ AVDD AVDD VINA+ VINA– AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9655 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AVDD RBIAS VCM VREF CSB DRVDD D0A+ D0A– NOTES 1. THE EXPOSED PAD IS THE ONLY GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 12737-004 D0B– D0B+ DCO– DCO+ FCO– FCO+ D1A– D1A+ 9 10 11 12 13 14 15 16 AVDD CLK+ CLK– SDIO/PDWN SCLK/DFS DRVDD D1B– D1B+ Figure 4. Pin Configuration, Top View Table 10. Pin Function Descriptions Pin No. 0, Exposed Pad Mnemonic AGND, Exposed Pad 1, 24, 25, 28, 29, 32 2, 3 4 AVDD CLK+, CLK− SDIO/PDWN 5 SCLK/DFS 6, 19 7, 8 9, 10 11, 12 13, 14 15, 16 17, 18 20 21 DRVDD D1B−, D1B+ D0B−, D0B+ DCO−, DCO+ FCO−, FCO+ D1A−, D1A+ D0A−, D0A+ CSB VREF 22 VCM 23 26, 27 30, 31 RBIAS VINA−, VINA+ VINB+, VINB− Description Exposed Pad. The exposed pad is the only ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1.8 V Supply Pins for the ADC Core Domain. Differential Encode Clock. These pins are PECL-, LVDS-, or 1.8 V CMOS-compatible inputs. SPI Data Input/Output (SDIO). This pin is a bidirectional SPI data input/output with a 31 kΩ internal pull-down resistor. Non-SPI Mode Power-Down (PDWN). This pin provides static control of chip power-down, and has a 31 kΩ internal pull-down resistor. SPI Clock Input in SPI Mode (SCLK). This pin has a 30 kΩ internal pull-down resistor. Non-SPI Mode Data Format Select (DFS). This provides static control of the data output format. This pin has a 30 kΩ internal pull-down resistor. Pull DFS high for a twos complement output; pull DFS low for an offset binary output. 1.8 V Supply Pins for Output Driver Domain. Channel B Lane 1 Digital Outputs. Channel B Lane 0 Digital Outputs. Data Clock Outputs. Frame Clock Outputs. Channel A Lane 1 Digital Outputs. Channel A Lane 0 Digital Outputs. SPI Chip Select. Active low enable; this pin has a 15 kΩ internal pull-up resistor. 1.0 V to 1.4 V Voltage Reference Output. Bypass this pin to ground with a 1.0 µF capacitor in parallel with a 0.1 µF capacitor; this pin internally provides reference voltage to the ADC. This pin can be disabled via Register 0x114 if external VREF is desired. Analog Output Voltage at Mid AVDD Supply. Bypass this pin to ground with a 0.1 µF capacitor; this pin can be used to set the common mode of the analog inputs externally. Sets Analog Current Bias. Connect this pin to a 10.0 kΩ (1% tolerance) resistor to ground. Channel A ADC Analog Inputs. Channel B ADC Analog Inputs. Rev. 0 | Page 11 of 37 AD9655 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V –20 AMPLITUDE (dBFS) –40 –60 –80 –80 –120 –120 10 20 30 40 50 60 FREQUENCY (MHz) Figure 5. Single-Tone 32k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 –140 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 8. Single-Tone 32k FFT with fIN = 100.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 AIN = –1dBFS fIN = 19.7MHz SNR = 78dBFS SINAD = 76.1dBc SFDR = 85.9dBc –20 AIN = –1dBFS fIN = 139.5MHz SNR = 75.7dBFS SINAD = 74.3dBc SFDR = 85.5dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –40 –60 –80 –100 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 6. Single-Tone 32k FFT with fIN = 19.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 –140 12737-006 –140 0 20 30 40 50 60 FREQUENCY (MHz) Figure 9. Single-Tone 32k FFT with fIN = 139.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 AIN = –1dBFS fIN = 69.5MHz SNR = 77.5dBFS SINAD = 76.0dBc SFDR = 86.6dBc –20 10 12737-009 –120 AIN = –1dBFS fIN = 301MHz SNR = 71.2dBFS SINAD = 67dBc SFDR = 70.3dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 –140 12737-007 –140 Figure 7. Single-Tone 32k FFT with fIN = 69.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 10 20 30 40 FREQUENCY (MHz) 50 60 12737-010 AMPLITUDE (dBFS) –60 –100 0 AMPLITUDE (dBFS) –40 –100 –140 AIN = –1dBFS fIN = 100.5MHz SNR = 76.6dBFS SINAD = 75.5dBc SFDR = 91.1dBc –20 12737-005 AMPLITUDE (dBFS) 0 AIN = –1dBFS fIN = 9.7MHz SNR = 77.9dBFS SINAD = 76.6dBc SFDR = 89.7dBc 12737-008 0 Figure 10. Single-Tone 32k FFT with fIN = 301 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. 0 | Page 12 of 37 Data Sheet AD9655 120 100 SFDR (dBFS) 90 SFDR (dBc) 80 SNR, SFDR (dBFS and dBc) SNR (dBFS) 80 60 SFDR (dBc) 40 20 SNR (dB) SNR (dBFS) 60 50 40 30 20 0 10 –10 –30 –50 –70 0 12737-012 –20 –90 INPUT AMPLITUDE (dBFS) Figure 11. SNR, SFDR vs. Input Amplitude; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 100 300 200 INPUT FREQUENCY (MHz) 400 500 Figure 14. SNR, SFDR vs. Input Frequency (fIN); fSAMPLE = 125 MSPS, VREF = 1.0 V 95 0 AIN = –7dBFS fIN = 100.1MHz, 102.1MHz IMD2 = –89.6dBc IMD3 = –90.2dBc SFDR = 89.6dBc SFDR (dBc) 90 SNR, SFDR (dBFS and dBc) –20 AMPLITUDE (dBFS) 70 12737-015 SNR, SFDR (dB, dBc, and dBFS) 100 –40 –60 2f1 + f2 –80 2f2 – f1 f1 – f2 f1 – f 2 –100 f1 + 2f2 f1 + V2 85 80 SNR (dBFS) 75 0 10 30 20 40 60 50 FREQUENCY (MHz) 70 –40 12737-013 –140 Figure 12. Two-Tone 32k FFT with fIN1 = 100.1 MHz and fIN2 = 102.1 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 20 40 60 80 Figure 15. SNR, SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 5 4 –SFDR (dBc) 3 –40 2 IMD3 (dBc) –60 INL (LSB) SFDR, IMD3 (dBc and dBFS) 0 TEMPERATURE (°C) 0 –20 –20 12737-016 –120 –80 1 0 –1 –SFDR (dBFS) –2 –100 –3 –120 IMD3 (dBFS) –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 Figure 13. Two-Tone SFDR, IMD3 vs. Input Amplitude (AIN) with fIN1 = 100.1 MHz and fIN2 = 102.1 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. 0 | Page 13 of 37 –5 0 10000 20000 30000 40000 50000 60000 OUTPUT CODE Figure 16. INL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 12737-017 –80 –4 12737-014 –140 –90 AD9655 Data Sheet 120 0.8 SFDR (dBc) 0.6 SNR, SFDR (dBFS and dBc) 100 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 80 SNR (dBFS) 60 40 20 0 10000 20000 30000 40000 50000 0 20 12737-018 –0.8 60000 OUTPUT CODE 40 80 60 SAMPLE RATE (MSPS) 100 120 12737-021 –0.6 Figure 19. SNR, SFDR vs. Sample Rate; fIN = 9.7 MHz, VREF = 1.0 V Figure 17. DNL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 120 350k 2.7LSB rms 300k SNR, SFDR (dBFS and dBc) 100 NUMBER OF HITS 250k 200k 150k 100k SFDR (dBc) 80 SNR (dBFS) 60 40 20 N + 14 N + 12 N + 10 N+8 N+6 12737-019 OUTPUT CODE N+4 N N+2 N–2 N–4 N–6 N–8 N – 10 N – 12 N – 14 0 Figure 18. Input Referred Noise Histogram; fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. 0 | Page 14 of 37 0 20 40 80 60 SAMPLE RATE (MSPS) 100 120 Figure 20. SNR, SFDR vs. Sample Rate; fIN = 69.5 MHz, VREF = 1.0 V, Clock Divider = 4 12737-022 50k Data Sheet AD9655 VREF = 1.4 V 0 AIN = –1dBFS fIN = 9.7MHz SNR = 79.6dBFS SINAD = 78dBc SFDR = 88.1dBc AMPLITUDE (dBFS) –40 –60 –80 –80 –120 –120 10 20 30 40 50 60 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V –140 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 24. Single-Tone 32k FFT with fIN = 100.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 0 AIN = –1dBFS fIN = 19.7MHz SNR = 79.4dBFS SINAD = 77.2dBc SFDR = 85.1dBc –20 AIN = –1dBFS fIN = 139.5MHz SNR = 76.6dBFS SINAD = 74.8dBc SFDR = 82.4dBc –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –40 –60 –80 –100 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) –140 12737-024 –140 Figure 22. Single-Tone 32k FFT with fIN = 19.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 20 30 40 50 60 FREQUENCY (MHz) Figure 25. Single-Tone 32k FFT with fIN = 139.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 0 AIN = –1dBFS fIN = 69.5MHz SNR = 79.4dBFS SINAD = 76.6dBc SFDR = 83.7dBc –20 10 12737-027 –120 AIN = –1dBFS fIN = 301MHz SNR = 55dBFS SINAD = 53.8dBc SFDR = 71.6dBc –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 –140 12737-025 –140 Figure 23. Single-Tone 32k FFT with fIN = 69.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 10 20 30 40 FREQUENCY (MHz) 50 60 12737-028 AMPLITUDE (dBFS) –60 –100 0 AMPLITUDE (dBFS) –40 –100 –140 AIN = –1dBFS fIN = 100.5MHz SNR = 78dBFS SINAD = 76dBc SFDR = 83.5dBc –20 12737-023 AMPLITUDE (dBFS) –20 12737-026 0 Figure 26. Single-Tone 32k FFT with fIN = 301 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V Rev. 0 | Page 15 of 37 AD9655 Data Sheet 120 100 SFDR (dBFS) 90 SFDR (dBc) 80 SNR, SFDR (dBFS and dBc) SNR, SFDR (dB, dBc, and dBFS) 100 SNR (dBFS) 80 60 SFDR (dBc) 40 20 SNR (dB) 70 60 SNR (dBFS) 50 40 30 20 0 –70 –50 –30 0 12737-030 –20 –90 –10 INPUT AMPLITUDE (dBFS) Figure 27. SNR, SFDR vs. Input Amplitude; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 200 300 400 500 INPUT FREQUENCY(MHz) Figure 30. SNR, SFDR vs. Input Frequency (fIN); fSAMPLE = 125 MSPS, VREF = 1.4 V 95 0 AIN = –7dBFS fIN = 101.1MHz, 102.1MHz IMD2 = –88.36dBc IMD3 = –85dBc SFDR = 85dBc 90 SNR, SFDR (dBFS and dBc) –20 AMPLITUDE (dBFS) 100 12737-033 10 –40 –60 2f1 + f2 f1 + 2f2 2f2 – f1 –80 f1 + f2 2f1 – f2 f1 – f 2 –100 SFDR (dBc) 85 80 SNR (dBFS) 75 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 –40 12737-031 –140 Figure 28. Two-Tone 32k FFT with fIN1 = 100.1 MHz and fIN2 = 102.1 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 20 40 TEMPERATURE (°C) 60 80 4 3 –SFDR (dBc) 2 –40 1 –60 INL (LSB) SFDR, IMD3 (dBc and dBFS) 0 Figure 31. SNR, SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 0 –20 –20 12737-034 –120 IMD3 (dBc) –80 0 –1 –SFDR (dBFS) –100 –2 –120 –3 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 Figure 29. Two-Tone SFDR, IMD3 vs. Input Amplitude (AIN) with fIN1 = 100.1 MHz and fIN2 = 102.1 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V Rev. 0 | Page 16 of 37 –4 0 10000 20000 30000 40000 50000 60000 OUTPUT CODE Figure 32. INL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 12737-035 –140 –90 12737-032 IMD3 (dBFS) Data Sheet AD9655 120 0.8 SFDR (dBc) 0.6 SNR, SFDR (dBFS and dBc) 100 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 80 SNR (dBFS) 60 40 20 0 10000 20000 30000 40000 50000 0 20 12737-036 –0.8 60000 OUTPUT CODE 40 60 80 100 120 SAMPLE RATE (MSPS) Figure 33. DNL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V 12737-039 –0.6 Figure 35. SNR, SFDR vs. Sample Rate; fIN = 9.7 MHz, VREF = 1.4 V 450k 120 2.0LSB rms 400k 100 SNR, SFDR (dBFS and dBc) NUMBER OF HITS 350k 300k 250k 200k 150k 100k SFDR (dBc) 80 SNR (dBFS) 60 40 20 N+9 N+8 N+7 N+6 N+5 N+4 12737-037 OUTPUT CODE N+3 N+2 N N+1 N–1 N–2 N–3 N–4 N–5 N–6 N–7 N–8 N–9 N – 10 0 Figure 34. Input Referred Noise Histogram; fSAMPLE = 125 MSPS, VREF = 1.4 V Rev. 0 | Page 17 of 37 0 20 40 60 80 100 120 SAMPLE RATE (MSPS) Figure 36. SNR, SFDR vs. Sample Rate; fIN = 69.5 MHz, VREF = 1.4 V, Clock Divider = 4 12737-040 50k AD9655 Data Sheet EQUIVALENT CIRCUITS DRVDD AVDD VINx± 400Ω SCLK/DFS 12737-045 12737-041 30kΩ Figure 37. Equivalent Analog Input Circuit Figure 41. Equivalent SCLK/DFS Input Circuit AVDD 10Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 12737-046 12737-042 CLK– 400Ω RBIAS AND VCM 10Ω Figure 42. Equivalent RBIAS and VCM Circuit Figure 38. Equivalent Clock Input Circuit DRVDD DRVDD 400Ω SDIO/PDWN 15kΩ 31kΩ 12737-047 12737-043 CSB 400Ω Figure 39. Equivalent SDIO/PDWN Input Circuit Figure 43. Equivalent CSB Input Circuit DRVDD AVDD V D0x–, D1x– V V D0x+, D1x+ V VREF 10Ω 400Ω 12737-044 12737-048 7.5kΩ Figure 44. Equivalent VREF Circuit Figure 40. Equivalent Digital Output Circuit Rev. 0 | Page 18 of 37 Data Sheet AD9655 THEORY OF OPERATION Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and an interstage residue amplifier, for example, a multiplying digital-to-analog converter (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy in each stage facilitates digital correction of flash errors. The last stage consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. Then, the data is serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9655 is a differential switched capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal dependent errors and achieve optimum performance. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. A differential capacitor, two single-ended capacitors, or a combination of these capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The AD9655 analog inputs are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 46 and Figure 47. 100 SFDR (dBc) 90 SNR, SFDR (dBFS and dBc) The AD9655 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The serializer transmits this converted data in a 16-bit output. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. 80 SNR (dBFS) 70 60 50 40 30 H 10 0.5 0.6 0.8 0.7 0.9 VCM (V) CPAR H S S S 100 SFDR (dBc) CSAMPLE VINx– 90 Figure 45. Switched Capacitor Input Circuit The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 45). When the input circuit switches to sample mode, the signal source must be capable of charging the sample capacitors and settling within one half of a clock cycle. SNR, SFDR (dBFS and dBc) H 12737-049 H CPAR 1.2 Figure 46. SNR, SFDR vs. Input Common-Mode Voltage (VCM), fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V CSAMPLE S 1.1 80 SNR (dBFS) 70 60 50 40 30 20 10 0.70 0.75 0.80 0.85 VCM (V) 0.90 0.95 1.00 12737-051 VINx+ 1.0 12737-050 20 Figure 47. SNR, SFDR vs. Input Common-Mode Voltage (VCM), fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.4 V Rev. 0 | Page 19 of 37 AD9655 Data Sheet An on-chip, common-mode dc voltage reference is included in the design and is available from the VCM pin. The VCM pin must be bypassed to ground by a 0.1 µF capacitor, as described in the Applications Information section. VCM error vs. load current is shown in Figure 48. 0 Figure 52 show the typical drift characteristics of the internal reference. The internal buffer generates the positive and negative full-scale references for the ADC core. A digital reset using Register 0x08 must follow any programmatic change in internal analog VREF. 0 –2 –10 –6 VREF ERROR (%) VCM ERROR (%) –4 –8 –10 –12 –20 –30 –40 –14 –50 –16 1.5 2.0 LOAD CURRENT (mA) 2.5 INTERNAL VREF = 1V –60 0 Figure 48. VCM Error vs. Load Current 0.5 1.0 1.5 LOAD CURRENT (mA) 2.0 2.5 12737-053 1.0 2.5 12737-054 0.5 Figure 49. VREF Error vs. Load Current, VREF = 1.0 V Differential Input Configurations 0 For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 54) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9655. –10 INTERNAL VREF = 1.4V –20 VREF ERROR (%) There are several ways to drive the AD9655 either actively or passively. However, optimum performance is achieved by driving the analog inputs differentially. Using a differential double balun configuration to drive the AD9655 provides excellent performance and a flexible interface to the ADC for baseband applications (see Figure 53). –60 –70 0 0.5 1.0 1.5 LOAD CURRENT (mA) 2.0 Figure 50. VREF Error vs. Load Current, VREF = 1.4 V It is not recommended to drive the AD9655 inputs single-ended. 0.004 VOLTAGE REFERENCE 0.002 VREF ERROR (V) Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9655, the largest input span available is 2.8 V p-p, which is achieved by setting VREF to 1.4 V. –40 –50 Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. A stable and accurate 1.0 V to 1.4 V dc voltage reference is built into the AD9655. Externally bypass the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. –30 If the internal reference of the AD9655 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 49 and Figure 50 show how the internal reference voltage is affected by loading. It is recommended that VREF not be used to drive the reference voltage of other devices at 1.4 V. Figure 51 and Rev. 0 | Page 20 of 37 0 –0.002 –0.004 –0.006 INTERNAL VREF = 1V –0.008 –40 –20 0 20 40 TEMPERATURE (°C) 60 Figure 51. Typical VREF Drift, VREF = 1.0 V 80 12737-055 0 12737-052 –18 Data Sheet AD9655 0.003 0.002 0.001 VREF ERROR (V) 0 –0.001 –0.002 –0.003 –0.004 –0.005 –0.006 –20 0 20 40 60 12737-056 INTERNAL VREF = 1.4V –0.007 –40 80 TEMPERATURE (°C) Figure 52. Typical VREF Drift, VREF = 1.4 V 0.1µF 0.1µF C11 R VINx+ 33Ω C 2V p-p 33Ω C ET1-1-I3 ADC 10pF 33Ω 0.1µF R VINx– 33Ω C VCM C11 200Ω 0.1µF 1C1 C 0.1µF IS OPTIONAL Figure 53. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO R C11 VINx+ 33Ω 2V p-p 49.9Ω C R 33Ω ADC 10pF VINx– VCM C11 0.1µF 0.1μF 1C1 IS OPTIONAL 12737-058 200Ω Figure 54. Differential Transformer Coupled Configuration for Baseband Applications Rev. 0 | Page 21 of 37 12737-057 R AD9655 Data Sheet CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9655 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 38) and require no external bias. If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 57. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers, noted as AD951x in Figure 57, Figure 58, and Figure 59, offer excellent jitter performance. Clock Input Options 0.1µF The AD9655 has a flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal used, clock source jitter is an important consideration, as described in the Jitter Considerations section. CLK+ Figure 57. Differential PECL Sample Clock (Up to 1 GHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 58. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.1µF 12737-059 SCHOTTKY DIODES: HSMS2822 0.1µF 0.1µF ADC 0.1µF 0.1µF ADC 0.1µF CLK– 50kΩ 50kΩ In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 59). CLK+ CLK– SCHOTTKY DIODES: HSMS2822 12737-060 50Ω 100Ω Figure 58. Differential LVDS Sample Clock (Up to 1 GHz) Figure 55. Transformer Coupled Differential Clock (Up to 200 MHz) CLOCK INPUT AD951x LVDS DRIVER 12737-062 CLOCK INPUT CLK– 0.1µF 0.1µF CLK+ ADC 0.1µF 240Ω CLOCK INPUT CLK+ 100Ω 50Ω 240Ω 50kΩ 12737-061 50kΩ 0.1µF 0.1µF ADC 0.1µF Figure 56. Balun-Coupled Differential Clock (Up to 1 GHz) The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer configuration is recommended for clock frequencies from 20 MHz to 200 MHz. The antiparallel Schottky diodes across the transformer/balun secondary winding limit clock excursions into the AD9655 to approximately 0.8 V p-p differential. VCC 0.1µF CLOCK INPUT 50Ω1 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 1kΩ CLK+ ADC CLK– 150Ω RESISTOR IS OPTIONAL. 0.1µF 12737-063 XFMR 100Ω CLK– Mini-Circuits® ADT1-1WT, 1:1 Z 0.1µF AD951x PECL DRIVER 0.1µF CLOCK INPUT Figure 55 and Figure 56 show two preferred methods for clocking the AD9655 at clock rates up to 1 GHz prior to the internal clock divider. A low jitter clock source is converted from a single-ended signal to a differential signal using either a radio frequency (RF) transformer or an RF balun. CLOCK INPUT 0.1µF CLOCK INPUT Figure 59. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9655 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. However, the diode capacitance comes into play at frequencies above 500 MHz. Care must be taken when choosing the appropriate signal limiting diode. The AD9655 contains an input clock divider that can divide the input clock by integer values from 1 to 8. To achieve a given sample rate, the frequency of the externally applied clock must be multiplied by the divide value. The increased rate of the external clock normally results in lower clock jitter, which is beneficial for intermediate frequency (IF) undersampling applications. Rev. 0 | Page 22 of 37 Data Sheet AD9655 The AD9655 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9655. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on. Jitter in the rising edge of the clock is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The following equation shows how SNR degrades at a given input frequency (fA) due only to aperture jitter (tJ): 1 2π × f A × t J SNR Degradation = 20 log10 In this equation, the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter. The effect of jitter alone on SNR, with no other noise contributors, is shown in Figure 60. 130 RMS CLOCK JITTER REQUIREMENT 100 16 BITS 90 14 BITS 12 BITS 70 10 BITS 60 8 BITS 40 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 30 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter 12737-064 SNR (dB) 110 50 POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 61, the power dissipated by the AD9655 is proportional to its sample rate. The AD9655 is placed in powerdown mode either by the SPI port or by asserting the SDIO/ PDWN pin high when in non-SPI mode. In this state, the ADC typically dissipates 2 mW. During power-down, the output drivers are placed in a high impedance state. In non-SPI mode, asserting the SDIO/PDWN pin low returns the AD9655 to its normal operating mode. Note that SDIO/PDWN is referenced to the digital output driver supply (DRVDD) and must not exceed that supply voltage. 0.32 0.30 0.28 0.26 VREF = 1.4V 0.24 VREF = 1.0V 0.22 0.20 0.18 0.16 20 40 60 80 SAMPLE RATE (MSPS) 100 120 Figure 61. Total Power Dissipation vs. Sample Rate (fSAMPLE) for fIN = 9.7 MHz, VREF = 1.0 V and VREF = 1.4 V 120 80 See the AN-501 Application Note and the AN-756 Application Note for more information about jitter performance as it relates to ADCs. 12737-065 Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. Treat the clock input as an analog signal when aperture jitter may affect the dynamic range of the AD9655. Separate clock driver power supplies from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it is recommended that the clock be retimed by the original clock as the last step. TOTAL POWER DISSIPATION (W) Clock Duty Cycle The AD9655 achieves low power dissipation in power-down mode by shutting down the reference, reference buffer, biasing networks, and clock. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. Do not invoke standby mode while foreground calibration is in progress. Foreground calibration is invoked automatically at power-up, and by executing a digital reset with Register 0x08. Completion is indicated by the contents of Register 0x107 = 0x00. See the Memory Map section for more details on using these features. Rev. 0 | Page 23 of 37 AD9655 Data Sheet DIGITAL OUTPUTS AND TIMING When operating in reduced range mode, the output current reduces to 2 mA. This results in a 200 mV swing (or 400 mV p-p differential) across a 100 Ω termination at the receiver. The LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close as possible to the receiver. Timing errors may result if there is no far-end receiver termination, or if there is poor differential trace routing. To avoid such timing errors, ensure that the trace length is less than 24 inches and that the differential output traces are close together and at equal lengths. D0 500mV/DIV D1 500mV/DIV DCO 500mV/DIV FCO 500mV/DIV 4ns/DIV 12737-067 The AD9655 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This default setting can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default) Figure 62 shows an example of the FCO and data stream with proper trace length and position. D0 400mV/DIV D1 400mV/DIV DCO 400mV/DIV FCO 400mV/DIV 4ns/DIV 12737-068 Figure 63 shows the LVDS output timing example in reduced range mode. Figure 63. LVDS Output Timing Example in Reduced Range Mode Rev. 0 | Page 24 of 37 Data Sheet AD9655 Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches (Approximate 6 Inch Trace Length Result Shown) on Standard FR-4 Material, External 100 Ω Far-End Termination Only Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater Than 24 Inches (Approximate 36 Inch Trace Length Result Shown) on Standard FR-4 Material, External 100 Ω Far-End Termination Only Figure 65. TIE Jitter Histogram for Trace Lengths Less Than 24 Inches (Approximate 6 Inch Trace Length Result Shown) Figure 67. TIE Jitter Histogram for Trace Lengths Greater Than 24 Inches (Approximate 36 Inch Trace Length Result Shown) Figure 64 shows an example of the LVDS output data eye using the ANSI-644 standard (default), and Figure 65 shows a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on standard FR-4 material. Figure 66 shows an example of the LVDS output data eye using the ANSI-644 standard (default), and Figure 67 shows a time interval error (TIE) jitter histogram with trace lengths greater than 24 inches on standard FR-4 material. Note that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the responsibility of the user to determine if the waveforms meet the timing budget of the design. The format of the output data is twos complement by default. See Table 11 for an example of the output coding format. To change the output data format to offset binary, see the Memory Map section. Data from each ADC is serialized and provided on a separate channel in two lanes in DDR mode. The data rate for each serial stream is equal to (16 bits × the sample clock rate)/2 lanes, with a maximum of 1 Gbps/lane (16 bits × 125 MSPS)/(2 lanes) = 1 Gbps/lane). The minimum conversion rate is 20 MSPS. Two output clocks assist in capturing data from the AD9655. The DCO clocks the output data and is equal to 4× the sample clock (CLK) rate for the default mode of operation. Data is clocked out of the AD9655 and must be captured on the rising and falling edges of the DCO that supports DDR capturing. The FCO signals the start of a new output byte and is equal to the sample clock rate in 1× frame mode. See the Timing Diagrams section for more information. When the SPI is used, the DCO phase can be adjusted in approximately 60° increments relative to one data cycle (30° relative to one DCO cycle). This allows the user to refine system timing margins if required. The example DCO+ and DCO− timing, as shown in Figure 2, is 180° relative to one data cycle (90° relative to one DCO cycle). In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. This can be inverted by using the SPI so that the LSB is first in the data output serial stream. Rev. 0 | Page 25 of 37 AD9655 Data Sheet Table 11. Digital Output Coding Input (V) VINx+ − VINx− VINx+ − VINx− VINx+ − VINx− VINx+ − VINx− VINx+ − VINx− Condition (V) <−VREF − 0.5 LSB − VREF 0V + VREF − 1.0 LSB >+ VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111 Table 12. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 PN sequence long1 Digital Output Word 1 Not applicable 12-bit: 1000 0000 0000 16-bit: 1000 0000 0000 0000 12-bit: 1111 1111 1111 16-bit: 1111 1111 1111 1111 12-bit: 0000 0000 0000 16-bit: 0000 0000 0000 0000 12-bit: 1010 1010 1010 16-bit: 1010 1010 1010 1010 Not applicable 0110 PN sequence short1 0111 One-/zero-word toggle 1000 User input 1001 1-/0-bit toggle 1010 1× sync 1011 One bit high 1100 Mixed frequency 1 Digital Output Word 2 Not applicable Not applicable Subject to Data Format Select Not applicable Yes Offset binary code shown Not applicable Yes Offset binary code shown Not applicable Yes Offset binary code shown 12-bit: 0101 0101 0101 16-bit: 0101 0101 0101 0101 Not applicable No Not applicable Not applicable Yes 12-bit: 1111 1111 1111 16-bit: 111 1111 1111 1111 Register 0x19 and Register 0x1A 12-bit: 1010 1010 1010 16-bit: 1010 1010 1010 1010 12-bit: 0000 0000 1111 16-bit: 0000 0000 1111 1111 12-bit: 1000 0000 0000 16-bit: 1000 0000 0000 0000 12-bit: 1010 0001 1001 16-bit: 1010 0001 1001 1100 12-bit: 0000 0000 0000 16-bit: 0000 0000 0000 0000 Register 0x1B and Register 0x1C Not applicable No Yes Notes PN23 ITU 0.150 x23 + x18 + 1 PN9 ITU 0.150 x9 + x5 + 1 No No Not applicable No Not applicable No Not applicable No Pattern associated with the external pin All test mode options except PN sequence short and PN sequence long can support 12-bit to 16-bit word lengths to verify data capture to the receiver. Rev. 0 | Page 26 of 37 Data Sheet AD9655 There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. See Table 12 for the available output bit sequencing options. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user defined test patterns can be assigned in Register 0x19, Register 0x1A, Register 0x1B, and Register 0x1C. The pseudorandom number (PN) sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 13 for the initial values). The output is a parallel representation of the serial PN9 sequence in MSB first format. The first output word is the first 16 bits of the PN9 sequence in MSB aligned form. Table 13. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x7F83 0x7FFF Next Three Output Samples (MSB First), Twos Complement 0x5F17, 0xB209, 0xCED1 0x7E00, 0x807C, 0x801F The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 13 for the initial values) and the AD9655 inverts the bit stream in relation to the ITU standard. The output is a parallel representation of the serial PN23 sequence in MSB first format. The first output word is the first 16 bits of the PN23 sequence in MSB aligned form. See the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/PDWN Pin For applications that do not require SPI mode operation, the CSB pin is tied to DRVDD, and the SDIO/PDWN pin controls the power-down mode according to Table 14. Table 14. Power-Down Mode Pin Settings SDIO/PDWN Pin Voltage AGND (Default) DRVDD Device Mode Run device, normal operation Power down device SCLK/DFS Pin The SCLK/DFS pin is used for output format selection in applications that do not require SPI mode operation. This pin determines the digital output format when the CSB pin is held high during device power-up. When SCLK/DFS is tied to DRVDD, the ADC output format is twos complement; when SCLK/DFS is tied to AGND, the ADC output format is offset binary. Table 15. Digital Output Format SCLK/DFS Voltage AGND DRVDD Output Format Offset binary Twos complement CSB Pin Tie the CSB pin to DRVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. RBIAS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. OUTPUT TEST MODES The output test options are described in Table 12 and are controlled by the output test mode bits at Register 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For general information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 27 of 37 AD9655 Data Sheet SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of SCLK/DFS, determines the start of the framing. An example of the serial timing is shown in Figure 68. See Table 7 for definitions of the timing parameters. The AD9655 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. Information specific to the AD9655 is contained in this data sheet, and takes precedence over the the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, which provides general information. Other modes involving the CSB pin are available. CSB can be held low indefinitely, which permanently enables SPI mode; this is called streaming. CSB can stall high between bytes to allow for additional external timing. When the CSB pin is tied high at power-up, SPI functions are placed in high impedance mode. This mode turns on the secondary functions of the SPI pins. Note that, when SPI mode is entered, that is, CSB is taken low, these secondary functions cannot be invoked without power cycling the device. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/PDWN pin, and the CSB pin (see Table 16). SCLK/DFS (a serial clock when CSB is low) synchronizes the read and write data presented from and to the ADC. SDIO/PDWN (serial data input/output when CSB is low) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. CSB (chip select bar) is an active low control that enables or disables the SPI read and write cycles. During the instruction phase of an SPI operation, a 16-bit instruction is transmitted. Data follows the instruction phase, and the length of this data is determined by the W0 and W1 bits (see Figure 68). In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output SDIO/PDWN pin to change direction from an input to an output at the appropriate point in the serial frame. Table 16. Serial Port Interface Pins Pin SCLK/DFS SDIO/PDWN CSB Function Serial clock when CSB is low. The serial shift clock input, which synchronizes serial interface reads and writes. Serial data input/output when CSB is low. A dualpurpose pin that typically serves as an input or an output, depending on the instruction sent and the relative position in the timing frame. Chip select bar. An active low control that enables the SPI mode read and write cycles. tHIGH tDS tS tDH All data is composed of 8-bit words. Data can be sent in MSB first mode or in LSB first mode. MSB first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO/PDWN DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 68. Serial Port Interface Timing Diagram Rev. 0 | Page 28 of 37 D4 D3 D2 D1 D0 DON’T CARE 12737-071 SCLK/DFS DON’T CARE Data Sheet AD9655 HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 16 comprise the physical interface between the user programming device and the serial port of the AD9655. The SCLK/DFS pin and the CSB pin function as inputs when using the SPI interface. The SDIO/PDWN pin is bidirectional, functioning as an input during write phases and as an output during readback. In applications that do not interface to the SPI control registers, the SCLK/DFS pin and the SDIO/PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and power-down feature control. In this mode, connect CSB to DRVDD, which disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. It is recommended that the SPI port not be active during periods when the full dynamic performance of the converter is required. Because the SCLK/DFS signal, the CSB signal, and the SDIO/PDWN signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9655 to prevent these signals from transitioning at the converter inputs during critical sampling periods. The SCLK/DFS and SDIO/PDWN pins serve a dual function when the SPI interface is not in use. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 14 and Table 15 describe the strappable functions supported on the AD9655. SPI ACCESSIBLE FEATURES Table 17 provides a brief description of the general features accessible via the SPI. These features are described in general in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9655 device-specific features are described in detail following Table 18, the external memory map register table. Table 17. Features Accessible Using the SPI Feature Name Power Mode Clock Offset Test I/O Output Mode Output Phase ADC Resolution Rev. 0 | Page 29 of 37 Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS, set the clock divider, and set the clock divider phase Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode Allows the user to set the output clock polarity Allows power consumption scaling with respect to sample rate AD9655 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table (see Table 18) has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index register (Address 0x05); and the global ADC function registers, including setup, control, and test registers (Address 0x08 and beyond). After the AD9655 is soft reset by Register 0x00, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 18. The memory map register table lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) contains the most significant bit of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x33. This means that in Address 0x05, Bits[7:6] = 00, Bits[5:4] = 11, Bits[3:2] = 00, and Bits[1:0] = 11 (in binary). This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note documents the functions controlled by Register 0x00 to Register 0xFF. Specific register functions for the AD9655 are documented in the Memory Map Register Descriptions section. Open Locations All address and bit locations not included in Table 18 are not currently supported for this device. Write unused bits of a valid address location with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open or not listed in Table 18 (for example, Address 0x13), this address location must not be written. Logic Levels An explanation of logic level terminology is as follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Channel Specific Registers Some channel setup functions can be programmed individually for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 18 as local. These local registers and bits can be accessed by setting the appropriate data channel bits (Channel A or Channel B) and the clock channel DCO bit (Bit 5) and clock channel FCO bit (Bit 4) in Register 0x05. If all the bits are set, the subsequent write affects the registers of both channels and the DCO/FCO clock channels. In a read cycle, only set one channel (Channel A or Channel B) to read one of the two registers. If all the bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits that are designated as global in Table 18 affect the entire device and channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 30 of 37 Data Sheet AD9655 MEMORY MAP REGISTER TABLE The AD9655 uses a 3-wire interface and 16-bit addressing; therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset, where all of the user registers revert to their default values and Bit 2 is automatically cleared. Table 18. Addr. (Hex) Parameter Name Chip Configuration Registers 0x00 SPI port configuration 0x01 Chip ID (global) 0x02 Chip grade (global) Bit 7 (MSB) 0 = SDO active Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first Soft reset 1 = 16-bit address 1= 16-bit address Soft reset LSB first Bit 0 (LSB) 0 = SDO active 8-bit chip ID, Bits[7:0] 0xC2 = AD9655, dual, 16-bit, 125 MSPS, serial LVDS Open Device Index Register 0x05 Device index Speed grade ID, Bits[6:4] 110 = 125 MSPS Open Clock channel DCO Global ADC Function Registers 0x08 Power modes (global) Clock channel FCO Open 0x09 Clock (global) Open 0x0B Clock divide (global) Open 0x0C Enhancement control Open Data Channel B 0x62 Comments Nibbles are mirrored to allow a given register value to perform the same function for either MSB first or LSB first mode. Unique chip ID used to differentiate devices; read only. Unique speed grade ID used to differentiate graded devices; read only. Data Channel A 0x33 Bits are set to determine which device on chip receives the next write command. Default is all devices on chip. Power mode 00 = chip run 01 = full power-down 10 = standby 11 = digital reset Open DCS 0 = off 1 = on 0x00 Determines various generic modes of chip operation. DCS controls. Bit 2 = 1 bypasses the clock divider as well as DCS. Setting Register 0x09, Bit 2 = 1 bypasses the clock divider as well as DCS. DCS bypass 0= inactive 1= active Clock divide ratio, Bits[2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Chop Open mode 0 = off 1 = on Rev. 0 | Page 31 of 37 0x18 0xC2 Revision, Bits[3:0] Open Default Value (Hex) 0x04 0x00 0x00 Enables/ disables chop mode. AD9655 Addr. (Hex) 0x0D 0x10 Parameter Name Test mode (local except for PN sequence resets) Data Sheet Bit 7 Bit 6 (MSB) User input test mode 00 = single 01 = alternate 10 = single once 11 = alternate once (Bits[7:6] affect user input, test mode only, Bits[3:0] = 1000) Bit 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Reset PN Reset PN short Output test mode, Bits[3:0] (local) long 0000 = off (default) generator gen0001 = midscale short 0010 = positive FS erator 0011 = negative FS 0100 = alternating checkerboard 0101 = PN23 sequence 0110 = PN9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 8-bit device offset adjustment, Bits[7:0] (local); offset adjust in LSBs from −128 to +127 (twos complement format) 0 0 0 LVDSOutput Open Output ANSI/ invert format LVDS0 = offset (local) IEEE binary option 1 = twos 0 = LVDScompleANSI ment 1= (global) LVDSIEEE reduced range link (global); see Table 19 Input clock phase adjust, Bits[6:4] Output clock phase adjust, Bits[3:0] (value is number of input clock cycles (0000 through 1011); see Table 21 of phase delay); see Table 20 0x14 Offset adjust (local) Output mode 0 0x16 Output phase Open 0x18 VREF 0x19 USER_PATT1_LSB (global) B7 B6 B5 B4 0x1A USER_PATT1_MSB (global) B15 B14 B13 0x1B USER_PATT2_LSB (global) B7 B6 0x1C USER_PATT2_MSB (global) B15 B14 Open Default Value (Hex) 0x00 0x00 0x01 0x03 Internal VREF adjustment digital scaling, Bits[2:0] 000 = 1.0 V p-p (1.4 V p-p) 001 = 1.14 V p-p (1.6 V p-p) 010 = 1.33 V p-p (1.86 V p-p) 011 = 1.6 V p-p (2.24 V p-p) 100 = 2.0 V p-p (2.8 V p-p) 0x04 B3 B2 B1 B0 0x00 B12 B11 B10 B9 B8 0x00 B5 B4 B3 B2 B1 B0 0x00 B13 B12 B11 B10 B9 B8 0x00 Rev. 0 | Page 32 of 37 Comments When set, the test data is placed on the output pins in place of normal data. Device offset trim. Configures the outputs and format of the data. On devices using global clock divide, Bits[6:4] determine which phase of the divider output supplies the output clock. Internal latching is unaffected. Digitally adjusts fullscale input voltage. Does not affect analog input swing. Values shown are for VREF = 1.0 V (1.4 V). User Defined Pattern 1 (8 LSBs). User Defined Pattern 1 (8 MSBs). User Defined Pattern 2 (8 LSBs). User Defined Pattern 2 (8 MSBs). Data Sheet Addr. (Hex) 0x21 Parameter Name Serial output data control (global) 0x22 Serial channel status (local) 0x101 User Input/Output Control 2 0x102 User Input/Output Control 3 0x107 Foreground calibrations status 0x112 Clock monitor control 0x114 VREF control AD9655 Bit 7 (MSB) LVDS output 0 = MSB first (default) 1 = LSB first Bit 6 Bit 5 Bit 4 SDR/DDR one-lane/two-lane, bitwise/bytewise, Bits[6:4] 000 = SDR two-lane, bitwise 001 = SDR two-lane, bytewise 010 = DDR two-lane, bitwise 011 = DDR two-lane, bytewise (default) 100 = DDR one-lane, wordwise Open Bit 3 0 Bit 2 0 = 1× frame (default) 1 = 2× frame Bit 0 Bit 1 (LSB) Serial output number of bits 00 = 16 bits (default) 01 = 14 bits 10 = 12 bits 11 = 10 bits Channel output reset Channel powerdown 0x00 0x00 0 0 Disable SDIO pull-down 0 1 Bit 1 = 1 during foreground calibration, Bit 1 = 0 after calibration is complete 1 Bit 0 = 1 during foreground calibration, Bit 0 = 0 after calibration is complete 1 Open Open VCM powerdown Open Open 0 Recovery mode 000 = recovery off (default) 101 = recovery on Open Rev. 0 | Page 33 of 37 Default Value (Hex) 0x30 Drive VREF external 0 = no 1 = yes VREF 00 = 1.0 V 01 = 1.2 V 10 = 1.3 V 11 = 1.4 V Comments Serial stream control. 0x00 Used with Register 0x05 to power down individual sections of a converter. Disables SDIO pull-down resistor. VCM control. 0x00 Read only. 0x07 Select clock recovery mode. Bits[1:0] set the internal reference voltage. Bit 2 disables the reference if an external source is desired. 0x00 AD9655 Data Sheet MEMORY MAP REGISTER DESCRIPTIONS For general information about the functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Device Index (Register 0x05) There are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context), regardless of which channel is selected. Bits[1:0] in Register 0x05 can be used to select which individual data channel is affected by the next SPI action. The output clock channels can be selected in Register 0x05, as well. A smaller subset of the independent feature list can be applied to those devices. Refer to the following sequence of SPI writes for an example of how to use Register 0x5 to power down Channel B while keeping Channel A active: 1. 2. 3. 4. 5. SPI_Write (0x05, 0x02)—designates Channel B to be affected by the next local SPI register instruction. SPI_Write (0x22, 0x01)—powers down the Channel previously designated. SPI_Write (0x05, 0x31)—designates DCO, FCO and Channel A to be affected by future local SPI register instruction (optional). SPI_Write (0x08, 0x03)—digital reset. SPI_Write (0x08, 0x00)—takes the device back to normal operation. Power Modes (Register 0x08) Bits[7:2]—Open Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode For applications sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9655 is an available feature, enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2, where it can be filtered. Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Setting this bit selects the LVDS-IEEE (reduced range) option. The default setting is LVDS-ANSI. When LVDS-ANSI or the LVDS-IEEE reduced range link is selected, the driver current is automatically selected to give the proper output swing. Table 19. LVDS-ANSI/LVDS-IEEE Options Output Mode, Bit 6 0 1 Bits[1:0]—Power Mode In normal operation (Bits[1:0] = 00), both ADC channels are active. In power-down mode (Bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. Outputs are disabled. In standby mode (Bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. Do not invoke standby mode while foreground calibration is in progress. Foreground calibration is invoked automatically at power-up and by executing a digital reset with Register 0x08. Foreground calibration completion is indicated by the contents of Register 0x107 = 0x00. During a digital reset (Bits[1:0] = 11), a foreground calibration is invoked, all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the SPI port. Note that the SPI is always left under control of the user; that is, it is never automatically disabled or in reset (except by power-on reset). Output Mode LVDS-ANSI LVDS-IEEE reduced range link Output Driver Current Automatically selected to give proper swing Automatically selected to give proper swing Bits[5:3]—000 Bit 2—Output Invert Setting this bit inverts the output bit stream. Bit 1—Open Bit 0—Output Format By default, this bit is set to send the data output in twos complement format. Clearing this bit to 0 changes the output mode to offset binary. Rev. 0 | Page 34 of 37 Data Sheet AD9655 Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust When the clock divider (Register 0x0B) is used, the applied clock is at a higher frequency than the internal sampling clock. Bits[6:4] determine at which phase of the external clock sampling occurs. This is applicable only when the clock divider is used. Selecting a value for Bits[6:4] greater than Register 0x0B, Bits[2:0] is prohibited. See Table 20 for details. Number of Input Clock Cycles of Phase Delay 0 1 2 3 4 5 6 7 Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference. Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bits[3:0]—Output Clock Phase Adjust See Table 21 for details. Bit 6—0 (Reserved) Table 21. Output Clock Phase Adjust Options Output Clock (DCO), Phase Adjust, Bits[3:0] 0000 0001 0010 0011 (Default) 0100 0101 0110 0111 1000 1001 1010 1011 through 1111 User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0 can be set to disable the internal 31 kΩ pull-down resistor on the SDIO/PWDN pin, which limits the loading when many devices are connected to the SPI bus. Table 20. Input Clock Phase Adjust Options Input Clock Phase Adjust, Bits[6:4] 000 (Default) 001 010 011 100 101 110 111 available in the AD9655. Note that, in single data rate (SDR) mode, the DCO frequency is double that of the frequency in DDR mode for a given sample rate. In SDR mode, to stay within the capability of the DCO LVDS driver, the ADC sample rate must be reduced to ≤62.5 MSPS to keep the DCO frequency at ≤500 MHz. DCO Phase Adjustment (Approximate Degrees Relative to the D0x±/D1x± Edge) 0 60 120 180 240 300 360 420 480 540 600 660 Bits[5:3]—Recovery Mode By default (Bits[5:3] = 000), recovery mode is off. In this condition, the AD9655 does not automatically recover from a state change or corruption due to a clock glitch or irregularity. With recovery mode off, a digital reset (Register 0x08 = 0x03, then Register 0x08 = 0x00) is needed to restore the AD9655 to proper operation in case of disruption due to clock instability. With clock recovery mode on (Bits[5:3] = 101), AD9655 automatically recovers from corruption due to a clock glitch or irregularity. After the corruption is autodetected, 31 × 106 clock cycles are needed to restore proper operation. Bits[2:0]— Recovery Mode Setup Recovery mode is set up for correct operation by default (Bits[2:0] = 111). VREF Control (Register 0x114) Serial Output Data Control (Register 0x21) The serial output data control register to programs the AD9655 in various output data modes, depending on the data capture solution. Table 22 describes the various serialization options This register adjusts the internal analog VREF value. A digital reset using Register 0x08 must follow any change in analog VREF. Table 22. SPI Register 0x21 Options Register 0x21 Contents 0x30 0x20 0x10 0x00 0x40 Serialization Options Selected Serial Output Number of Bits (SONB) Frame Mode Serial Data Mode 16-bit 1× DDR two-lane bytewise 16-bit 1× DDR two-lane bitwise 16-bit 1× SDR two-lane bytewise 16-bit 1× SDR two-lane bitwise 16-bit 1× DDR one-lane wordwise Rev. 0 | Page 35 of 37 DCO Multiplier 4 × fS 4 × fS 8 × fS 8 × fS 8 × fS Timing Diagram See Figure 2 (default setting) See Figure 2 See Figure 2 See Figure 2 See Figure 3 AD9655 Data Sheet APPLICATIONS INFORMATION Before starting design and layout of the AD9655 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements needed for certain pins. POWER AND GROUND GUIDELINES When connecting power to the AD9655, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, use several different bypass capacitor values to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the device, with minimal trace length. A single PCB ground plane is sufficient when using the AD9655. With proper bypassing and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. CLOCK STABILITY CONSIDERATIONS When powered on, the AD9655 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. During the initialization process, the AD9655 needs a stable clock. If the ADC clock source is not present or not stable during ADC power-up, it disrupts the state machine and causes the ADC to start up in an unknown state. To correct this, reinvoke an initialization sequence after the ADC clock is stable by issuing a digital reset via Register 0x08. In the default configuration (internal VREF, accoupled input) where VREF and VCM are supplied by the ADC, a stable clock during power-up is sufficient. WhenVCM is supplied by an external source, this, too, must be stable at power-up; otherwise, a subsequent digital reset via Register 0x08 is needed. Clock instability during normal operation may also necessitate digital reset to restore proper operation. The pseudo code sequence for a digital reset is as follows: 1. 2. SPI_Write (0x08, 0x03)—digital reset. SPI_Write (0x08, 0x00)—normal operation. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9655. It is recommended that an exposed continuous copper plane on the PCB mate to the AD9655 exposed pad, Pin 0. It is also recommended that this copper plane have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Solder-fill or plug these vias. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen or solder mask on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 69 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). SILKSCREEN PARTITION PIN 1 INDICATOR 12737-072 DESIGN GUIDELINES Figure 69. Typical PCB Layout VCM Bypass the VCM pin to ground with a 0.1 μF capacitor. REFERENCE BYPASSING Externally bypass the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI PORT The SPI port must not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9655 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 36 of 37 Data Sheet AD9655 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 EXPOSED PAD 3.60 SQ 3.55 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 70. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9655BCPZ-125 AD9655BCPZRL7-125 AD9655-125EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) Evaluation Board Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12737-0-1/15(0) Rev. 0 | Page 37 of 37 Package Option CP-32-12 CP-32-12