Eight Character 5 mm and 7 mm Smart Alphanumeric Displays Technical Data HDSP-210X Series HDSP-211X Series HDSP-250X Series Features • X Stackable (HDSP-21XX) • XY Stackable (HDSP-250X) • 128 Character ASCII Decoder • Programmable Functions • 16 User Definable Characters • Multi-Level Dimming and Blanking • TTL Compatible CMOS IC • Wave Solderable Applications • Computer Peripherals • Industrial Instrumentation • Medical Equipment • Portable Data Entry Devices • Cellular Phones • Telecommunications Equipment • Test Equipment Description The HDSP-210X/-211X/-250X series of products is ideal for applications where displaying eight or more characters of dot matrix information in an aesthetically pleasing manner is required. These devices are 8-digit, 5 x 7 dot matrix, alphanumeric displays and are all packaged in a standard 15.24 mm (0.6 inch) 28 pin DIP. The onboard CMOS IC has the ability to decode 128 ASCII characters which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in on-board ROM, allowing consider- able flexibility for displaying additional symbols and icons. Seven brightness levels provide versatility in adjusting the display intensity and power consumption. The HDSP-210X/-211X/-250X products are designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional 8-bit data bus. Device Selection Guide Font Height 0.2 inches AlGaAs Red HDSP-2107 High Efficiency Red HDSP-2112 Orange HDSP-2110 Yellow HDSP-2111 Green HDSP-2113 0.27 inches HDSP-2504 HDSP-2502 HDSP-2500 HDSP-2501 HDSP-2503 2 Package Dimensions Absolute Maximum Ratings Supply Voltage, VDD to Ground[1] ........................................ -0.3 to 7.0 V Operating Voltage, VDD to Ground[2] .............................................. 5.5 V Input Voltage, Any Pin to Ground .............................. -0.3 to VDD +0.3 V Free Air Operating Temperature Range, TA[3] ................ -45°C to +85°C Storage Temperature Range, TS .................................. -55°C to +100°C Relative Humidity (non-condensing) ............................................... 85% Maximum Solder Temperature (Below Seating Plane), t < 5 sec .............................................. 260°C ESD Protection @ 1.5 kΩ, 100 pF ........................ VZ = 4 kV (each pin) Notes: 1. Maximum Voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness. 3. Maximum supply voltage is 5.25 V for operation above 70°C. ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID STATIC DISCHARGE. 3 Package Dimensions 4 ASCII Character Set HDSP-210X, HDSP-211X, HDSP-250X Series Recommended Operating Conditions Parameter Supply Voltage Symbol Minimum Nominal Maximum Units VDD 4.5 5.0 5.5 V 5 Electrical Characteristics Over Operating Temperature Range (-45°C to +85°C) 4.5 V < VDD < 5.5 V, unless otherwise specified Parameter Symbol TA = 25°C VDD = 5.0 V Typ. Max. -45°C < TA < + 85°C 4.5 V < VDD < 5.5 V Min. Max. Units Test Conditions 1.0 -1.0 µA VIN = 0 to VDD, pins CLK, D0-D7, A0-A4 Input Leakage (Input without pullup) IIH IIL Input Current (Input with pullup) IIPL -11 -18 -30 µA VIN = 0 to VDD, pins CLS, RST, WR, RD, CE, FL IDD (BLK) 0.5 3.0 4.0 mA VIN = VDD IDD 8 digits 12 dots/character[1,2] IDD(V) 200 255 330 mA “V” on in all 8 locations IDD 8 digits 20 dots/character[1,2,3, 4] IDD(#) 300 370 430 mA “#” on in all locations IDD Blank Input Voltage High VIH 2.0 VDD +0.3 V Input Voltage Low VIL GND -0.3 V 0.8 V Output Voltage High VOH 2.4 Output Voltage Low D0-D7 VOL Output Voltage Low CLK V VDD = 4.5 V, IOH = -40 µA 0.4 V VDD = 4.5 V, IOL = 1.6 mA VOL 0.4 V VDD = 4.5 V, IOL = 40 µA High Level Output Current IOH -60 mA VDD = 5.0 V Low Level Output Current IOL 50 mA VDD = 5.0 V Thermal Resistance IC Junction-to-Case Rθ J-C 15 °C/W Notes: 1. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x IDD (#). 2. Maximum IDD occurs at -55°C. 3. Maximum IDD(#) = 355 mA at VDD = 5.25 V and IC TJ = 150°C. 4. Maximum IDD(#) = 375 mA at VDD = 5.5 V and IC TJ = 150°C. 6 Optical Characteristics at 25°C[1] VDD = 5.0 V at Full Brightness Description AlGaAs HER Orange Yellow High Performance Green Part Number HDSP-2107 -2504 HDSP-2112 -2502 HDSP-2110 -2500 HDSP-2111 -2501 HDSP-2113 -2503 Luminous Intensity Character Average (#) Iv (mcd) Min. Typ. 5.0 15.0 Peak Wavelength λPeak (nm) 645 Dominant Wavelength λd (nm) 637 2.5 7.5 635 626 2.5 7.5 600 602 2.5 7.5 583 585 2.5 7.5 568 574 Note: 1. Refers to the initial case temperature of the device immediately prior to measurement. AC Timing Characteristics Over Temperature Range (-45°C to +85 °C) 4.5 V < VDD < 5.5 V, unless otherwise specified Reference Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol tACC tACS tCE tACH tCER tCES tCEH tW tWSU tWH tR tRD tDF tRC Description Display Access Time Write Read Address Setup Time to Chip Enable Chip Enable Active Time[2,3] Write Read Address Hold Time to Chip Enable Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge of [2,3] Write Read Chip Enable Hold Time to Rising Edge of Read/Write Signal[2,3] Write Active Time Data Write Setup Time Data Write Hold Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time[4] Min.[1] Units 210 230 10 ns ns 140 160 20 60 ns ns ns 140 160 ns 0 100 50 20 160 75 10 300 ns ns ns ns ns ns ns ns Notes: 1. Worst case values occur at an IC junction temperature of 150° C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line. 7 AC Timing Characteristics Over Temperature Range (-45°C to +85°C) 4.5 V < VDD < 5.5 V, unless otherwise specified Symbol Description 25°C Typ. Min.[1] Units FOSC Oscillator Frequency 57 28 kHz FRF[2] Display Refresh Rate 256 128 Hz FFL[3] Character Flash Rate 2 1 Hz tST[4] Self Test Cycle Time 4.6 9.2 sec Notes: 1. Worst case values occur at an IC junction temperature of 150°C. 2. F = F /224 RF OSC 3. FFL = FOSC /28,672 4. tST = 262,144/FOSC Write Cycle Timing Diagram 8 Read Cycle Timing Diagram Relative Luminous Intensity vs. Temperature HER HDSP-2112/2502 YELLOW HDSP-2111/2501 HDSP-2113/2503 9 Electrical Description Pin Function Description RESET (RST, pin 1) Initializes the display. FLASH (FL, pin 2) FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. ADDRESS INPUTS (A0-A4, pins 3-6, 10) Each location in memory has a distinct address. Address inputs (A0-A2) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A3-A4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory Section of Memory FL A4 A3 A2 A1 A0 Flash RAM 0 X X Char. Address UDC Address Register 1 0 0 Don't Care UDC RAM 1 0 1 Row Address Control Word Register 1 1 0 Don’t Care Character RAM 1 1 1 Character Address CLOCK SELECT (CLS, pin 11) Used to select either an internal (CLS = 1) or external (CLS = 0) clock source. CLOCK INPUT/OUTPUT (CLK, pin 12) Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. WRITE (WR, pin 13) Data is written into the display when the WR input is low and the CE input is low. CHIP ENABLE (CE, pin 17) Must be at a logic low to read or write data to the display and must go high between each read and write cycle. READ (RD, pin 18) Data is read from the display when the RD input is low and the CE input is low. DATA Bus (D0-D7, pins 19, 20, 23-28) Used to read from or write to the display. GND (SUPPLY) (pin 15) Analog ground for the LED drivers. GND (LOGIC) (pin 16) Digital ground for internal logic. VDD (POWER) (pin 14) Positive power supply input. Figure 1. HDSP-210X/-211X/-212X/-250X Internal Block Diagram. 10 11 Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP-210X/ -211X/-250X displays. The CMOS IC consists of an 8 byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register, and refresh circuitry necessary to synchronize the decoding and driving of eight 5 x 7 dot matrix characters. The major user-accessible portions of the display are listed below: Character RAM This RAM stores either ASCII character data or a UDC RAM address. Flash RAM This is a 1 x 8 RAM which stores Flash data. User-Defined Character RAM (UDC RAM) This RAM stores the dot pattern for custom characters. User-Defined Character Address Register (UDC Address Register) This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. Control Word Register This register allows the user to adjust the display brightness, flash individual characters, blink, self test, or clear the display. Character Ram Figure 2 shows the logic levels needed to access the HDSP-210X/-211X/-250X Character RAM. During a normal access, the CE = “0” and either RD = “0” or WR = “0.” However, erroneous data may be written into the Character RAM if the address lines are unstable when CE = “0” regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between the ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0-D6 are used to input ASCII data and D0-D3 are used to input a UDC address. Figure 2. Logic Levels to Access the Character RAM. 12 UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0-D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character, eight write cycles are required. One cycle is used to store the UDC RAM address in the UDC Address Register and seven cycles are used to store dot data in the UDC RAM. Data is entered by rows and one cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an “F.” A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM while address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attribute. D0 is used to store or remove the flash attribute. D0 = “1” stores the attribute and D0 = “0” removes the attribute. Figure 3. Logic Levels to Access a UDC Character. C C O O L L 1 2 D4 D3 1 1 1 0 1 0 1 1 1 0 1 0 1 0 IGNORED C O L 3 D2 1 0 0 1 0 0 0 C O L 4 D1 1 0 0 1 0 0 0 C O L 5 D0 1 0 0 0 0 0 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 UDC CHARACTER * * * * * * * * * * * * * * HEX CODE 1F 10 10 1D 10 10 10 0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED. Figure 4. Data to Load ""F'' into the UDC RAM. When the attribute is enabled through bit 3 of the Control Word and a “1” is stored in the Flash RAM, the corresponding character will flash at approxi- mately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672. 13 Figure 5. Logic Levels to Access the Flash RAM. Control Word Register Figure 6 shows how to access the Control Word Register. This 8-bit register performs five functions: Brightness control, Flash RAM control, Blinking, Self Test, and Clear. Each function is independent of the others; however, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent brightness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a“1,” the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a “1,” the associated digit will flash at Figure 6. Logic Levels to Access the Control Word Register Table 2. Current Requirements at Different Brightness Levels VDD = 5.0 V Symbol IDD (V) D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 % D0 Brightness 0 100 1 80 0 53 1 40 0 27 1 20 0 13 approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a “0,” the content of the Flash RAM is ignored. To use this function with multiple display systems, see the Display Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all Current at 25°C Typ. 200 160 106 80 54 40 26 Units mA mA mA mA mA mA mA eight digits of the display. When this bit is a “1” all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems, see the Display Reset section. 14 Self Test Function (Bits 5, 6) Bit 6 of the Control Word Register is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = “1” indicates a passed self test and bit 5 = “0” indicates a failed self test. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal routines which exercise major portions of the IC and illuminate all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to “1.” The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, the Flash RAM is cleared, and the UDC Address Register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a “1” will start the clear function. Three clock cycles (110 ms minimum using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a “0.” The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with “0”s. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected. Display Reset Figure 7 shows the logic levels needed to Reset the display. The display should be Reset on Power-up. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 µs minimum using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a Figure 7. Logic Levels to Reset the Display. space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all “0”s. The UDC RAM and UDC Address Register are unaffected. All displays which operate with the same clock source must be simultaneously reset to synchronize the Flashing and Blinking functions. Mechanical and Electrical Considerations The HDSP-210X/-211X/-250X are 28 pin dual-in-line packages with 26 external pins. The devices can be stacked horizontally and vertically to create arrays of any size. The HDSP-210X/-211X/-250X are designed to operate continuously from -45°C to +85°C with a maximum of 20 dots on per character at 5.25 V. Illuminating all thirty-five dots at full brightness is not recommended. The HDSP-210X/-211X/-250X are assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a thermally conductive printed circuit board. A polycarbonate lens is placed over the PC board creating an air gap over the LED wire bonds. A protective cap creates an air gap over the CMOS IC. Backfill epoxy environmentally seals the display package. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering. The inputs to the IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be 15 used. Prior to use, the HDSP210X/-211X/-250X should be stored in antistatic tubes or in conductive material. During assembly, a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VDD (VIN > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Thermal Considerations The HDSP-210X/-211X/-212X/ 250X have been designed to provide a low thermal resistance path for the CMOS IC to the 26 package pins. Heat is typically conducted through the traces of the printed circuit board to free air. For most applications no additional heatsinking is required. Measurements were made on a 32 character display string to determine the thermal resistance of the display assembly. Several display boards were constructed using 0.062 in. thick printed circuit material, and one ounce copper 0.020 in. traces. Some of the device pins were connected to a heatsink formed by etching a copper area on the printed circuit board surrounding the display. A maximally metallized printed circuit board was also evaluated. The junction temperature was measured for displays soldered directly to these PC boards, displays installed in sockets, and finally displays installed in sockets with a filter over the display to restrict airflow. The results of these thermal resistance measurements, RθJ-A are shown in Table 3 and include the effects of RθJ-C. Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnections between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltage below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch. Soldering and Post Solder Cleaning Instructions for the HDSP-210X/-211X/ -250X The HDSP-210X/-211X/-250X may be hand soldered or wave soldered with SN63 solder. When hand soldering, it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315°C (600°F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245°C ± 5°C (473°F ± 9°F), and the dwell in the wave should be set between 11 /2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 105°C (221°F) as measured on the solder side of the PC board. Table 3. Thermal Resistance, θJA, Using Various Amounts of Heatsinking Material Heatsinking Metal per Device sq. in. W/Sockets W/O Sockets W/O Filter W/O Filter (Avg.) (Avg.) W/Sockets W/Filter (Avg.) Units 0 1 3 Max. Metal 31 31 30 29 30 28 26 25 35 33 33 32 °C/W °C/W °C/W °C/W 4 Board Avg 30 27 33 °C/W For additional information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components. Contrast Enhancement The objective of contrast enhancement is to provide good readability in a variety of ambient lighting conditions. For information on contrast enhancement see Application Note 1015, Contrast Enhancement Techniques for LED Displays. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. Obsoletes 5964-6378E 5968-7907E (11/99)