IRF IRS20954STRPBF Protected digital audio driver Datasheet

Data Sheet No. PD60276
IRS20954S
Protected Digital Audio Driver
Features
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Product Summary
Floating PWM input enables easy half bridge
implementation
Integrated programmable bi-directional over-current
protection with self-reset function
Programmable compensated preset deadtime for
improved THD performances
High noise immunity
±100 V high voltage ratings deliver up to 500 W output
power
3.3 V / 5 V logic compatible input
Operates up to 800 kHz
RoHS compliant
± 100 V
VOFFSET (max)
Gate driver
Io+
1.0 A
Io -
1.2 A
Propagation delay
15 ns, 25 ns,
35 ns, 45 ns
90 ns
OC protection delay
1 µs (max)
Selectable Deadtime
Package
Description
The IRS20954 is a high voltage, high speed MOSFET driver
with floating PWM input, specially designed for Class D audio
amplifier applications. The bi-directional current sensing
requires no external shunt resistors. It can capture over-current
conditions at either positive or negative load current direction. A
built-in control block provides secure protection sequence
against over-current conditions, including a programmable reset
timer.
The internal deadtime generation block provides
accurate gate switch timing and enables optimum deadtime
settings for better audio performances, such as THD and audio
noise floor.
16-Lead SOIC (narrow body)
Typical Connection
IRS 20954 S
PWM
VDD
CSH
CSD
VB
IN
HO
VSS
VS
NC
NC
VREF
(Please refer to Lead
Assignments for correct
pin configuration. This
diagram shows
electrical connections
only)
OCSET
DT
+B
Speaker
VCC
LO
COM
Vcc
12 V
-B
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IRS20954S
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSS; all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
VB
High-side floating supply voltage
Min.
Max.
-0.3
220
VS
High-side floating supply voltage (Note 1)
VB-20
VB+0.3
VHO
High-side floating output voltage
Vs-0.3
VB+0.3
VCSH
CSH pin input voltage
Vs-0.3
VB+0.3
VCC
Low-side fixed supply voltage (Note 1)
-0.3
20
VLO
Low-side output voltage
-0.3
VCC +0.3
VDD
Floating input supply voltage
VSS
Floating input supply voltage (Note 1)
-0.3
210
(see IDDZ)
VDD+0.3
VIN
PWM input voltage
VSS -0.3
VDD+0.3
VCSD
CSD pin input voltage
VSS -0.3
VDD+0.3
VDT
DT pin input voltage
-0.3
VCC +0.3
VOCSET
OCSET pin input voltage
-0.3
VCC +0.3
VREF
VREF pin voltage
-0.3
VCC +0.3
IDDZ
Floating input supply zener clamp current (Note 1)
-
10
ICCZ
Low-side supply zener clamp current (Note 1)
-
10
IBSZ
Floating supply zener clamp current (Note 1)
-
10
IOREF
Units
V
mA
Reference output current
-
5
d VS /dt
Allowable VS voltage slew rate
-
50
d VSS /dt
Allowable VSS voltage slew rate (Note 2)
-
50
d VSS /dt
Allowable VSS voltage slew rate upon power-up (Note 3)
-
50
V/ms
Maximum power dissipation
-
1.0
W
°C/W
PD
Rth,JA
Thermal resistance, junction to ambient
-
115
TJ
Junction temperature
-
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
-
300
V/ns
°C
Note1: VDD - VSS, VCC -COM and VB - VS contain internal shunt zener diodes. Please note that the voltage
ratings of these can be limited by the clamping current.
Note2: For the rising and falling edges of step signal of 10 V; Vss=15 V to 200 V.
Note3: Vss ramps up from 0 V to 200 V.
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IRS20954S
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset
ratings are tested with supplies biased at IDD=5 mA, VCC=12 V, and VB-VS=12 V.
Symbol
Definition
Min.
Max.
Units
Vs+10
Note 1
Vs+18
100
V
mA
VB
VS
High-side floating supply absolute voltage
High-side floating supply offset voltage
IDDZ
Floating input supply Zener clamp current
1
5
VSS
Floating input supply absolute voltage
0
200
VHO
High-side floating output voltage
VS
VB
VCC
Low-side fixed supply voltage
10
18
VLO
Low-side output voltage
0
VCC
VIN
V
PWM input voltage
VSS
VDD
VCSD
CSD pin input voltage
VSS
VDD
VDT
DT pin input voltage
0
VCC
IOREF
Reference output current to COM (Note 2)
0.3
0.8
mA
OCSET pin input voltage
0.5
5
V
VOCSET
TA
Ambient temperature
-40
125
°C
Note 1: Logic operational for Vs equal to –5 V to +200 V. Logic state held for Vs equal to –5 V to –VBS.
Note 2: Nominal voltage for VREF is 5 V. IOREF of 0.3 mA to 0.8 mA dictates total external resistor value on VREF to be 6.3 kΩ
to 16.7 kΩ.
Electrical Characteristics
VCC, VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V, CL=1 nF, and TA=25 °C unless otherwise specified.
Symbol
Definition
Low-side Supply
UVCC+
VCC supply UVLO positive threshold
UVCCVCC supply UVLO negative threshold
IQCC
Low-side quiescent current
VCLAMPL
Low-side Zener diode clamp voltage
High-side Floating Supply
High-side well UVLO positive
UVBS+
threshold
High-side well UVLO negative
UVBSthreshold
IQBS
High-side quiescent current
ILKH
High-side to low-side leakage current
VCLAMPH High-side Zener diode clamp voltage
Floating Input Supply
VDD, VSS floating supply UVLO
UVDD+
positive threshold
VDD, VSS floating supply UVLO
UVDDnegative threshold
IQDD
Floating input quiescent current
Floating input Zener diode clamp
VCLAMPM
voltage
Floating input side to low-side leakage
ILKM
current
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Min.
Typ.
Max.
8.4
8.2
19.8
8.9
8.7
20.8
9.4
9.2
3
21.8
8.0
8.5
9.0
7.8
8.3
8.8
Units
Test Conditions
V
mA
V
VDT = VCC
ICC=2 mA
V
-
-
1
-
mA
50
V
VB=VS =200 V
IBS=2 mA
V
VSS =0 V
1
mA
VDD=9.5 V +Vss
10.4
10.9
V
IDD=2 mA
-
50
µA
VDD=VSS =200 V
19.8
20.8
21.8
8.2
8.7
9.2
7.7
8.2
8.7
-
-
9.9
-
µA
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IRS20954S
Electrical Characteristics (cont.)
Definition
Symbol
Floating PWM Input
VIH
Logic high input threshold voltage
VIL
Logic low input threshold voltage
IIN+
Logic “1” input bias current
IINLogic “0” input bias current
Protection
VREF
Reference output voltage
Vth,OCL
Low-side OC threshold in Vs
Vth,OCH
High-side OC threshold in VCSH
Vth,1
Vth,2
ICSD+
ICSD-
CSD pin shutdown release threshold
CSD pin self reset threshold
CSD pin discharge current
CSD pin charge current
Shutdown propagation delay from
tSD
VCSD > VSS + VthOCH to shutdown
Propagation delay time from VCSH >
tOCH
VthOCH to shutdown
Propagation delay time from Vs>
tOCL
VthOCL to shutdown
Gate Driver (Fig.5)
Output high short circuit current
Io+
(source)
IoOutput low short circuit current (sink)
Low level output voltage
VOL
LO – COM, HO - VS
High level output voltage
VOH
VCC – LO, VB - HO
tr
Turn-on rise time
tf
Turn-off fall time
High- and low-side turn-on propagation
ton_1
delay, floating inputs
High- and low-side turn-off propagation
toff_1
delay, floating inputs
High- and low-side turn-on propagation
ton_2
delay, non-floating inputs
High- and low-side turn-off propagation
toff_2
delay, non-floating inputs
Deadtime: LO turn-off to HO turn-on
DT1
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
DT2
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
DT3
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
DT4
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)VDT= VDT4
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Min.
Typ.
Max.
2.3
-
-
1.5
40
5
4.6
5.1
5.6
1.0
1.2
1.4
1.0+ Vs
1.2+ Vs
1.4+ Vs
Units
Test Conditions
V
µA
V
VIN =3.3 V
VIN = VSS
IOREF =0.5 mA
OCSET=1.2 V,
Fig. 13
Vs=200 V,
Fig. 14
0.62 x VDD
0.26 x VDD
50
50
0.70 x VDD
0.30 x VDD
100
100
0.78 x VDD
0.34 x VDD
150
150
-
-
1
-
-
1
-
-
1
0.8
1.0
-
1.0
1.2
-
-
-
0.1
-
-
1.4
-
15
10
-
-
105
-
-
90
-
-
105
-
-
90
-
8
15
22
15
25
35
VDT1>VDT> VDT2,
VSS = COM
20
35
50
VDT2>VDT> VDT3,
VSS = COM
25
45
60
VDT3>VDT> VDT4,
VSS = COM
VSS =0 V
µA
VSD = VSS +5 V
Fig. 2
µs
Fig. 3
Fig. 4
A
Vo=0 V, PW<10 µs
Vo=12 V, PW<10 µs
V
Io=0 A
VDT = VCC,
VS = 100 V,
VSS = COM
ns
VDT>VDT1,
VSS = COM
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IRS20954S
Electrical Characteristics (cont.)
Definition
Symbol
VDT1
VDT2
VDT3
DT mode select threshold 2
DT mode select threshold 3
DT mode select threshold 4
Min.
Typ.
Max.
Units
0.51·(Vcc)
0.32·(V cc)
0.21·(V cc)
0.57·(V cc)
0.36·(V cc)
0.23·(V cc)
0.63·(V cc)
0.40·(V cc)
0.25·(Vv
V
Test Conditions
Lead Definitions
Pin #
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
CSD
IN
VSS
NC
VREF
OCSET
DT
COM
LO
VCC
NC
VS
HO
VB
CSH
Description
Floating input positive supply
Shutdown timing capacitor, referenced to VSS
PWM non-inverting input, in phase with HO
Floating input supply return
5 V reference output for setting OCSET
Low-side over-current threshold setting, referenced to COM
Input for programmable deadtime, referenced to COM
Low-side supply return
Low-side output
Low-side logic supply
High-side floating supply return
High-side output
High-side floating supply
High-side over-current sensing input, referenced to VS
VDD
1
16
CSH
CSD
2
15
VB
IN
3
14
HO
VSS
4
13
VS
NC
5
12
NC
VREF
6
11
VCC
OCSET
7
10
LO
8
9
COM
DT
20954
IRS20954 16 Lead SOIC (narrow body)
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IRS20954S
Block Diagram
FLOATING INPUT
UV
DETECT
VDD
VB
UV
HIGH
SIDE
CS
INPUT
LOGIC
Q
HO
20.8V
IN
CSH
UV
DETECT
10.4V
HV
LEVEL
SHIFT
VSS
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
VS
HV
LEVEL
SHIFT
VCC
5V REG
UV
DETECT
CHARGE/
DISCHARGE
CSD
SD
PROTECTION
CONTROL
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
DT
20.8V
DEAD-TIME
LO
COM
LOW SIDE CS
5.1V REFERENCE
OCSET
VREF
DT
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IRS20954S
Figure 1: Switching Time Waveform Definitions
Vth1
CSD
90%
HO/LO
tSD
Figure 2: CSD to Shutdown Waveform Definitions
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IRS20954S
Vth1
CSD
90%
HO/LO
tSD
Figure 3: CSH to Shutdown Waveform Definitions
VS
VTHCSL
90%
LO
tOCL
Figure 4: Vs > VTH,SCL to Shutdown Waveform Definitions
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IRS20954S
Functional Description
Floating PWM Input
The IRS20954 has a floating input interface which enables easy half bridge implementation. Three pins, VDD, CSD
and IN, are referenced to VSS. As a result, the PWM input signal can be directly fed into IN referencing ground, which
is typically middle point of DC bus in a half bridge configuration.
The IRS20954 also has a non-floating input with VSS tied to COM.
VDD
HV
LEVEL
SHIFT
CSD
10.4V
IN
PROTECTION
VSS
Floating Input Isolation
Floating Bias
0V – 200V
COM
IRS20954
Figure 5: Floating PWM Input Structure
Over-Current Protection (OCP)
The IRS20954 features over-current protection to protect the power MOSFET from over load conditions. The IRS20954 enters
shutdown mode when it detects over-current condition either from low side or high side current sensing. The timing control
block measures resume timing interval with an external timing capacitor Ct. All the critical timing of the over-current protection is
specified and guaranteed for secure protection.
The sequence on the over-current detection is:
1.
2.
3.
4.
5.
6.
As soon as either high or low side current sensing block detects over-current condition, the OC Latch (OCL) flips and
shutdowns the outputs LO and HO.
The CSD pin starts discharging the external capacitor Ct.
When VSCD crosses the lower threshold Vth2, the output signal from the COMP2 resets the OCL.
The CSD pin starts charging the external capacitor Ct.
When VSCD crosses the upper threshold Vth1, the COMP1 flips and enables shutdown signal released.
If one of current sensing block detects over-current condition, the sequence is repeated until the cause of over-current
goes away.
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IRS20954S
VAA
VCSD
Vth1
Vth2
VSS
t OCL / t OCH
OC detection
Charge
CSD Capacitor
Discharge
Shutdown
SD
Release
Normal operation
Power on mute
Protection
reset interval
Normal operation
Figure 6: Over-Current Protection Timing Chart
Protection Control
The internal protection control block manages operational mode between shutdown and normal, with a help from CSD pin.
Shutdown mode forces LO and HO to output 0 V to the COM and VS respectively to turn the power MOSFET off.
The external capacitor pin, CSD, provides five functions.
1. Power up delay timer for self reset configuration
2. Self-reset configuration
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
VDD
Vth1
`
COMP1
CSD
OC
S
Q
UVLO(VB)
`
COMP2
Ct
R
OC DET (H)
Vth2
VSS
HV
LEVEL
SHIFT
FLOATING INPUT
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
LOW SIDE
OC DET (L)
UVLO(VCC)
SD
PWM
HO
DEAD TIME
`
LO
Figure 7: Shutdown Functional Block Diagram
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IRS20954S
Self Reset Protection
By simply putting a capacitor between the CSD and VSS, the OCP in the IRS20954 acts as a self.
VDD
Ct
CSH
CSD
VB
IN
HO
VSS
VS
NC
NC
VREF
OCSET
DT
VCC
LO
COM
Figure 8: Self-Reset Protection Configuration
Designing Ct
Timing capacitor Ct programs the protection resume interval timing tPR given as:
t PR = 1.1⋅
Ct ⋅VDD
I CSD
[sec]
or
Ct =
t PR ⋅ I CSD
1.1 ⋅ VDD
[F]
For example, tPR is 1.2 s with a 10 µF capacitor for VDD=10.8 V. The start-up time tSU, from power-up to
shutdown release, is given as:
t SU = 0.7 ⋅
Ct ⋅ VDD
I CSD
[sec]
or
Ct =
t SU ⋅ I CSD
0.7 ⋅ VDD
[F]
where ICSD is charge/discharge current in CSD pin, 100 µA.
VDD is supply voltage respect to VSS.
Protection-resume timing tPR should be long enough to avoid over heating and failure of the MOSFET from
the repetitive sequences of shutdown and resume when the load is in continuous short circuit. In most of
applications, the minimum recommended protection-resume timing tPR is 0.1 s.
Shutdown Input
By externally discharging Ct down to below Vth2, for example with a transistor shown in Fig. 9, the IRS20954 enters
shutdown mode. The operation resumes when the voltage of CSD pin comes back and cross the upper threshold of
CSD, Vth1, by its charging process.
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IRS20954S
VDD
SHUTDOWN
CSH
CSD
VB
IN
HO
VSS
VS
NC
NC
VREF
VCC
OCSET
DT
LO
COM
Figure 9: Shutdown Input
Latched Protection
Connecting CSD to VDD through a 10 kΩ or less resistor configures the IRS20954 as a latched over-current protection.
The over-current protection stays in shutdown mode after over-current condition detected. To reset the latch status, an
external reset switch brings CSD pin voltage down below the lower threshold, Vth2. Minimum reset pulse width
required is 200 ns.
CSH
VDD
<10k
RESET
CSD
VB
IN
HO
VSS
VS
NC
NC
VREF
VCC
OCSET
LO
DT
COM
Figure 10: Latched Protection Configuration
Interfacing with System Controller
The IRS20954 communicates with external system controller by adding simple interfacing circuit shown in Fig. 11. A
generic PNP-BJT U1, such as 2N3906, is to send out SD signal when OCP event happens by capturing sinking
current in CSD pin. Another generic NPN-BJT U2, such as 2N3094, is to reset the internal protection logic by pulling
the CSD voltage below Vth2. Note that the CSD pin is configured as a latched type OCP in this configuration.
VDD
U1
SD
<10k
U2
VSS
VB
IN
HO
VSS
VS
NC
NC
VREF
RESET
CSH
CSD
OCSET
DT
VCC
LO
COM
Figure 11: Interfacing System Controller
Programming OCP Trip Level
In a Class D audio amplifier, the direction of the load current alternates according to the audio input signal. An overcurrent condition can therefore happen during either a positive current cycle or a negative current cycle. The IRS20954
uses RDS(ON) in the output MOSFET as current sensing resistors. Due to the high voltage IC structural constraints, high
and low side have different implementations of current sensing. Once measured current gets exceeded predetermined threshold, OC output signal is fed to the protection block to shutdown the MOSFET to protect the devices.
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IRS20954S
D1
R2
+B
CSH
UV
DETECT
R1
VB
UV
HIGH
SIDE
CS
Q
Dbs
R3
HO
Q1
Cbs
OUT
HV
LEVEL
SHIFT
VS
HV
LEVEL
SHIFT
FLOATING HIGH SIDE
5V REG
Vcc
VCC
UV
DETECT
DEAD TIME
Q2
LO
SD
-B
COM
R5
LOW SIDE CS
OCSET
R4
VREF
Figure 12: Bi-Directional Over-Current Protection
Low Side Over-Current Sensing
For the negative load current, low side over-current sensing monitors over load condition and shutdown the switching operation
if the load current exceeds the preset trip level.
The low side current sensing is based on measurement of VDS during the low side MOFET on state. In order to avoid incorrect
current value due to overshoot , VS sensing ignores the first 200 ns signal after LO turned on.
OCSET pin is to program the threshold for low side over-current sensing. The threshold voltage at VS pin turning on the OC
protection is the same as the voltage applied to the OCSET pin to COM. It is recommended to use VREF to supply a reference
voltage to a resistive divider, R4 and R5, generating a voltage to OCSET for better immunity against VCC fluctuations.
+B
Q1
OC
REF
OCREF
5.1V
R4
R5
OCSET
OUT
VS
0.5mA
-
OC
+
OC Comparator
COM
LO
LO
Q2
IRS20954
-B
Figure 13: Low-Side Over-Current Sensing
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IRS20954S
Since the sensed voltage of VS is compared with the voltages fed to the OCSET pin, the required voltage of OCSET with
respect to COM for a trip level ITRIP+ is:
VOCSET = VDS(LOW SIDE) = ITRIP+ x RDS(ON)
In order to neglect the input bias current of OCSET pin, it is recommended to use 10 kΩ total for R4 and R5 to drain 0.5 mA
through the resistors.
High Side Over-Current Sensing
For the positive load current, high side over-current sensing monitors over load condition by measuring VDS with CSH and Vs
pins and shutdown the operation. The CSH pin is to detect the drain-to-source voltage refers to the VS pin which is the source
of the high side MOSFET. In order to neglect overshoot ringing at the switching edges, CSH sensing circuitry starts monitoring
after the first 300 ns the HO is on by blanking the signal from CSH pin.
In contrast to the low side current sensing, the threshold of CSH pin to engage OC protection is internally fixed at 1.2 V. An
external resistive divider R2 and R3 can be used to program a higher threshold.
An external reverse blocking diode, D1, is to block high voltage feeding into the CSH pin while high side is off. By subtracting a
forward voltage drop of 0.6 V at D1, the minimum threshold which can be set in the high side is 0.6 V across the drain to
source.
With the configuration in Fig. 14, the voltage in CSH is:
VCSH =
R3
⋅ (V DS ( HIGHSIDE ) + V F ( D1) )
R 2 + R3
Where:
VDS(HIGH SIDE) is drain to source voltage of the high side MOSFET in its ON state
VF(D1) is the forward drop voltage of D1
Since VDS(HIGH SIDE) is determined by the product of drain current ID and RDS(ON) in the high side MOSFET. VCSH can be written
as:
VCSH =
R3
⋅ (RDS ( ON ) ⋅ I D + VF ( D1) )
R 2 + R3
R 2 VDS + VF
=
−1
R3 VthOCH
The reverse blocking diode D1 is forward biased by a 10 kΩ resistor R1 when the high side MOSFET is on.
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IRS20954S
CSH
Comparator
OC
D1
R2
CSH
+B
R1
VB
+
-
R3
1.2V
HO
HO
Q1
OUT
VS
Vcc
LO
Q2
IRS20954
-B
Figure 14: Programming High Side Over-Current Threshold
OCP Design Example
High Side Over-current Setting
Fig. 14 demonstrates the typical peripheral circuit of high side current sensing. For example, the over-current protection level is
set to trip at 30 A with a MOSFET with RDS(ON) of 100 mΩ, the component values of R2 and R3 are calculated as:
Choose R2+R3=10 kΩ, thus R3
R3 = 10kΩ
= 10kΩ − R2 .
VthOCH
VDS + VF
VthOCL = 1.2 V
VF = 0.6 V
VDS@ID=30A = 100 mΩ x 30 A = 3 V
VDS is the voltage drop at ID=30 A across RDS(ON) of the high side MOSFET. VF is a forward voltage of reverse blocking diode,
D1. The values of R2 and R3 from the E-12 series are:
R2 = 6.8 kΩ
R3 = 3.3 kΩ
Choosing the Right Reverse Blocking Diode
The reverse blocking diode D1 is determined by voltage rating and speed. To block bus voltage, reverse voltage has to be
higher than (+B)-(-B). Also the reverse recovery time needs to be as fast as the bootstrap charging diode. The Philips BAV21W,
200 V, 50 ns high speed switching diode, is more than sufficient.
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\
IRS20954S
Low Side Over-current Setting
Designing with the same MOSFET as in high side with RDS(ON) of 100 mΩ, the OCSET voltage, VOCSET, to set 30 A
trip level is given by:
VOCSET = ITRIP+ x RDS(ON) = 30 A x 100 mΩ = 3.0 V
Choose R4+R5=10 kΩ for proper loading of VREF pin, thus
R5 =
VOCSET
⋅10kΩ
VREF
3.0V
⋅10kΩ
5.1V
= 5.8kΩ
=
Where VREF is the output voltage of VREF pin, 5.1 V typical.
Choose R5 = 5.6 kΩ and R4 = 3.9 kΩ from E-12 series.
In general, RDS(ON) has a positive temperature coefficient that needs to be considered when the threshold level is being set.
Although this characteristic is preferable from a device protection point of view, these variation needs to be considered as well
as variations of external or internal component values.
Deadtime Generator
The deadtime generator block provides a blanking time between the high-side on and low-side on to avoid a simultaneous on
state causing shoot-through. The IRS20954 has an internal deadtime generation block to reduce the number of external
components in the output stage of a Class D audio amplifier. Selectable deadtime programmed through the DT/SD pin voltage
is an easy and reliable function, which requires only two external resistors. This selectable deadtime way of setting prevents
outside noise from modulating the switching timing, which is critical to the audio performances.
How to Determine Optimal Deadtime
The effective deadtime in an actual application differs from the deadtime specified in this datasheet due to finite switching fall
time, tf. The deadtime value in this datasheet is defined as the time period from the starting point of turn-off on one side of the
switching stage to the starting point of turn-on on the other side as shown in Fig. 15. The fall time of MOSFET gate voltage
must be subtracted from the deadtime value in the datasheet to determine the effective dead time of a Class D audio amplifier.
(Effective deadtime) = (Deadtime in datasheet) – (fall time, tf)
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16
IRS20954S
90%
HO (or LO)
Effective dead-time
10%
tf
LO (or HO)
Deadtime
10%
Figure 15: Effective Deadtime
A longer dead time period is required for a MOSFET with a larger gate charge value because of the longer tf. A shorter
effective deadtime setting is always beneficial to achieve better linearity in the Class D switching stage. However, the likelihood
of shoot-through current increases with narrower deadtime settings in mass production. Negative values of effective deadtime
may cause excessive heat dissipation in the MOSFETs, potentially leading to serious damage. To calculate the optimal
deadtime in a given application, the fall time tf for both output voltages, HO and LO, in the actual circuit needs to be measured.
In addition, the effective deadtime can also vary with temperature and device parameter variations. Therefore, a minimum
effective deadtime of 10 ns is recommended to avoid shoot-through current over the range of operating temperatures and
supply voltages.
Programming Deadtime
DT pin provides a function setting deadtime. The IRS20954 determines its deadtime based on the voltage applied to the DT pin.
An internal comparator translates which pre-determined deadtime is being used by comparing internal reference voltages.
Threshold voltages for each mode are set internally by a resistive voltage divider off VCC, negating the need of using a precise
absolute voltage to set the mode. The relationship between the operation mode and the voltage at DT pin is illustrated in the
Fig. 16 below.
Dead- time
15nS
25nS
35nS
45nS
0.23 xVcc
0.36 xVcc
0.57 xVcc
Vcc
VDT
.
Figure 16: Deadtime Settings vs. VDT Voltage
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17
IRS20954S
Table 1 shows suggested values of resistance for setting the deadtime. Resistors with up to 5% tolerance can be used if these
listed values are followed.
IRS20954
>0.5mA
Vcc
R6
DT
R7
COM
Figure 17: External Resistor
Deadtime
R6
R7
DT/SD
mode
voltage
DT1
<10 kΩ
Open
1.0·(Vcc)
DT2
3.3 kΩ
8.2 kΩ
0.71·(Vcc)
DT3
5.6 kΩ
4.7kΩ
0.46·(Vcc)
DT4
8.2 kΩ
3.3 kΩ
0.29·(Vcc)
Table 1: Suggested Resistor Values for Deadtime Settings
Power Supply Considerations
Supplying VDD
VDD is designed to be supplied with the internal zener diode clamp. VDD supply current IDD can be estimated by:
-9
IDD = 1.5 mA x 300 x 10 x switching frequency + 0.5 mA + 0.5 mA
(Dynamic power consumption)
(Static) (zener bias)
The resistance of Rdd to feed this IDD therefore is:
Rdd ≤
V+ B − 10.8V [Ω]
I DD
In case of 400 kHz average PWM switching frequency, the required IDD is 1.18 mA. A condition using 50 V power supply
voltage yields Rdd=33 kΩ.
Make sure IDD is below the maximum zener diode bias current, IDDZ, at static state conditions such as a condition with no PWM
input.
I DDZ ≥
V+ B − 10.8V
− 0.5mA
Rdd
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18
IRS20954S
Rdd
IRS20954S
VDD
VB
CSD
10.4V
IN
PWM
+B
CSH
HO
VSS
VS
NC
NC
VCC
VREF
LO
OCSET
COM
DT
Vcc
12V
-B
Figure 18: Supplying VDD
Charging VBS Prior to start
The high side bootstrap power supply can be charged up through a resistor from the positive supply bus to VB pin by utilizing an
internal 20.8 V zener diode clamp between VB and VS. Advantage of this scheme is to eliminate the minimum duration required
for the initial low-side ON.
To determine the requirement for Rcharge, following condition has to be met;
I CHARGE > I QBS
Where ICHARGE is a required charging current through Rcharge
IQBS is high side quiescent current
Note that Rcharge can drain floating supply charge during on state of high side, which limits maximum PWM modulation index
capability of the system. Rcharge should be large enough not to discharge the floating power supply during the high side ON.
Icharge
IRS20954S
IQBS
CSD
IN
VREF
OCSET
VB
HO
NC
20.8V
NC
Rcharge
VS
IQBC
VSS
DT
+B
CSH
20.8V
VDD
VCC
LO
COM
Vcc
12V
-B
Figure 19: Bootstrap Supply Pre-Charging
Start-up Sequence (UVLO)
The protection control block monitors the status of the power supply of VDD and VCC whether the voltages are above the Under
Voltage Lockout threshold. The LO and HO of the IRS20954 are disabled by shutdown until the UVLO of VCC and VDD are
released and CSD timer capacitor Ct is charged up. After the UVLO of VCC is released, CSD pin resets power-on timer. At the
time the voltage at CSD pin reached the release threshold, Vth1, shutdown logic enables LO and HO. The OC detection blocks
for the low side and high side are disabled until UVLO of VCC and VBS are released.
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19
IRS20954S
Power-down Sequence
As soon as VDD or VCC reaches the UVLO negative going threshold, protection logic makes LO and HO 0 V to turn off the
MOSFET.
UVLO( VCC )
VCC
CHARGE /
DISCHARGE
Discharge
HO
LO
Figure 20: IRS20954 Power-Down Timing Chart
Power Supply Decoupling
As the IRS20954 contains analog circuitry, careful attention to the power supply decoupling should be taken to achieve proper
operation. Ceramic capacitors of 0.1 µF or more close to the power supply pins are recommended.
Please also refer to the application note AN-978 for general considerations of high voltage gate driver IC.
VSS Negative Bias Clamping
There is a case that VSS can go below the COM potential such as a case missing negative supply in dual supply configuration.
This causes excessive negative VSS voltage to damage the IRS20954. It is recommended to have a diode to clamp potential
negative bias to VSS, if there is a possibility. A standard recovery 1 A diode such as 1N4002 is sufficient in most cases for this
purpose.
VDD
VB
IN
HO
VSS
VS
NC
NC
VREF
Negative VSS
Clamping Diode
CSH
CSD
OCSET
DT
VCC
LO
COM
-Vbus
Figure 21: Negative VSS Clamping
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20
IRS20954S
Junction Temperature Estimation
The power dissipation in the IRS20954 consists of following dominant items;
PMID: dissipation in floating input logic and protection
PLOW: dissipation in low side
PHIGH: dissipation in high side
1.
PMID: Dissipation in Floating Input Section
The dissipation in floating input section is given by;
PMID = PZDD + PLDD
≈
V+ BUS − VDD
⋅ VDD
RDD
Where
PZDD is dissipation from internal zener diode clamping VDD voltage.
PLDD is dissipation from internal logic circuitry.
V+BUS is positive bus voltage feeding VDD from.
RDD is a resistor feeding VDD from V+BUS.
For obtaining a value of RDD, refer to Supplying VDD section above.
2.
PLOW: Dissipation in Low Side
The dissipation in low side includes loss from logic circuitry and loss from driving LO, and is given by;
PLOW = PLDD + PLO


RO

= (I QCC ⋅ VCC ) + Vcc ⋅ Qg ⋅ f SW ⋅

RO + Rg + Rg (int) 

Where
PLDD is dissipation from internal logic circuitry.
PLO is dissipation from gate drive stage to LO.
RO is equivalent output impedance of LO, typically 10 Ω for the IRS20954.
Rg(int) is internal gate resistance of MOSFET.
Rg is external gate resistance.
Qg is total gate charge of low side MOSFET.
3.
PHIGH: Dissipation in High Side
The dissipation in high side includes loss from logic circuitry and loss from driving LO and is given by;
PHIGH = PLDD + PHO


RO

= (I QBS ⋅ VBS ) + VBS ⋅ Qg ⋅ f SW ⋅

RO + Rg + Rg (int) 

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21
IRS20954S
Where
PLDD is dissipation from internal logic circuitry.
PHO is dissipation from gate drive stage to LO.
RO is equivalent output impedance of HO, typically 10 Ω for the IRS20954.
Rg(int) is internal gate resistance of high side MOSFET.
Rg is external gate resistance.
Qg is total gate charge of high side MOSFET.
Then, total dissipation Pd is given by;
Pd = PMID + PLOW + PHIGH
Estimated Tj from the thermal resistance between ambient and junction temperature, RthJA;
T j = RthJA ⋅ Pd + TA < 150°C
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22
IRS20954S
Case Outline
NOTES:
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5W-1982
2. CONTROLLING DIMENSION. MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETER [INCHES]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AC
5. DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE
6. DIMENSION DOES NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED
0.15 [.006]
16-Lead SOIC (narrow body)
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23
IRS20954S
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
N OTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
15.70
16.30
D
7.40
7.60
E
6.40
6.60
F
10.20
10.40
G
1.50
n/a
H
1.50
1.60
16SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.618
0.641
0.291
0.299
0.252
0.260
0.402
0.409
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 16SOICN
Metric
Imperial
Code
Min
Max
Min
Max
A
329.60
330.25
12.976
13.001
B
20.95
21.45
0.824
0.844
C
12.80
13.20
0.503
0.519
D
1.95
2.45
0.767
0.096
E
98.00
102.00
3.858
4.015
F
n/a
22.40
n/a
0.881
G
18.50
21.10
0.728
0.830
H
16.40
18.40
0.645
0.724
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24
IRS20954S
LEAD-FREE PART MARKING INFORMATION
Part number
Date code
IRSxxxxx
YWW?
?XXXX
Pin 1
Identifier
?
P
IR logo
MARKING CODE
Lead Free Released
Non-Lead Free
Relased
Lot Code
(Prod mode – 4 digit SPN code)
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
16-Lead SOIC IRS20954SPbF
16-Lead SOIC Tape & Reel IRS20954STRPbF
SO-16 package is MSL3 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/3/2006
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25
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