ASIX AX88195P 10/100base local cpu bus fast ethernet mac controller Datasheet

AX88195P
10/100BASE Fast Ethernet MAC Controller
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
Document No.: AX195-17 / V1.7 / May. 12 ’00
Features
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IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
NE2000 register level compatible instruction
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides a MII port for both 10/100Mbps operation
Support EEPROM interface to store MAC address
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External and internal loop-back capability
Two external 32K*8 Asynchronous SRAMs
required for packet buffer
128-pin LQFP low profile package
25MHz Operation, Dual 5V and 3.3V CMOS
process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88195 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller.
The AX88195 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80x86 series, MC68K series
CPU and ISA bus. The AX88195 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify the
design. Two low cost 32k*8 SRAM is required for packet buffer.
System Block Diagram
BUFFER
SRAM
AD BUS
LATCH
CPU
Addr L
Addr H
AX88195
PHY/TxRx
RJ45
Ctl BUS
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : Oct/02/1998
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88195 Local CPU Bus Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 4
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 4
1.2 AX88195 BLOCK DIAGRAM: .............................................................................................................................. 4
1.3 AX88195 PIN CONNECTION DIAGRAM ............................................................................................................... 5
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode................................................................................ 6
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode................................................................................... 7
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode ................................................................................ 8
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode ............................................................................... 9
2.0 SIGNAL DESCRIPTION ................................................................................................................................. 10
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ................................................................................................... 10
2.2 MII INTERFACE SIGNALS GROUP........................................................................................................................ 11
2.3 EEPROM SIGNALS GROUP .............................................................................................................................. 12
2.4 SRAM INTERFACE PINS GROUP......................................................................................................................... 12
2.5 MISCELLANEOUS PINS GROUP............................................................................................................................ 12
2.6 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 13
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 14
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 14
3.2 I/O MAPPING ................................................................................................................................................... 14
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 14
4.0 REGISTERS OPERATION ............................................................................................................................. 15
4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE)................................................................................... 17
4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE) ..................................................................... 17
4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE) ................................................................................. 18
4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE)....................................................................... 18
4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE)................................................................ 18
4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ) ................................................................................ 19
4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE) .................................................................................. 19
4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ) .................................................................................. 19
4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE) ...................................................................................... 20
4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE) ............................................................... 20
4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE) ............................................................... 20
4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE) .............................................. 20
4.13 TEST REGISTER (TR) OFFSET 15H (WRITE) ................................................................................................... 20
5.0 CPU I/O READ AND WRITE FUNCTIONS .................................................................................................. 21
5.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 21
5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 21
5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 22
5.3 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .................................................................................................... 22
6.0 ELECTRICAL SPECIFICATION AND TIMINGS........................................................................................ 23
6.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 23
6.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23
6.3 DC CHARACTERISTICS ..................................................................................................................................... 23
6.4 A.C. TIMING CHARACTERISTICS ....................................................................................................................... 24
6.4.1 XTAL / CLOCK........................................................................................................................................ 24
6.4.2 Reset Timing ............................................................................................................................................ 24
6.4.3 ISA Bus Access Timing............................................................................................................................. 25
6.4.4 80186 Type I/O Access Timing ................................................................................................................. 26
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.5 68K Type I/O Access Timing .................................................................................................................... 27
6.4.6 8051 Bus Access Timing........................................................................................................................... 28
6.4.7 MII Timing............................................................................................................................................... 29
6.4.8 Asynchronous Memory I/F Access Timing ................................................................................................ 30
7.0 PACKAGE INFORMATION........................................................................................................................... 31
APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 32
A.1 USING CRYSTAL.............................................................................................................................................. 32
A.2 USING OSCILLATOR......................................................................................................................................... 32
A.3 DUAL POWER (5V AND 3.3V/3.0V) APPLICATION ............................................................................................. 33
A.4 SINGLE POWER (3.3V/3.0V) APPLICATION ........................................................................................................ 33
A.5 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY............................................................................. 34
APPENDIX B: APPLICATION NOTE 2 ............................................................................................................. 35
B.1 ADVANCE APPLICATION FOR USING CRYSTAL................................................................................................... 35
APPENDIX C: APPLICATION NOTE FOR RDY IS NOT APPLICABLE ...................................................... 36
ERRATA OF AX88195 V1..................................................................................................................................... 37
FIGURES
FIG - 1 AX88195 BLOCK DIAGRAM ............................................................................................................................. 4
FIG - 2 AX88195 PIN CONNECTION DIAGRAM .............................................................................................................. 5
FIG - 3 AX88195 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ............................................................................... 6
FIG - 4 AX88195 PIN CONNECTION DIAGRAM FOR 80X86 MODE .................................................................................. 7
FIG - 5 AX88195 PIN CONNECTION DIAGRAM FOR MC68K MODE................................................................................ 8
FIG - 6 AX88195 PIN CONNECTION DIAGRAM FOR MCS-51 MODE ............................................................................... 9
TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP .................................................................................................. 11
TAB - 2 MII INTERFACE SIGNALS GROUP ..................................................................................................................... 11
TAB - 3 EEPROM BUS INTERFACE SIGNALS GROUP ..................................................................................................... 12
TAB - 4 SRAM INTERFACE PINS GROUP ...................................................................................................................... 12
TAB - 5 MISCELLANEOUS PINS GROUP ......................................................................................................................... 13
TAB - 6 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 13
TAB - 7 I/O ADDRESS MAPPING ................................................................................................................................. 14
TAB - 8 LOCAL MEMORY MAPPING ............................................................................................................................ 14
TAB - 9 PAGE 0 OF MAC CORE REGISTERS MAPPING .................................................................................................. 15
TAB - 10 PAGE 1 OF MAC CORE REGISTERS MAPPING ................................................................................................ 16
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
1.0 Introduction
1.1 General Description:
The AX88195 provides industrial standard NE2000 registers level compatable instruction set. Various drivers
are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to
various embedded system with no pain and tears
The AX88195 Fast Ethernet Controller is a high performance local CPU bus Ethernet Controller. The AX88195
supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80x86 series, MC68K series CPU
and ISA bus. The AX88196 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify
the design.
AX88195 use 128-pin LQFP low profile package, 25MHz operation, dual 5V and 3.3V CMOS process with 5V
I/O tolerance or pure 3.3V operation.
1.2 AX88195 Block Diagram:
MEMA[15:1]
MEMD[15:0]
SRAM
Arbiter
EECS
EECK
EEDI
EEDO
STA
SEEPROM
I/F
MII I/F
Remote
DMA
FIFOs
NE2000
Registers
MAC
Core
Host Interface
Ctl BUS
SA[9:0]
SD[15:0]
Fig - 1 AX88195 Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
1.3 AX88195 Pin Connection Diagram
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TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
The AX88195 is housed in the 128-pin plastic light quad flat pack. Fig - 2 shows the AX88195 pin
connection diagram.
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AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
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HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
/MEMRD
/MEMWR
VSS
NC
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
/UDS SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
/IRQ IRQ
NC
R/W /IOWR
/IORD
NC
NC
/LDS /BHE
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
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TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL[0]
SAL[1]
SAL[2]
SAH[0]
SAH[1]
SAH[2]
SAX[0]
SAX[1]
VSS
/IOCS16
SAX[2]
SAX[3]
/CS
AEN/PSEN
RDY/DTACK
/RESET
RESET
LVDD
Fig - 2 AX88195 Pin Connection Diagram
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
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TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode
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AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
( for ISA Bus I/F )
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HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
/MEMRD
/MEMWR
VSS
NC
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
IRQ
NC
/IOWR
/IORD
NC
NC
/BHE
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
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TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL[0]
SAL[1]
SAL[2]
SAH[0]
SAH[1]
SAH[2]
SAX[0]
SAX[1]
VSS
/IOCS16
SAX[2]
SAX[3]
/CS
AEN
RDY
/RESET
RESET
LVDD
Fig - 3 AX88195 Pin Connection Diagram for ISA Bus Mode
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
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TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode
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AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for x86 Interface)
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HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
/MEMRD
/MEMWR
VSS
NC
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
IRQ
NC
/IOWR
/IORD
NC
NC
/BHE
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
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TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL[0]
SAL[1]
SAL[2]
SAH[0]
SAH[1]
SAH[2]
SAX[0]
SAX[1]
VSS
NC
SAX[2]
SAX[3]
/CS
NC
RDY
/RESET
RESET
LVDD
Fig - 4 AX88195 Pin Connection Diagram for 80x86 Mode
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
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TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode
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AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for 68K Interface)
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HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
/MEMRD
/MEMWR
VSS
NC
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
/UDS
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
/IRQ
NC
R/W
NC
NC
NC
/LDS
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
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TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL[0]
SAL[1]
SAL[2]
SAH[0]
SAH[1]
SAH[2]
SAX[0]
SAX[1]
VSS
NC
SAX[2]
SAX[3]
/CS
NC
/DTACK
/RESET
RESET
LVDD
Fig - 5 AX88195 Pin Connection Diagram for MC68K Mode
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
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TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode
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113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AX88195
LOCAL CPU BUS
10/100BASE MAC
CONTROLLER
(for 8051 Interface)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
/MEMRD
/MEMWR
VSS
NC
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
/IRQ
NC
/IOWR
/IORD
NC
NC
NC
HVDD
NC
NC
NC
NC
VSS
NC
NC
NC
NC
HVDD
SD[7]
SD[6]
SD[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
SAL[0]
SAL[1]
SAL[2]
SAH[0]
SAH[1]
SAH[2]
SAX[0]
SAX[1]
VSS
NC
SAX[2]
SAX[3]
/CS
/PSEN
NC
/RESET
RESET
LVDD
Fig - 6 AX88195 Pin Connection Diagram for MCS-51 Mode
9
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
2.0 Signal Description
The following terms describe the AX88195 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 Local CPU Bus Interface Signals Group
SIGNAL
SAL[2:0]
TYPE
I/PD
PIN NO.
113 – 111
SAH[2:0]
I/PU
116 – 114
SAX[3:0]
I/PU
122 – 121
118 – 117
SA[9:1],
SA[0]/UDS
I
10 – 1
/BHE
or
/LDS
I
18
I/O
O
20 – 23,
25 – 28,
30 – 33,
35 – 38
12
OD
125
/CS
I
123
/IORD
I
15
/IOWR
or
R/W
I
14
SD[15:0]
IREQ/IREQ
RDY/DTACK
DESCRIPTION
System Address Select Low : Signals SAL[2:0] are additional address
signal input lines which active low enable higher I/O address decoder
on chip.
System Address Select High : Signals SAH[2:0] are additional
address signal input lines which active high enable higher I/O
address decoder on chip.
System Address Select Low/High : Signals SAX[3:0] are additional
address signal input lines which active low/high depend on power on
setting to enable higher I/O address decoder on chip.
System Address : Signals SA[9:0] are address bus input lines which
lower I/O spaces on chip. SA[0] also means Upper Data Strobe
(/UDS) active low signal in 68K application mode.
Bus High Enable or Lower Data Strobe : Bus High Enable is active
low signal in some 16 bit application mode which enable high bus
(SD[15:8]) active. The signal also name as Lower Data Strobe (/LDS)
for 68K application mode.
System Data Bus : Signals SD[15:0] constitute the bi-directional
data bus.
Interrupt Request : When ISA BUS or 80186 CPU mode is select.
IREQ is asserted high to indicate the host system that the chip
requires host software service. When MC68K or MCS-51 CPU
mode is select. /IREQ is asserted low to indicate the host system that
the chip requires host software service.
Ready : This signal is set low to insert wait states during Remote
DMA transfer.
/Dtack : When Motorola CPU type is select, the pin is active low
inform CPU that data is accepted.
Chip Select
When the /CS signal is asserted, the chip is selected.
I/O Read :The host asserts /IORD to read data from AX88195 I/O
space. When Motorola CPU type is select , the pin is useless.
I/O Write :The host asserts /IOWR to write data into AX88195 I/O
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
/IOCS16
OD
120
AEN
I/PD
124
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88195 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88195, this signal is active high to access the chip. This
signal is for 8051 bus application only.
or
/PSEN
Tab - 1 Local CPU bus interface signals group
2.2 MII interface signals group
SIGNAL
RXD[3:0]
TYPE
I
PIN NO.
90 – 87
CRS
I
85
RX_DV
I
83
RX_ER
I
82
RX_CLK
I
86
COL
TX_EN
I
O
84
95
TXD[3:0]
O
99 – 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
DESCRIPTION
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 2 MII interface signals group
11
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
2.3 EEPROM Signals Group
SIGNAL
EECS
EECK
EEDI
EEDO
TYPE
O
O
O
I/PU
PIN NO.
106
107
108
109
DESCRIPTION
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 3 EEPROM bus interface signals group
2.4 SRAM Interface pins group
SIGNAL
MEMA[15:1]
TYPE
O
MEMD[15:0]
I/O/PU
/MEMRD
/MEMWR
O
O
PIN NO.
43, 45 – 48,
50 –53’
55 – 58,
60 – 61
62 – 63,
65 – 68,
70 – 74,
76 – 80
42
41
DESCRIPTION
SRAM Address :
SRAM Data :
SRAM Read
SRAM Write
Tab - 4 SRAM Interface pins group
2.5 Miscellaneous pins group
SIGNAL
LCLK/XTALIN
TYPE
I
XTALOUT
O
CLKO25M
RESET
O
I/PD
/RESET
I/PU
NC
N/A
LVDD
P
PIN NO.
103
DESCRIPTION
CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty
cycle.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
104
Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
101
Clock Output 25MHz : This clock is source from LCLK/XTALIN.
127
Reset
Reset is active high then place AX88195 into reset mode immediately.
During Falling edge the AX88195 loads the power on setting data.
User can select either RESET or /RESET for applications.
126
/Reset
Reset is active low then place AX88195 into reset mode immediately.
During rising edge the AX88195 loads the power on setting data.
User can select either RESET or /RESET for applications.
13, 16, 17, No Connection : for manufacturing test only.
39
44, 54,
Power Supply : +3.3V DC.
100, 110,
128
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
HVDD
P
VSS
P
19, 29, 64, Power Supply : +5V DC.
75
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
11, 24, 34, Power Supply : +0V DC or Ground Power.
40, 49,59,
69, 81,93,
102, 105,
119
Tab - 5 Miscellaneous pins group
2.6 Power on configuration setup signals cross reference table
SIGNAL NAME SHARE WITH
DESCRIPTION
IO_BASE[2:0]
MEMD[15:13]
IO_BASE[2] IO_BASE[1] IO_BASE[0]
IO_BASE
0
0
0
300h
0
0
1
320h
0
1
0
340h
0
1
1
360h
1
0
0
380h
1
0
1
3A0h
1
1
0
200h
1
1
1
220h
SAX[3:0]
MEMD[12:9]
SAX[3] address decode depends on MEMD[12] power on value
SAX[2] address decode depends on MEMD[11] power on value
SAX[1] address decode depends on MEMD[10] power on value
SAX[0] address decode depends on MEMD[9] power on value
CPU TYPE
MEMD[8:7]
MEMD[8] MEMD[7]
CPU TYPE
0
0
ISA BUS
0
1
80186
1
0
MC68K
1
1
MCS-51 (805X)
All of the above signals are pull-up for default values.
Tab - 6 Power on Configuration Setup Table
13
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88195.
1.
2.
3.
EEPROM Memory Mapping
I/O Mapping
Local Memory Mapping
3.1 EEPROM Memory Mapping
User can define by themselves and can access via I/O address offset 14H MII/EEPROM registers
3.2 I/O Mapping
SYSTEM I/O OFFSET
0000H
001FH
FUNCTION
MAC CORE REGISTER
Tab - 7 I/O Address Mapping
3.3 SRAM Memory Mapping
OFFSET
4000H
7FFF
0000H
FFFFH
FUNCTION
NE2000 COMPATABLE MODE
8K X 16 SRAM BUFFER
EXTENSION MODE
32K X 16 SRAM BUFFER
Tab - 8 Local Memory Mapping
14
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.0 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the Command
Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
00H
0AH
READ
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Status Register
( TSR )
Number of Collisions Register
( NCR )
Current Page Register
( CPR )
Interrupt Status Register
( ISR )
Current Remote DMA Address 0
( CRDA0 )
Current Remote DMA Address 1
( CRDA1 )
Reserved
0BH
Reserved
0CH
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Missed Packet Errors
( CNTR2 )
Data Port
01H
02H
03H
04H
05H
06H
07H
08H
09H
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
to
1EH
1FH
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 0
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Inter-frame Gap (IFG)
Reserved
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Reset
Reserved
Tab - 9 Page 0 of MAC Core Registers Mapping
15
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
to
1EH
1FH
READ
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
WRITE
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Inter-frame Gap (IFG)
Reserved
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Reset
Reserved
Tab - 10 Page 1 of MAC Core Registers Mapping
16
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.1 Command Register (CR) Offset 00H (Read/Write)
FIELD
7:6
5:3
2
1
0
NAME
DESCRIPTION
PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1
PS0
0 0
page 0
0 1
page 1
RD2,RD1 RD2,RD1,RD0 : Remote DMA Command
,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88195 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0
0
0
Not allowed
0
0
1
Remote Read
0
1
0
Remote Write
0
1
1
Not allowed
1
X
X
Abort / Complete Remote DMA
TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
START START :
This bit is used to active AX88195 operation.
STOP STOP : Stop AX88195
This bit is used to stop the AX88195 operation.
4.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
RST Reset Status :
Set when AX88195 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
RDC Remote DMA Complete
Set when remote DMA operation has been completed
CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
TXE Transmit Error
Set when packet transmitted with one or more of the following errors
n Excessive collisions
n FIFO Underrun
RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
PTX Packet Transmitted
Indicates packet transmitted with no error
PRX Packet Received
Indicates packet received with no error.
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
RDCE
CNTE
OVWE
TXEE
RXEE
PTXE
PRXE
DESCRIPTION
Reserved
DMA Complete Interrupt Enable. Default “low” disabled.
Counter Overflow Interrupt Enable. Default “low” disabled.
Overwrite Interrupt Enable. Default “low” disabled.
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
4.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD
7
6:2
1
0
NAME
DESCRIPTION
RDCR Remote DMA always completed
Reserved
BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80186).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(MC68K)
WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
7
6
5
4:3
2:1
0
NAME
DESCRIPTION
FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
Reserved
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0
0
0
Normal operation
Mode 1
0
1
Internel NIC loop-back
Mode 2
1
0
PHYcevisor loop-back
CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD
7
6:4
3
2
1
0
NAME
DESCRIPTION
OWC Out of window collision
Reserved
ABT Transmit Aborted
Indicates the AX88195 aborted transmission because of excessive collision.
COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
Reserved
PTX Packet Transmitted
Indicates transmission without error.
4.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
Reserved
INTT Interrupt Trigger Mode for ISA and 80186 modes
0 : Low active
1 : High active (default)
Interrupt Trigger Mode for MCS-51 and MC68K modes
0 : High active
1 : Low active (default)
MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
AM
AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
AB
AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
AR
AR : Accept Runt
Enable the receiver to accept runt packet.
SEP
SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD
7
6
5
4
3
2
1
0
NAME
DIS
PHY
MPA
FO
FAE
CR
PRX
DESCRIPTION
Reserved
Receiver Disabled
Multicast Address Received.
Missed Packet
FIFO Overrun
Frame alignment error.
CRC error.
Packet Received Intact
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ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap. Default value 15H.
4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 1. Default value 0cH.
4.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 2. Default value 11H.
4.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
EECLK EECLK:
EEPROM Clock
EEO EEO : (Read only)
EEPROM Data Out value. That reflects Pin-109 EEDO value.
EEI
EEI
EEPROM Data In. That output to Pin-108 EEDI as EEPROM data input value.
EECS EECS
EEPROM Chip Select
MDO MDO
MII Data Out
MDI MDI: (Read only)
MII Data In. That reflects Pin-91 MDIO value.
MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
MDC MDC
MII Clock
4.13 Test Register (TR) Offset 15H (Write)
FIELD
7:5
4
3
2:0
NAME
TF16T
TPE
IFG
DESCRIPTION
Reserved
Test for Collision
Test pin Enable
Select Test Pins Output
20
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
5.0 CPU I/O Read and Write Functions
The AX88195 supports four kinds of CPU/BUS types access function, including ISA, 80186,
MC68000 and MCS-51. These Access methods are described as the following sections.
5.1 ISA bus type access functions.
ISA bus I/O Read function
Function Mode
/CS
/BHE
Standby Mode
H
X
Byte Access
L
H
L
H
Word Access
L
L
A0
X
L
H
L
/IORD
X
L
L
L
/IOWR
X
H
H
H
SD[15:8]
High-Z
Not Valid
Not Valid
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Odd-Byte
Even-Byte
ISA bus I/O Write function
Function Mode
/CS
/BHE
Standby Mode
H
X
Byte Access
L
H
L
H
Word Access
L
L
A0
X
L
H
L
/IORD
X
H
H
H
/IOWR
X
L
L
L
SD[15:8]
X
X
X
Odd-Byte
SD[7:0]
X
Even-Byte
Odd-Byte
Even-Byte
5.2 80186 CPU bus type access functions.
80186 CPU bus I/O Read function
Function Mode
/CS
/BHE
Standby Mode
H
X
Byte Access
L
H
L
L
Word Access
L
L
A0
X
L
H
L
/IORD
X
L
L
L
/IOWR
X
H
H
H
SD[15:8]
High-Z
Not Valid
Odd-Byte
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Not Valid
Even-Byte
80186 CPU bus I/O Write function
Function Mode
/CS
/BHE
Standby Mode
H
X
Byte Access
L
H
L
L
Word Access
L
L
A0
X
L
H
L
/IORD
X
H
H
H
/IOWR
X
L
L
L
SD[15:8]
X
X
Odd-Byte
Odd-Byte
SD[7:0]
X
Even-Byte
X
Even-Byte
21
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
5.3 MC68K CPU bus type access functions.
68K bus I/O Read function
Function Mode
/CS
/UDS
Standby Mode
H
X
Byte Access
L
H
L
L
Word Access
L
L
/LDS
X
L
H
L
R/W
X
H
H
H
SD[15:8]
High-Z
Not Valid
Even-Byte
Even-Byte
SD[7:0]
High-Z
Odd-Byte
Not Valid
Odd-Byte
68K bus I/O Write function
Function Mode
/CS
/UDS
Standby Mode
H
X
Byte Access
L
H
L
L
Word Access
L
L
/LDS
X
L
H
L
R/W
X
L
L
L
SD[15:8]
X
X
Even-Byte
Even-Byte
SD[7:0]
X
Odd-Byte
X
Odd-Byte
5.3 MCS-51 CPU bus type access functions.
8051 bus I/O Read function
Function Mode
/CS
/PSEN
Standby Mode
H
X
X
L
Byte Access
L
H
L
H
SA0
X
X
L
H
/IORD
X
X
L
L
/IOWR
X
X
H
H
SD[15:8]
High-Z
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
High-Z
Even-Byte
Odd-Byte
8051 bus I/O Write function
Function Mode
/CS
/PSEN
Standby Mode
H
X
X
L
Byte Access
L
H
L
H
SA0
X
X
L
H
/IORD
X
X
H
H
/IOWR
X
X
L
L
SD[15:8]
X
X
X
X
SD[7:0]
X
X
Even-Byte
Odd-Byte
22
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Ta
0
+85
°C
Ts
-55
+150
°C
HVdd
-0.3
+6
V
LVdd
-0.3
+4.6
V
HVin
-0.3
HVdd+0.5
V
LVin
-0.3
LVdd+0.5
V
Output Voltage
HVout
-0.3
HVdd+0.5
V
LVin
-0.3
LVdd+0.5
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+220
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
Operating Temperature
Storage Temperature
Supply Voltage
Supply Voltage
Input Voltage
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
Ta
0
HVdd +4.75V
LVdd +2.70
+3.00
Tpy
25
+5.00V
+3.00
+3.30
Max
+75
+5.25V
+3.30
+3.60
Units
°C
V
V
V
Max
Units
V
V
V
V
uA
uA
Max
Units
V
V
V
V
uA
uA
Max
Units
mA
mA
mA
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Min
2
Vdd-0.4
-1
-1
Tpy
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Min
1.9
Vdd-0.4
-1
-1
Tpy
SYM
DPt5v
DPt3v
SPt3v
Min
Description
Power Consumption (Dual power)
Power Consumption (Single power 3.3V)
23
0.8
0.4
+1
+1
0.8
0.4
+1
+1
Tpy
20
38
46
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
Thigh
LCLK/XTALIN
Tr
Tf
Tlow
Tcyc
CLK25M
Tod
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Tod
Description
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
LCLK/XTALIN TO CLK25M OUT DELAY
(INVERTED)
Max
16
16
1
1
Typ.
40
20
20
3
24
24
4
6
Units
ns
ns
ns
ns
ns
Min
100
Typ.
-
Max
-
Units
LClk
6.4.2 Reset Timing
LCLK/XTALIN
RESET
/RESET
Symbol
Trst
Description
Reset pulse width
24
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.3 ISA Bus Access Timing
Tsu(AEN)
Th(AEN)
AEN
Tsu(A)
Th(A)
/BHE
SA[9:0],SAL,SAH,SAX
Tv(CS16-A)
Tdis(CS16-A)
/IOCS16
Ten(RD)
/IOWR,/IORD
Tw(RW)
Tv(RDY)
Tdis(RDY)
RDY
Tdis(RD)
Read Data
SD[15:0](Dout)
DATA Valid
Tsu(WR)
Write Data
SD[15:0](Din)
Symbol
Th(WR)
DATA Input Establish
Min
Typ.
0
5
0
5
0
0.5
5
5
*90
* Note : for byte access minimum is 90ns, for word access minimum is 50 ns.
Tsu(A)
Th(A)
Tsu(AEN)
Th(AEN)
Tv(CS16-A)
Tdis(CS16-A)
Tv(RDY)
Tdis(RDY)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
Tw(RW)
Description
ADDRESS SETUP TIME
ADDRESS HOLD TIME
AEN SETUP TIME
AEN HOLD TIME
/IOCS16 VALID FROM ADDRESS CHANGE
/IOCS16 DISABLE FROM ADDRESS CHANGE
RDY VALID FROM /IORD OR /IOWR
RDY DISABLE FROM /IORD OR /IOWR
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
/IORD OR /IOWR WIDTH TIME
25
Max
20
6
20
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.4 80186 Type I/O Access Timing
Tsu(A)
Th(A)
/BHE
SA[9:0],SAL,SAH,SAX
Tw(RW)
/IOWR,/IORD
Tv(RDY)
Tdis(RDY)
RDY
Ten(RD)
Tdis(RD)
Read Data
SD[15:0](Dout)
DATA Valid
Tsu(WR)
Write Data
SD[15:0](Din)
Symbol
Th(WR)
DATA Input Establish
Min
Typ.
0
5
0
0.5
5
5
*90
* Note : for byte access minimum is 90ns, for word access minimum is 50 ns.
Tsu(A)
Th(A)
Tv(RDY)
Tdis(RDY)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
Tw(RW)
Description
ADDRESS SETUP TIME
ADDRESS HOLD TIME
RDY VALID FROM /IORD OR /IOWR
RDY DISABLE FROM /IORD OR /IOWR
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
/IORD OR /IOWR WIDTH TIME
26
Max
20
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.5 68K Type I/O Access Timing
Tsu(A)
Th(A)
SA[9:1],SAL,SAH,SAX
Tv(DS-WR)
Tw(DS)
Tdis(WR-DS)
/UDS,/LDS
(Read)
R/W
Ten(DS)
(Write)
R/W
Tv(DTACK)
Tdis(DTACK)
/DTACK
Tdis(DS)
(Read Data)
SD[15:0](Dout)
DATA Valid
Tsu(DS)
Th(DS)
(Write Data)
SD[15:0](Din)
Symbol
DATA Input Establish
Min
Typ.
0
5
0
5
0
0.5
5
5
*90
* Note : for byte access minimum is 90ns, for word access minimum is 50 ns.
Tsu(A)
Th(A)
Tv(DS-WR)
Tdis(WR-DS)
Tv(DTACK)
Tdis(DTACK)
Ten(DS)
Tdis(DS)
Tsu(DS)
Th(DS)
Tw(DS)
Description
ADDRESS SETUP TIME
ADDRESS HOLD TIME
/UDS OR /LDS VALID FROM /W
/W DISABLE FROM /UDS OR /LDS
DACK VALID FROM /UDS OR /LDS
DACK DISABLE FROM /UDS OR /LDS
OUTPUT ENABLE TIME FROM /UDS OR /LDS
OUTPUT DISABLE TIME FROM /UDS OR /LDS
DATA SETUP TIME
DATA HOLD TIME
/UDS OR /LDS WIDTH TIME
27
Max
20
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.6 8051 Bus Access Timing
/PSEN
Tsu(PSEN)
Th(PSEN)
Tsu(A)
Th(A)
SA[9:0],SAL,SAH,SAX
Ten(RD)
/IOWR,/IORD
Tw(RW)
Tv(RDY)
Tdis(RDY)
(For Reference)
RDY
Tdis(RD)
Read Data
SD[7:0](Dout)
DATA Valid
Tsu(WR)
Write Data
SD[7:0](Din)
Symbol
Tsu(A)
Th(A)
Tsu(PSEN)
Th(PSEN)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
Tw(RW)
Th(WR)
DATA Input Establish
Description
Min
0
5
0
5
0.5
5
5
90
ADDRESS SETUP TIME
ADDRESS HOLD TIME
/PSEN SETUP TIME
/PSEN HOLD TIME
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
/IORD OR /IOWR WIDTH TIME
28
Typ.
-
Max
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.7 MII Timing
Ttclk
Ttch
Ttcl
TXCLK
Ttv
Tth
TXD<3:0>
TXEN
Trclk
Trch
Trcl
RXCLK
Trs
Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
5
14
140
14
140
6
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
RXER data setup time
29
Typ.
40
400
40
400
-
Max
26
260
26
260
20
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.8 Asynchronous Memory I/F Access Timing
MEMORY WRITE
Tsu(A)
Th(A)
MEMA[15:1]
Tw(WR)
/MEMWR
Td(WtoR)
Tw(RDdis)
/MEMRD
Tsu(D)
Write Data
SD[15:0](Dout)
DATA Valid
Symbol
Tsu(A)
Th(A)
Tw(WR)
Tw(RDdis)
Td(WtoR)
Tsu(D)
Th(D)
Th(D)
Description
Min
36
0.3
ADDRESS SETUP TIME
ADDRESS HOLD TIME
WRITE PULSE WIDTH
READ DISABLE PULSE WIDTH
WRITE TO READ DEALY
DATA SETUP TIME
DATA HOLD TIME
Typ.
*
*
-
1
16
0.3
Max
1
4.5
2
Units
ns
ns
ns
ns
ns
ns
ns
MEMORY READ
Tsu(A)
Th(A)
MEMA[15:1]
Referance
Internal
“/MEMRD”
Tw(RD)
( High Level )
/MEMWR
( Low Level )
/MEMRD
Tsu(RD)
Read Data
MEMD[15:1]
Symbol
Th(RD)
Valid DATA
Typ.
Max
Units
ns
1
ns
*
ns
3
ns
0
2
ns
* NOTE : The pulse width can be seen as LCLK/XTALIN high time. See also 6.4.1 “Thigh” parameter.
NOTE : All most any brand asynchronous SRAM access time under 20 ns can fit into the specification.
Tsu(A)
Th(A)
Tw(RD)
Tsu(D)
Th(D)
Description
Min
30
1.3
ADDRESS SETUP TIME
ADDRESS HOLD TIME
READ PULSE WIDTH
DATA SETUP TIME
DATA HOLD TIME
30
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
7.0 Package Information
He
A
A2
A1
L
L1
D
Hd
E
pin 1
e
b
θ
SYMBOL
MILIMETER
MIN.
NOM
A1
A2
MAX
0.1
1.3
1.4
A
1.5
1.7
b
0.155
0.16
0.26
D
13.90
14.00
14.10
E
13.90
14.00
14.10
e
0.40
Hd
15.60
16.00
16.40
He
15.60
16.00
16.40
L
0.30
0.50
0.70
L1
θ
1.00
0
10
31
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
Appendix A: Application Note 1
A.1 Using Crystal
AX88195
To PHY
CLKO25M
XTALIN
XTALOUT
25MHz
Crystal
8pf
2Mohm
8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please
refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator
AX88195
To PHY
CLKO25M
XTALIN
XTALOUT
NC
3.3V Power OSC 25MHz
32
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
A.3 Dual power (5V and 3.3V/3.0V) application
RJ45
MAGNETIC
+5V
+5V
+5V
PHY/TxRx
Optional
EEPROM
HVdd
+3.3V LVdd
AX88195
SRAM
+5V
+5V
+5V CPU I/F
A.4 Single power (3.3V/3.0V) application
RJ45
MAGNETIC
+3.3V
+3.3V
PHY/TxRx
Optional
EEPROM
+3.3V HVdd
+3.3V LVdd
AX88195
SRAM
+3.3V
+3.3V
+3.3V CPU I/F
33
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
A.5 Dual power (5V and 3.3V) application with 3.3V PHY
The 510 and 1K Ohm resisters are just for voltage adjustment
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
AX88195
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
510 ohm
34
1k ohm
PHY
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
Appendix B: Application Note 2
B.1 Advance Application for Using Crystal
Date: May 21, 1999
Condition: In short cable, AX88195 +AH 101 Phyceiver can’t link to BCM 5308
Switch.
Conclusion: 1. After measuring and verifying, we found it’s relevant to clock source.
2. We ascertain the problem is caused by matching issues between crystal
and capacitor.
Solution: Change the value of capacitors beside crystal as below:
Y1
XIN
XOUT
25MHZ
R4
2M
C22
18p
C23
18p
Note: The capacitors may be various depend on the specification of crystal. While
designing, please refer to the circuit provided by crystal supplier.
35
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
Appendix C: Application Note for RDY is not applicable
This application note is for some kind of CPU that doesn’t support asynchronous wait state insertion function.
For example, 8051 CPU series have only fix access cycle time. For some application that the CPU has the
capability of wait state insertion, but the designer do not want to use the handshake signal in order to simply the
design. This application note is helpful for those cases.
The following criteria must be meet:
1. The bus access timing must meet the AC timing specification.
2. The “remote DMA” move data from/to data port access time can’t faster than 120ns.
Solution:
Because of the access time from FIFO to Packet Buffer RAM or from Packet Buffer RAM to FIFO is
120ns/Word. The “remote DMA read” operation is the only case that RDY signal will be active to request some
wait state to pre-fetch data from RAM into FIFO. As soon as the first word of data feed into the FIFO, the RDY
will not active again for the lasting cycle. For the critical time, just insert “No Operation” instruction (to insert
wait state using software) after write remote DMA read command and before read data port.
Ex : IOBASE=300 ; Insert wait state by software.
Mov dx,308h
Mov al,0h
Out dx,al
Inc dx
Mov al,4dh
Out dx,al
Inc dx
Mov al,40h
Out dx,al
Inc dx
Mov al,40h
Out dx,al
Mov dx,300h
Mov al,0ah
Out dx,al
Nop
Nop
Mov dx,310h
Lea di, RxBuffer
Mov cx, RxLen
Rep insw
…
; Index = 308h
;
; Set Remote Start Address low byte = 0
; Index = 309h
;
; Set Remote Start Address high byte = 4d
; Index = 30Ah
;
; Set Remote DMA Byte Count low byte = 40h
; Index = 30Bh
;
; Set Remote DMA Byte Count high byte = 00h
; Index = 300h
;
; Set remote DMA read command
; Insert wait state here
; Insert more wait states again if necessary
; Index = 310h
; Set Rx Buffer Address
; Set Rx Length
; Read data port
36
ASIX ELECTRONICS CORPORATION
AX88195 Local CPU Bus Fast Ethernet MAC Controller
Errata of AX88195 V1
1. Interrupt Status can’t always clean up
Solution : Using software to do clean and check iteration until clean up.
Ex : IOBASE=300 ; Clear Tx/Rx interrupt.
Mov dx,307h
ClrISR :
ClrISRDone:
Mov al,3
Out dx,al
In al,dx
Test al,3
Jz ClrISRDone
Mov al,0
Out dx,al
Jmp ClrISR
…
; clear Tx/Rx interrupt
; output to clear ISR
; read ISR
; Check ISR cleared or not
; Clear ok
; if not, clear again
; clear successful
2. DTACK can’t fit 68K CPU timing in 68K mode
Solution : Using the DTACK automatic insertion function in 68K CPU.
37
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