ICST ICS85357AG-01T 4:1 or 2:1 differential-to-3.3v lvpecl / ecl clock multiplexer Datasheet

Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS85357-01 is a 4:1 or 2:1 Differential-to3.3V LVPECL / ECL clock multiplexer which can
HiPerClockS™ operate up to 750MHz and is a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS85357-01 has 4
selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The device can operate
using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or
3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully differential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors. Leaving one input unconnected
(pulled to logic low by the internal resistor) will transform
the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins
will select the same numbered data input (i.e., 00
selects CLK0, nCLK0).
• High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
,&6
• 1 differential 3.3V LVPECL output
• 4 selectable CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency up to 750MHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLKx input
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.5ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.135V to -3.465V
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK0
nCLK0
00
CLK1
nCLK1
01
CLK2
nCLK2
10
CLK3
nCLK3
11
VCC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
Q0
nQ0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
SEL1
SEL0
VCC
Q0
nQ0
VCC
nc
nc
VEE
ICS85357-01
20-Lead TSSOP
4.40mm x 6.50mm x 0.90mm body package
G Package
Top View
SEL1 SEL0
85357AG-01
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1
REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
1, 14,
17, 20
2
Name
3
4
Type
Description
VCC
Power
Positive supply pins. Connect to 3.3V.
CLK0
Input
Pulldown
nCLK0
Input
Pullup
CLK1
Input
Pulldown
5
nCLK1
Input
Pullup
6
CLK2
Input
Pulldown
7
nCLK2
Input
Pullup
8
CLK3
Input
Pulldown
9
nCLK3
Input
Pullup
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
10, 11
VEE
Power
12, 13
nc
Unused
No connect.
15, 16
nQ0, Q0
Output
Differential output pairs. LVPECL interface levels.
18
SEL0
Input
Pulldown
Clock select input. LVCMOS / LVTTL interface levels.
19
SEL1
Input
Pulldown
Clock select input. LVCMOS / LVTTL interface levels.
Negative supply pins. Connect to ground.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Input Capacitance
Minimum
Typical
CLK, nCLK,
CLK1, nCLK1,
CLK2, nCLK2,
CLK3, nCLK3
SEL0, SEL1
Maximum
Units
4
pF
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
85357AG-01
Clock Out
SEL1
SEL0
CLK
0
0
CLK0, nCLK0
0
1
CLK1, nCLK1
1
0
CLK2, nCLK2
1
1
CLK3, nCLK3
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2
REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
Outputs, VO
Package Thermal Impedance, θ JA
Storage Temperature, TSTG
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
VCC
Positive Supply Voltage
Test Conditions
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
35
mA
Maximum
Units
3.765
V
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
Test Conditions
Minimum
SEL0, SEL1
Typical
2
VIL
Input Low Voltage
SEL0, SEL1
IIH
Input High Current
SEL0, SEL1
VCC = VIN = 3.465V
-0.3
IIL
Input Low Current
SEL0, SEL1
VCC = 3.465V, VIN = 0V
0.8
V
150
µA
-5
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
IIH
Parameter
Input High Current
Test Conditions
CLK0, CLK1,
CLK2, CLK3
Minimum
Typical
VCC = VIN = 3.465V
nCLK0, nCLK1,
VCC = VIN = 3.465V
nCLK2, nCLK3
CLK0, CLK1,
-5
VCC = 3.465V, VIN = 0V
CLK2, CLK3
IIL
Input Low Current
nCLK0, nCLK1,
VCC = 3.465V, VIN = 0V
-150
nCLK2, nCLK3
Peak-to-Peak Voltage
0.15
VPP
Common Mode Input Voltage;
VCMR
VEE + 0.5
NOTE 1, 2
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
85357AG-01
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3
Maximum
Units
150
µA
5
µA
µA
µA
1.3
V
VCC - 0.85
V
REV. A JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCC - 1.4
VCC - 1.0
V
VCC - 2.0
VCC -1.7
V
0.6
0.85
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA=0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
750
MHz
IJ 750MHz
1
1.2
1.5
ns
fMAX
Maximum Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(pp)
Par t-to-Par t Skew; NOTE 2, 3
150
ps
tR
Output Rise Time
20% to 80% @50MHz
300
400
700
ps
tF
Output Fall Time
20% to 80% @50MHz
300
400
700
ps
odc
Output Duty Cycle
47
53
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
%
85357AG-01
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4
REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
Q0
LVPECL
VCC = 2.0V
nQ0
nQx
VEE = -1.3V ± 0.135V
FIGURE 1 - OUTPUT LOAD TEST CIRCUIT
V CC
CLKx
V
PP
Cross Points
V
CMR
nCLKx
VEE
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
85357AG-01
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REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
Q0
PART 1
nQ0
Q0
PART 2
nQ0
tsk(pp)
FIGURE 3- PART-TO-PART SKEW
80%
80%
V
20%
SWING
20%
Clock Inputs
and Outputs
t
t
R
FIGURE 4 - INPUT
AND
OUTPUT RISE
AND
F
FALL TIME
CLKx
nCLKx
Q0
nQ0
t
PD
FIGURE 5 - PROPAGATION DELAY
CLKx, Q0
nCLKx, nQ0
Pulse Width
t
t
odc =
t
PERIOD
PW
PERIOD
FIGURE 6 - odc & tPERIOD
85357AG-01
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REV. A JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 7 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 7 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
85357AG-01
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REV. A JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85357-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85357-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 35mA = 121.3mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 151.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.151W * 66.6°C/W = 80.06°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85357AG-01
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8
REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 8 - LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
)
OH_MAX
Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX)
L
•
For logic high, VOUT = V
OH_MAX
Using V
CC_MAX
•
OH_MAX
OL_MAX
CC_MAX
– 1.0V
CC_MAX
= 3.465, this results in V
For logic low, VOUT = V
Using V
=V
=V
CC_MAX
= 2.465V
– 1.7V
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85357AG-01
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REV. A JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85357-01 is: 400
85357AG-01
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REV. A JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS85357-01
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
A
MAX
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
85357AG-01
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REV. A JULY 16, 2001
ICS85357-01
Integrated
Circuit
Systems, Inc.
4:1 OR 2:1
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS85357AG-01
ICS85357AG-01
20 lead TSSOP
74 per tube
0°C to 70°C
ICS85357AG-01T
ICS85357AG-01
20 lead TSSOP on Tape and Reel
2500
0°C to 70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85357AG-01
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REV. A JULY 16, 2001
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