AD ADF4001 200 mhz clock generator pll Datasheet

a
200 MHz Clock Generator PLL
ADF4001
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware-Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead Chip Scale Package
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, and a programmable 13-bit N counter. In
addition, the 14-bit reference counter (R Counter) allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthesizer
is used with an external loop filter and VCO (Voltage Controlled
Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).
The N min value of 1 allows flexibility in clock generation.
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
ADF4001
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CP
CHARGE
PUMP
R COUNTER
LATCH
DATA
24-BIT
INPUT REGISTER
22
FUNCTION
LATCH
LE
CPI3 CPI2
SDOUT
CURRENT
SETTING 2
CURRENT
SETTING 1
LOCK DETECT
CLK
CPI1 CPI6 CPI5
CPI4
N COUNTER
LATCH
HIGH Z
AVDD
13
MUXOUT
MUX
RFINA
13-BIT
N COUNTER
RFINB
SDOUT
M3
CE
AGND
M2
M1
DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADF4001–SPECIFICATIONS1 (AV
DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =
CPGND = 0 V; RSET = 4.7 k; TA = TMIN to TMAX unless otherwise noted; dBm referred to 50 )
Parameter
B Version
Unit
RF CHARACTERISTICS (3 V)
RF Input Frequency
RF Input Sensitivity
5/165
–10/0
MHz min/max
dBm min/max
10/200
20/200
MHz min/max
MHz min/max
5/100
MHz min/max
REFIN Input Sensitivity2
–5
dBm min
REFIN Input Capacitance
REFIN Input Current
10
± 100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency3
55
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD – 0.4
0.4
V min
V max
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V
5.5
0.4
1
mA max
mA max
µA typ
4.5 mA typical
TA = 25°C
–161
–153
dBc/Hz typ
dBc/Hz typ
–99
dBc/Hz typ
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCXO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
–90/–95
dBc typ/dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
RF CHARACTERISTICS (5 V)
RF Input Frequency
REFIN CHARACTERISTICS
REFIN Input Frequency
POWER SUPPLIES
AVDD
DVDD
VP
IDD4 (AIDD + DIDD)
ADF4001
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor5
Phase Noise Performance6
200 MHz Output7
Spurious Signals
200 MHz Output7
Test Conditions/Comments
See Figure 3 for Input Circuit
–5/0 dBm min/max
–10/0 dBm min/max
See Figure 2 for Input Circuit
For f < 5 MHz, Use DC-Coupled Square Wave
(0 to VDD)
AC-Coupled. When DC-Coupled:
0 to VDD max (CMOS-Compatible)
Programmable: See Table V
With RSET = 4.7 kΩ
With RSET = 4.7 kΩ
See Table V
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
IOH = 500 µA
IOL = 500 µA
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 Evaluation Board and the HP8562E Spectrum Analyzer.
7
fREFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; f RF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
–2–
REV. 0
ADF4001
TIMING CHARACTERISTICS (AV
DD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V; RSET =
4.7 k; TA = TMIN to TMAX unless otherwise noted; dBm referred to 50 .)
Parameter
Limit at
TMIN to TMAX
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Set Up Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Set Up Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t3
t4
CLOCK
t1
DB20
(MSB)
DATA
t2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance (Paddle Soldered) . . . . 122°C/W
CSP θJA Thermal Impedance (Paddle Not Soldered) . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to + 0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . 150°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADF4001BRU
ADF4001BCP
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package*
RU-16
CP-20
*Contact factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADF4001
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I CP MAX =
2
CP
3
4
5
CPGND
AGND
RFINB
6
7
RFINA
AVDD
8
REFIN
9
10
DGND
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DVDD
16
VP
23.5
RSET
So, with RSET = 4.7 kΩ, ICP MAX = 5 mA.
Charge Pump Output. When enabled, this provides ± ICP to the external loop filter which, in turn, drives the
external VCO or VCXO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N Counter. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 3.
Input to the N Counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or can be
ac-coupled.
Digital Ground
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high will power up the device, depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high-impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high-impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5 V and used to drive a VCO or VCXO with a tuning range of up to 5 V.
RSET 1
16 VP
CP 2
CPGND 3
AGND 4
20 CP
19 RSET
18 VP
17 DVDD
16 DVDD
PIN CONFIGURATIONS
15 DVDD
ADF4001
14 MUXOUT
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
13 LE
RFINA 6
11 CLK
AVDD 7
10 CE
REFIN 8
9 DGND
ADF4001
TOP VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
AVDD 6
AVDD 7
REFIN 8
DGND 9
DGND 10
TOP VIEW
RFINB 5 (Not to Scale) 12 DATA
PIN 1
INDICATOR
TRANSISTOR COUNT
6425 (CMOS) and 50 (Bipolar).
–4–
REV. 0
Typical Performance Characteristics–ADF4001
10dB/DIVISION
–40
0
RL = –40dBc/Hz
rms NOISE = 0.229 DEGREES
–50
0.229 rms
–5
PHASE NOISE – dBc/Hz
–60
AMPLITUDE – dBm
–10
–15
TA = +85C
–20
TA = +25C
–25
–70
–80
–90
–100
–110
–120
–30
–130
TA = –40C
–140
100
–35
0
50
100
150
FREQUENCY – MHz
200
250
TPC 1. Input Sensitivity. VDD = 3.3 V; 100 pF on RFIN
1k
10k
100k
FREQUENCY OFFSET FROM 200MHz CARRIER – Hz
TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)
0
0
–10
–5
–20
OUTPUT POWER – dB
AMPLITUDE – dBm
1M
–10
–15
–20
REFERENCE LEVEL =
–5.7dBm
–30
–40
VDD = 3V, VP = 5V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 300Hz
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2 SECONDS
AVERAGES = 20
–50
–60
–70
–92.3dBc
–80
–25
–90
–30
5
0
10
15
FREQUENCY – MHz
20
–100
25
–200kHz
0
OUTPUT POWER – dB
–20
REFERENCE LEVEL =
–5.7dBm
–30
–40
VDD = 3V, VP = 5V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 26
–50
–60
–70
–99.2dBc/Hz
–80
–90
–100
–2kHz
–1kHz
200MHz
1kHz
2kHz
0
TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)
REV. 0
200MHz
100kHz
200kHz
0
TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)
TPC 2. Input Sensitivity. VDD = 3.3 V; 100 pF on RFIN
–10
–100kHz
–5–
ADF4001
FROM
N COUNTER LATCH
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO PFD
Figure 4. N Counter
R Counter
POWER-DOWN
CONTROL
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
NC
100k
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
SW2
REFIN
13-BIT N
COUNTER
FROM RF
INPUT STAGE
NC
BUFFER
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic. The
PFD includes a programmable delay element which controls the
width of the antibacklash pulse. This pulse ensures that there is
no deadzone in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the Reference Counter
Latch, ABP2 and ABP1 control the width of the pulse. See
Table III.
TO
R COUNTER
SW1
SW3
NO
Figure 2. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N Counter buffer.
VP
HI
D1
UP
U1
1.6V
BIAS
GENERATOR
Q1
CHARGE
PUMP
R DIVIDER
CLR1
AVDD
2k
2k
DELAY
CP
U3
RFINA
RFINB
CLR2
HI
N DIVIDER
D2
Q2
DOWN
U2
CPGND
AGND
Figure 3. RF Input Stage
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
R DIVIDER
N DIVIDER
N and R Relationship
CP OUTPUT
The N counter, in conjunction with the R Counter make it
possible to generate output frequencies that are spaced only by
the Reference Frequency divided by R. The equation for the
VCO frequency is as follows:
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
fVCO = N/R × fREFIN
fVCO
Output Frequency of external voltage-controlled oscillator (VCO).
N
Preset Divide Ratio of binary 13-bit counter (1 to 8,191).
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
fREFIN External reference frequency oscillator.
R
Preset divide ratio of binary 14-bit programmable reference counter (1 to 16,383).
–6–
REV. 0
ADF4001
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.
DVDD
ANALOG LOCK DETECT
INPUT SHIFT REGISTER
DIGITAL LOCK DETECT
CONTROL
MUX
The ADF4001 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs DB1,
DB0 as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a summary of how the latches are programmed.
MUXOUT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
DGND
Figure 6. MUXOUT Circuit
Table I. C2, C1 Truth Table
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to “0,” digital
lock detect is set high when the phase error on three consecutive
Phase Detector cycles is less than 15 ns. With LDP set to “1,” five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
Control Bits
C2
C1
Data Latch
0
0
1
1
R Counter
N Counter
Function Latch
Initialization Latch
0
1
0
1
Table II. ADF4001 Family Latch Summary
LOCK
DETECT
PRECISION
REFERENCE COUNTER LATCH
RESERVED
DB23 DB22
X
X
TEST
MODE
BITS
DB21
DB20
DB19
X
LDP
T2
ANTIBACKLASH
WIDTH
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
T1
ABP2
ABP1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
DB3
DB2
DB1
DB0
R2
R1
C2 (0) C1 (0)
N -COUNTER
RESERVED
CP
GAIN
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
G1
N13
N12
N11
N10
N9
N8
X
X
13-BIT N COUNTER
DB14
N7
DB13
N6
CONTROL
BITS
RESERVED
DB12
DB11
DB10
DB9
DB8
N5
N4
N3
N2
N1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
FUNCTION LATCH
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
CONTROL
BITS
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB0
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
INITIALIZATION LATCH
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (1)
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
X = DON’T CARE
REV. 0
–7–
MUXOUT
CONTROL
DB0
ADF4001
LOCK
DETECT
PRECISION
Table III. Reference Counter Latch Map
RESERVED
DB23 DB22
X
X
ANTIBACKLASH
WIDTH
TEST
MODE
BITS
DB21
DB20
DB19
X
LDP
T2
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
T1
ABP2
ABP1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
DB3
DB2
DB1
DB0
R2
R1
C2 (0) C1 (0)
X = DON’T CARE
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
0
1
1
0
.
.
.
0
1
0
1
0
.
.
.
0
1
2
3
4
.
.
.
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
ABP2
ABP1
ANTIBACKLASH PULSEWIDTH
0
0
1
1
0
1
0
1
2.9ns
1.3ns
6.0ns
2.9ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP
OPERATION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
–8–
REV. 0
ADF4001
RESERVED
CP GAIN
Table IV. N Counter Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
G1
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
X
X
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
C2 (0)
C1 (1)
X = DON’T CARE
N13
N12
N11
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
0
0
0
0
.
.
.
1
1
1
1
1
1
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
0
0
0
1
1
0
1
1
N3
N2
N1
N COUNTER DIVIDE RATIO
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
.
.
1
0
1
1
0
.
.
.
0
1
0
1
0
.
.
.
0
1
2
3
4
.
.
.
8188
1
..........
1
0
1
8189
1
..........
1
1
0
8190
1
..........
1
1
1
8191
OPERATION
CHARGE PUMP CURRENT SETTING
1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON’T CARE BITS.
REV. 0
CONTROL
BITS
RESERVED
13-BIT N COUNTER
–9–
ADF4001
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
Table V. Function Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
X
X
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB0
X = DON’T CARE
F2
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
F3
CHARGE PUMP OUTPUT
0
NORMAL
1
THREE-STATE
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TC4
TC3
TC2
TC1
TIMEOUT
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
CPI6
CPI5
CP14
CPI3
CPI2
CPI1
2.7k
4.7k
10k
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.088
2.176
3.264
4.352
5.44
6.528
7.616
8.704
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
0.294
0.588
0.882
1.176
1.47
1.764
2.058
2.352
F1
0
1
COUNTER
OPERATION
NORMAL
R, N COUNTER
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
AVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ICP (mA)
CE PIN
PD2
PD1
MODE
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
–10–
REV. 0
ADF4001
RESERVED
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PHASE
DETECTOR
POLARITY
POWERDOWN 1
COUNTER
RESET
Table VI. Initialization Latch Map
DB23 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
TC4
TC3
TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
X
X
CURRENT
SETTING
1
CURRENT
SETTING
2
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB0
X = DON’T CARE
F2
0
1
REV. 0
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
TIMEOUT
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
CPI6
CPI5
CP14
CPI3
CPI2
CPI1
2.7k
4.7k
10k
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.088
2.176
3.264
4.352
5.44
6.528
7.616
8.704
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
0.294
0.588
0.882
1.176
1.47
1.764
2.058
2.352
ICP (mA)
PD1
MODE
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
THREE-STATE
F5
TC1
X
X
0
1
NORMAL
1
X
0
1
TC2
PD2
CHARGE PUMP OUTPUT
0
0
1
1
TC3
0
1
1
1
F3
F4
TC4
CE PIN
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
–11–
F1
0
1
COUNTER
OPERATION
NORMAL
R, N COUNTER
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
AVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
ADF4001
THE FUNCTION LATCH
The device enters Fastlock by having a “1” written to the CP
Gain bit in the N counter latch. The device exits Fastlock by
having a “0” written to the CP Gain bit in the AB counter latch.
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming
the Function Latch.
Fastlock Mode 2
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,
the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device powers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”
In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a “1” into bit
PD1 (on condition that a “1” has also been loaded to PD2), the
device will go into power-down on the occurrence of the next
charge pump event.
When a power-down is activated (either synchronous or
asynchronous mode, including CE-pin-activated power-down),
the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the N counter latch. The device exits Fastlock under
the control of the Timer Counter. After the timeout period
determined by the value in TC4–TC1, the CP Gain bit in the
N counter latch is automatically reset to “0” and the device
reverts to normal mode instead of Fastlock. See Table V for
the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that the Current Setting 1 is used when
the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed).
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as Current Setting 2.
At the same time they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the Function Latch. The truth
table is given in Table V.
Now, when the user wishes to program a new output frequency,
they can simply program the N counter latch with new value for N.
At the same time they can set the CP Gain bit to a “1,” which sets
the charge pump with the value in CPI6–CPI4 for a period of
time determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time the CP Gain bit in the N Counter latch is reset to 0
and is now ready for the next time that the user wishes to change
the frequency.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4001. Table V shows the truth table.
Charge Pump Currents
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
Fastlock Mode Bit
PD Polarity
DB10 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0,” Fastlock Mode 1 is selected;
if the Fastlock Mode bit is “1, ”Fastlock Mode 2 is selected.
This bit sets the PD Polarity Bit. See Table V.
Fastlock Enable Bit
CP 3-State
This bit sets the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP
output is enabled.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
–12–
REV. 0
ADF4001
THE INITIALIZATION LATCH
The Counter Reset Method
When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
Apply VDD.
However, when the Initialization Latch is programmed, there is
an additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at load point when the
N counter data is latched, and the device will begin counting in
close phase alignment.
Do an R Counter Load (“00” in 2 LSBs).
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The oscillator input buffer is
unaffected by the internal reset pulse, and so close phase alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply VDD.
Program the Initialization Latch (“11” in 2 LSBs of input word).
Make sure that F1 bit is programmed to “0.”
Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “1” to the F1 bit. This enables the counter reset.
Do an N Counter Load (“01” in 2 LSBs).
Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “0” to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
APPLICATIONS SECTION
Extremely Stable, Low Jitter Reference Clock for GSM Base
Station Transmitter
Figure 7 shows the ADF4001 being used with a VCXO to produce an extremely stable, low jitter reference clock for a GSM
base station Local Oscillator (LO).
13MHz
SYSTEM
CLOCK
1
13MHz
R DIVIDER
CHARGE
PUMP
PFD
Then do an R load (“00” in 2 LSBs).
CP
LOOP
FILTER
VCXO
1
Then do an N load (“01” in 2 LSBs).
RFIN
N DIVIDER
When the Initialization Latch is loaded, the following occurs:
ADF4001
1. The function latch contents are loaded.
2. An internal pulse resets the R, N, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.
The CE Pin Method
Apply VDD.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10).
Program the R Counter Latch (00).
Program the N Counter Latch (01).
Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
REV. 0
REFIN CP
LOOP
FILTER
VCO
RFIN
ADF4110
ADF4111
ADF4112
ADF4113
RFINA
Figure 7. Low Jitter, Stable Clock Source for GSM Base
Station Local Oscillator cct
The system reference signal is applied to the circuit at REFIN.
Typical GSM systems would have a very stable OCXO as the
clock source for the entire base station. However, distribution of
this signal around the base station makes it susceptible to
noise and spurious pickup. It is also open to pulling from the
various loads it may need to drive.
The charge pump output of the ADF4001 (Pin 2) drives the
loop filter and the 13 MHz VCXO. The VCXO output is fed
back to the RF input of the ADF4001 and also drives the reference (REFIN) for the LO. A T-circuit configuration provides
50 Ω matching between the VCXO output, the LO REFIN, and
the RFIN terminal of the ADF4001.
COHERENT CLOCK GENERATION
When testing A/D converters, it is often advantageous to use a
coherent test system, that is a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
–13–
ADF4001
function. Figure 8 shows how the ADF4001 can be used to
handle all the possible combinations of input signal frequency
and sampling rate. The first ADF4001 is phase locked to a
VCO. The output of the VCO is also fed into the N divider of
the second ADF4001. This results in both ADF4001’s
being coherent with the REFIN. Since the REFIN comes from
the signal generator, the MUXOUT signal of the second
ADF4001 is coherent with the FIN frequency to the ADC. This is
used as FS, the sampling clock.
FS = (FIN N1)/(R1 N2)
AIN
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
4
ADF4001
CPRF
N1
LOOP
FILTER
RFIN
N1
REFIN
19.44MHz SYSTEM
CLOCK FOR WCDMA
R2
1300
CPRF
52MHz
MASTER
CLOCK
A/D
CONVERTER
UNDER
TEST
VCXO
19.44MHz
LOOP
FILTER
RFIN
486
N2
ADF4001
FS
R1
VCXO
13MHz
LOOP
FILTER
ADF4001
SAMPLING
CLOCK
REFIN
CPRF
1
FIN
SINE
OUTPUT
13MHz SYSTEM
CLOCK FOR GSM
R1
REFIN
19.2MHz SYSTEM
CLOCK FOR CDMA
R3
REFIN
65
CPRF
VCO
100MHz
RFIN
VCXO
19.2MHz
LOOP
FILTER
RFIN
24
N3
N2
ADF4001
RFIN
Figure 9. Tri-Band System Clock Generation
NC7S04
MUXOUT
VP
ADF4001
Figure 8. Coherent Clock Generator
POWER-DOWN CONTROL
TRI-BAND CLOCK GENERATION CIRCUIT
In multi-band applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz Master Clock. The low RF
Fmin spec and the ability to program R and N values as low as
1 makes the ADF4001 suitable for this. Other FOUT clock
frequencies can be realized using the formula:
FOUT = REFIN ∗ ( N ÷ R )
S
VDD
VDD
RFOUT
IN
ADG702
D
15
7
16
10
AVDD DVDD VP
CE
CP
FREFIN
RSET
GND
100pF
18
VCC
2
LOOP
FILTER
1
10k
100pF 18
VCO
OR
VCXO
18
GND
ADF4001
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic “1” is applied to the IN input.
The low-cost switch is available in both SOT-23 and micro
SO packages.
100pF
RFINA 6
51
RFINB
CPGND AGND DGND
3
4
9
5
100pF
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
Figure 10. Local Oscillator Shutdown Circuit
–14–
REV. 0
ADF4001
INTERFACING
ADSP-2181 Interface
The ADF4001 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA, and LE control
the data transfer. When LE (Latch Enable) goes high, the 24
bits that have been clocked into the input register on each rising
edge of SCLK will be transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
Figure 12 shows the interface between the ADF4001 family and
the ADSP-21xx Digital Signal Processor. The ADF4001 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate
Framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the Autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz or one update every 1.2 ms. This is certainly more
than adequate for systems with typical lock times in hundreds
of microseconds.
ADuC812 Interface
Figure 11 shows the interface between the ADF4001 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4001 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
SCLK
DT
TFS
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will
be 166 kHz.
ADF4001
ADuC812
SCLOCK
MOSI
SCLK
SDATA
LE
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
Figure 11. ADuC812 to ADF4001 Family Interface
REV. 0
SCLK
SDATA
LE
CE
I/O FLAGS
On first applying power to the ADF4001 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
ADF4001
ADSP-21xx
MUXOUT
(LOCK DETECT)
Figure 12. ADSP-21xx to ADF4001 Family Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip package (CP-20) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package land length and 0.05 mm wider than the
package land width. The land should be centered on the pad.
This will ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edge of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
–15–
ADF4001
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink SO Package (TSSOP)
(RU-16)
16
C02569–1–7/01(0)
0.201 (5.10)
0.193 (4.90)
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8
0
0.028 (0.70)
0.020 (0.50)
20-Leadless Frame Chip Scale Package (LFCSP)
(CP-20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
16
0.009 (0.24)
15
0.157 (4.0)
BSC SQ
TOP
VIEW
0.148 (3.75)
BSC SQ
0.031 (0.80) MAX
0.026 (0.65) NOM
12 MAX
0.035 (0.90) MAX
0.033 (0.85) NOM
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.022 (0.60)
0.014 (0.50)
20
1
0.080 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
BOTTOM
VIEW
11
10
6
5
0.080 (2.00)
REF
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
PRINTED IN U.S.A.
PIN 1
INDICATOR
0.010 (0.25)
MIN
–16–
REV. 0