MSK MSK5061RH Rad hard low voltage 10a switching regulator with current share Datasheet

MIL-PRF-38534 AND 38535 CERTIFIED FACILITY
RAD HARD
LOW VOLTAGE
10A SWITCHING REGULATOR
WITH CURRENT SHARE
5061RH
FEATURES:
•
•
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•
•
•
•
•
•
•
Radiation Hardened to 100Krad, High and Low Dose Rates
Exceptional SEE Performance
TOR Ready, Designed and Derated to MIL-STD-1547B and NASA EEE-INST-002
Integrated Inductor
Adjustable 0.6V to 4.0V Output, Greater than 10A
2 Phase Current Sharing Mode Enables Output Current in Excess of 20A
Adjustable Frequency and Synchronization for Sensitive Applications
Soft-Start, Logic Level Enable, PGOOD Flag, and Power On Reset Features Simplify Sequencing
Simple Heat Sinking; Low Thermal Resistance, Pin Connected Case
Contact MSK for MIL-PRF-38534 Qualification and RHA Status
DESCRIPTION:
The MSK5061RH is a radiation hardened adjustable output switching voltage regulator. The wide input and output range, output current in excess of
10A, and full complement of features defines this regulator as an ideal solution for many space power applications. Designed specifically for the cutting
edge low voltage/high current FPGA & ASIC technologies, two MSK5061RH can be operated in 2 phase current sharing mode to deliver output currents
in excess of 20A accross the full output range. The robust integrated inductor and passives significantly reduce design time and board area. All internal
components have been designed to satisfy even the most stringent reliability requirements, mitigating program design-in risks. The MSK5061RH is hermetically sealed in a 50 pin flatpack.
EQUIVALENT SCHEMATIC
1
PRELIMINARY Rev. B 3/15
TYPICAL APPLICATIONS
PIN-OUT INFORMATION
• Low Voltage High Current Point of Load Regulation
• High Efficiency Satellite and space craft power supply
• High power FPGA, ASIC, µP, & Analog POL
ABSOLUTE MAXIMUM RATINGS
VIN
IOUT
TC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VIN1
VIN2
VIN3
VIN4
VIN5
ISHA
ISHREFA
ISHB
ISHREFB
ISHC
ISHREFC
SS
PGOOD
ISHCOM
ISHSL
ISHEN
PORSEL
SYNC
M/S
FSEL
VIN6
VIN7
VIN8
VIN9
VIN10
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGND1/CASE
PGND2
PGND3
PGND4
PGND5
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
PGND6
PGND7
PGND8
PGND9
PGND10
AGND
EN
REF
FB
6
Supply Voltage ...................................................6.2V
8
Output Current.....................................................12A
Case Operating Temperature Range
MSK5061K/HRH............................-55°C to +125°C
MSK5061RH....................................-40°C to +85°C
TST
TLD
TJ
2
Storage Temperature Range............-65°C to +150°C
Lead Temperature Range
(10 Seconds)....................................................300°C
Junction Temperature.......................................150°C
ESD Rating....................................................Class 2
PRELIMINARY Rev. B 3/15
ELECTRICAL SPECIFICATIONS
NOTES:
1
2
3
4
5
6
7
8
Unless otherwise specified VIN=5.5V, VOUT=1.5V, IOUT =5A, 1MHz, current share disabled.
Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only.
Industrial grade devices shall be tested to subgroup 1 and 4 unless otherwise specified.
Military and space grade devices (‘H’ and ‘K’ suffix) shall be 100% tested to Subgroups 1,2,3 and 4.
Subgroup 5 and 6 testing available upon request.
Subgroup 1, 4, 7
TA = TC = +25°C
Subgroup 2, 5, 8A TA = TC = +125°C
Subgroup 3, 6, 8B TA = TC = -55°C
Continuous operation at or above absolute maximum ratings may adversely effect the device performance and/or life cycle.
Pre and post irradiation limits @ 25°C, up to 100Krad TID, are identical unless otherwise specified.
Absolute maximum output current rating is subordinate to the “RMS output current vs case temperature” SOA curve on sheet 9.
3
PRELIMINARY Rev. B 3/15
APPLICATION NOTES
PIN FUNCTIONS
VIN – The VIN pins are the input supply pins for all of
the internal circuitry. High di/dt switching currents are
conducted through these pins. Locally decouple VIN to
PGND with a mix high frequency ceramic capacitors and
low ESR tantalum. Provide sufficient bulk capacitance
to ensure a low impedance buss and limit input voltage
ripple.
FSEL – The FSEL pin is used to program the Switching
frequency of the MSK5061RH. Connect to VIN for 1MHz
or to PGND for 500KHz operation.
PORSEL – The PORSEL pin is used to program the power
on reset thresholds of the MSK5061RH. Connect to VIN
for a 5V nominal input bus, or PGND for a 3.3V nominal
input bus. Connect to PGND for a input bus that varies
from 3V to 5.5V.
PGND – The PGND pins connect to the internal power
ground plane. High di/dt switching currents are conducted through these pins. Provide a continuous low impedance ground path between the MSK5061RH PGND, the
input supply return, and the load. Avoid layouts that force
load return current to cross the AGND reference path.
SS – The Soft Start pin provides control of turn on surge
currents and enables coincident or ratiometric tracking
functionality. A 23µA current source charges the internal
SS capacitor and sets the output ramp rate to approximately 2.6mS. Connect additional capacitance to reduce
the output ramp rate. In 2 phase current sharing applications, the slave ramp rate should be at least twice that of
the master. Further application guidance is provided in the
Start Up Considerations section.
VOUT – The VOUT pins are connected to the internal
output inductor. Connect VOUT as close as possible to
the load to minimize bus impedance. Connecting 500 to
1000µF low ESR bulk capacitance to VOUT is typically sufficient to ensure stable operation. Some ceramic
capacitance near the load is typically required to roll off
high frequency gain, suppress switching noise and fast
load transients. A mix of high frequency ceramic capacitors and low ESR tantalum are recommended. See Output Capacitor Selection paragraph.
EN – The EN pin provides hysteretic on/off control of the
regulator. Driving this pin above 0.6V enables the regulator. Programmable hysteresis is realized with an 11µA current sink that is active until the pin voltage exceeds VREF.
Bypass with a capacitor to ground when controlling from a
high impendence source. See the applications section for
further guidance.
AGND – The AGND pin provides a low noise signal reference for the internal control circuitry. For optimum regulation performance, connect AGND and PGND together
near the ground side of the load.
PGOOD – The PGOOD pin is a high impedance logic output that is pulled low when the regulators output voltage is
outside of a ±11% typical window. This status flag can be
used for supply sequencing and fault detection.
PGND1/CASE – This pin is electrically connected to the
MSK5061RH case and PGND.
M/S – The M/S input pin determines the function of the
bidirectional SYNC pin. Connect M/S to VIN for Master
mode, where the SYNC pin is the master oscillator output.
Connect M/S to PGND for Slave mode, where SYNC becomes an input.
FB – The FB pin is the inverting input to the error amplifier. The voltage at this pin and the 0.6V reference voltage are used to servo to current control loop set point.
Place a resistor divider between VOUT and AGND near
the load, and connect the FB pin to the center node to
program the output voltage. See Output Voltage Selection paragraph.
SYNC – When SYNC is configured as an output, M/S = VIN,
this pin drives the SYNC pin input of another MSK5061RH
with a square wave that is phase shifted ≈180° from the
Master clock driving the Master PWM circuits. When configured as an input, M/S = PGND, this pin uses the SYNC
output from another MSK5061RH or an external clock to
clock the PWM circuitry. If synchronizing to an external
clock, the clock must be SEE hardened and the frequency
must be within the range of 400kHz to 1.2MHz.
REF – The REF pin is the internal 0.6V reference voltage
used in several circuit functions. The reference voltage is
pined out for current sharing applications. When applying the 2 phase current sharing functionality, connect the
REF pins of the master and slave MSK5061RHs through
a 10Ω resistor. This pin must not be otherwise loaded.
4
PRELIMINARY Rev. B 3/15
APPLICATION NOTES CONT’D
PIN FUNCTIONS
POWER SUPPLY BYPASSING
ISHEN – The ISHEN pin enables the current sharing feature. Connect to VIN to enable current sharing functions.
Connect to PGND to disable the current sharing features.
Current is drawn from the input bus in roughly trapezoidal
pulses with very fast edge rates, and consequently consists
of a broad frequency spectrum. High quality low ESR/ESL
ceramic capacitors connected directly across the VIN and
PGND pins are recommended to provide a low impedance
to the high frequency components of the wave form and
trap them local to the regulator, thereby limiting conducted
EMI. Minimizing the area of the VIN-CIN-PGND loop will
help minimize radiated EMI. The MSK5061RH simplifies
application with the inclusion of significant internal ceramic capacitance. The internal and external input capacitors
source the AC component of the switched current into the
regulator. The RMS ripple current seen by the input capacitors is high, approaching a maximum of 0.5 x Iout at
approximately 50% duty cycle. Sufficient bulk capacitance
must be provided to minimize ripple voltage seen by the
device and ensure stable operation. As a general rule of
thumb, VIN ripple should be less than 3 to 5% of VIN. Selection of the bulk input capacitors will likely involve a parallel combination of several tantalum and ceramics to allow
proper voltage and ripple current derating. Satisfying those
requirements will almost invariably result in sufficient bulk
to minimize ripple voltage and ensure stable operation.
ISHSL – The ISHSL pin configures the MSK5061RH as either a current share master or slave. Connect to PGND to
configure the device as a master or if current sharing functions are not implemented. Connect to VIN to configure the
MSK5061RH as a current share slave device.
ISHCOM – ISHCOM is a bidirectional communication line
between a current share Master and a current share Slave.
If using current share, tie ISHCOM of the Master to ISHCOM of the Slave. The Master enables the Slave by resistively (~ 8.5kΩ) pulling ISHCOM high. The Slave indicates
an over-current fault condition to the Master by pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PWB ground plane. If not using
current share this pin should be floated or connected to the
PCB ground plane. ISHCOM is tri-stated if ISHEN is low.
ISHREFA, B, C - If configured as a current share Master
the ISHREFA/ISHREFB/ISHREFC pins provide a reference output current equal to 100μA each. If configured as
a current share Slave, the ISHREFA/ISHREFB/ISHREFC
pins accept a reference input current. For a current share
Slave, this input current is used together with the ISHA/
ISHB/ISHC current to determine the Master’s redundant
A/B/C error amp output current. If using current share, tie
ISHREFA/ISHREFB/ISHREFC of the MASTER to ISHREFA/ISHREFB/ISHREFC of the Slave. If not using current
share, tie ISHREFA/ISHREFB/ISHREFC to VIN. The purpose of the reference current is to reduce the impact of
external noise coupling onto ISHA/ISHB/ISHC. ISHREFA/
ISHREFB/ISHREFC are tri-stated prior to a valid POR and
when ISHEN = PGND.
OUTPUT CAPACITOR SELECTION
When operated at 1MHz, 500uF total of low ESR capacitance mounted near the MSK5061RH have been shown
to provide good stability margins. However physical and
practical realities may necessitate at least some bypass
capacitance local to the load. The capacitor parasitic ESR
and ESL, the non-zero impedance between the regulator
output and the load terminals, and finite bandwidth will
cause a transient voltage signal to develop proportional to the magnitude of the load step. Additional low ESR
output capacitance can help mitigate the transient voltage
excursions. Care should be exercised in capacitor selection such that the loop maintains adequate stability margin.
Additional output capacitance will be required to lower the
loop bandwidth and improve stability margins if operating at
switch frequencies below 750kHz. Adding 220µF to 330µF
is typically a sufficient adjustment for this scenario. See the
typical performance curves for addition information.
ISHA, B, C – If configured as a current share Master, the
ISHA/ISHB/ISHC pins are outputs that provide a current
equal to 25 times the redundant A/B/C error amp output
currents plus ISHREFA/ISHREFB/ISHREFC (nominally
100μA each). If configured as a current share Slave, the
ISHA/ISHB/ISHC pins are inputs that become the Slave’s
redundant A/B/C error amp output current. If using current
share, tie ISHA/ISHB/ISHC of the Master to ISHA/ ISHB/
ISHC of the Slave. If not using current share, tie ISHA/
ISHB/ISHC to DVDD. ISHA/ISHB/ISHC are tri-stated prior
to a valid POR and when ISHEN = PGND.
5
PRELIMINARY Rev. B 3/15
APPLICATION NOTES CONT’D
OUTPUT VOLTAGES SELECTION
The output voltage is governed by the following equation:
VOUT=VREF x
VENABLE=
1 + R1
R2
(
VREF x 1+
RT
RB
VDISABLE= VREF x 1 +
Solving for R1:
R1 = R2 x VOUT -1
VREF
)
+ IEN x RT
RT
RB
ENHYST= VENABLE - VDISABLE
Resistors in the 1KΩ to 5KΩ range are typically used to minimize power and leakage current effects. Some loop compensation can be achieved by placing R –C networks in
parallel with either R1 and/or R2. Any compensation efforts
should be verified by analysis and measurement.
Once the POR and EN thresholds have been satisfied, a
soft start cycle will be initiated. The Soft Start circuit limits
the surge current drawn to charge the output capacitors by
controlling the ramp rate of the output voltage. This feature
can also be exploited to implement coincident and ratiometric tracking supplies required by many cutting edge digital
systems. During start up the error amplifier reference voltage is clamped to the SS pin while a 23µA current source
charges the SS pin capacitor. The soft start ramp rate can
be adjusted over a range of 2.6ms to 214ms. Determine the
desired ramp rate and use the following equation to select
the corresponding soft start capacitor.
START UP CONSIDERATION; POR, EN, SS
AND PGOOD
The input of any buck switching regulator exhibits a negative
input resistance; i.e. as input voltage decreases the input
current increases. Also the current required to charge the
output capacitors is proportional to the total output capacitance and the rate at which the output voltage is allowed to
rise. At start up a lockup condition can occur in intermediate power systems not designed specifically to handle these
additional currents. Further complicating matters is the fact
many FPGA, ASIC, and µProcessor place strict constraints
on the rise time and sequence of supply rail voltages. The
MSK5061RH has several features specifically designed to
simplify managing these challenges.
CSSEXT=
TSS x ISS
VREF
- 0.1uF
Once the SS pin voltage equals the reference voltage, the
clamp is released and the SS pin voltage continues to rise to
≈1.4V. Once the SS pin reaches 1.4V and the output voltage
is with ≈±10% of the set point, the PGOOD pin will transition
to the high state. After an over current or under voltage fault,
the SS pin is discharged through a 2.2Ω nominal resistance.
The Power On Reset function prevents the MSK5061RH
from initiating the soft start cycle until VIN has risen above
the threshold determined by the PORSEL pin strap. Review
the Electrical Specifications Table and the pin functional
description for guidance in selecting the appropriate POR
threshold for your application.
SYNCHRONIZATION
The MSK5061RH can be externally synchronized to an external clock in the range of 400kHz to 1.2MHz. This gives
designers of precision systems the ability to steer switching
noise away sensitive bands, reduce supply ripple current,
and eliminate power supply beat frequencies generated by
multiple free running switching regulators. To synchronize
the MSK5061RH to another MSK5061RH simply connect
the M/S pins of the master and slave devices to VIN and
PGND respectively and directly connect the SYNC pins.
Similarly one or more MSK5061RH can be synchronized to
a RAD HARD clock generator.
The EN pin enables the regulator output when driven above
VREF, providing a convenient means for implementing supply sequencing. Noise immunity is afforded by the user programmable EN pin Hysteresis. Connect the control signal to
EN through a resistor divider. An 11µA current source is active until the EN pin voltage crosses 0.6V, creating the upper
bound of the hysteresis loop. The current source is disabled
once EN exceeds 0.6V, establishing the lower bound of the
hysteresis loop. Use the following equations to define the
EN pin thresholds and hysteresis.
6
PRELIMINARY Rev. B 3/15
APPLICATION NOTES CONT’D
CURRENT SHARING
Two MSK5061RH can be configured together in a robust fault tolerant two phase supply
with current capacity in excess of 20A. In this
mode, a redundant Current Sharing bus balances the load current between the two devices and communicates any fault conditions.
One MSK5061RH is designated the Master
and the other the Slave. The Master ISHSL pin
is connected to PGND and the Slave ISHSL
pin is connected to VIN. The ISHEN pins on
both Master and Slave are connected to VIN.
The SYNC, ISHA, ISHB, ISHC, ISHREFA,
ISHREFB, ISHREFC, ISHCOM and FB pins
are connected from the Master to the Slave
and the REF pins are tied with a 10Ω resistor.
Configured this way, the 2 phase current regulator nearly doubles the load current capacity,
limited only by the Current Share Match tolerance. In this Master/Slave configuration the
MSK5061RH operate 180° out-of-phase to
minimize the input ripple current, effectively
operating as a single IC at twice the switching frequency. Also under idealized conditions
the output ripple voltage terms can completely
cancel producing a comparatively quite supply
rail over a broad band. The Master phase uses
the falling edge of the SYNC clock to initiate
the Master switching cycle with the non-overlap period before the rising edge of LX, while
the Slave phase internally inverts the SYNC
input and uses the falling edge of the inverted copy to start it’s switching cycle. This is
independent of whether the Master phase is
configured for an external clock (Master M/S
= PGND) or its internal clock (Master M/S =
VIN). The Master Error Amplifier and Compensation controls the two phase regulator while
the Slave Error Amplifier is disabled.
TYPICAL APPLICATION CIRCUIT
TYPICAL APPLICATON CIRCUIT, CURRENT SHARING
TOTAL DOSE RADIATION TEST
PERFORMANCE
Radiation performance curves for TID testing will be generated for all radiation testing
performed by MS Kennedy. These curves
show performance trends throughout the
TID test process and can be located in the
MSK5061RH radiation test report. The complete test report will be available in the RAD
HARD PRODUCTS section of the MSK website.
7
PRELIMINARY Rev. B 3/15
TYPICAL PERFORMANCE CURVES
OVER CURRENT REFERENCE VOLTAGE vs Tc
EFFICIENCY vs LOAD CURRENT
600
100%
599.5
95%
90%
598.5
OCB
OCA
597.5
80%
597
75%
596.5
70%
596
-55
-35
-15
5
25
45
Temperature (°C)
65
85
105
PRELIMINARY
85%
65%
125
0
1
2
REFERENCE VOLTAGE vs Tc
Percent of Maximum Rated Output Current
601.5
VREF (mV)
601
600.5
600
599.5
599
598.5
598
-35
-15
5
25
45
Temperature (°C)
65
85
105
Gain (db)
SWITCHING FREQUENCY (kHz)
975
950
925
PRELIMINARY
60%
40%
20%
0%
-30
-5
20
45
70
Case Temperature (°C)
900
25
45
Temperature (°C)
65
120
200
60
150
40
100
20
50
0
0
-20
-50
-40
-100
1VOUT, 3.3VIN, 10A, 500uF
PHASE MARGIN = 75°, GAIN MARGIN = 10.8dB
-150
-80
5
95
80
-60
-15
10
MSK5061RH Stability
VIN = 5.5V
-35
9
80%
-55
VIN = 3V
-55
8
100%
SWITCHING FREQUENCY vs Tc
1000
7
120%
125
1050
1025
4
5
6
LOAD CURRENT (A)
RMS OUTPUT CURRENT vs Tc
SOA CURVE
602
-55
3
85
105
0.1
125
8
1
10
Frequency (KHz)
100
-200
1000
PRELIMINARY Rev. B 3/15
Phase (°)
598
EFFICIENCY
VOLATGE (mV)
599
MECHANICAL SPECIFICATION
ESD TRIANGLE INDICATES PIN 1
WEIGHT=TBD GRAMS TYPICAL
MSK5061 H RH
ALL DIMENSIONS ARE SPECIFIED IN INCHES
ORDERING INFORMATION
LEAD FORM OPTION
BLANK= STRAIGHT; G= GULL WING
RADIATION HARDENED
SCREENING
BLANK = INDUSTRIAL; H = MIL-PRF-38534 CLASS H;
K = MIL-PRF-38534 CLASS K
GENERAL PART NUMBER
9
PRELIMINARY Rev. B 3/15
MECHANICAL SPECIFICATION
ESD TRIANGLE INDICATES PIN 1
WEIGHT=TBD GRAMS TYPICAL
MSK5061 H RH G
ALL DIMENSIONS ARE SPECIFIED IN INCHES
ORDERING INFORMATION
LEAD FORM OPTION
BLANK= STRAIGHT; G= GULL WING
RADIATION HARDENED
SCREENING
BLANK = INDUSTRIAL; H = MIL-PRF-38534 CLASS H;
K = MIL-PRF-38534 CLASS K
GENERAL PART NUMBER
10
PRELIMINARY Rev. B 3/15
REVISION HISTORY
MSK
www.anaren.com/msk
The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make
changes to its products or specifications without notice, however, and assumes no liability for the use of its products.
Please visit our website for the most recent revision of this datasheet.
Contact MSK for MIL-PRF-38534 qualification status.
11
PRELIMINARY Rev. B 3/15
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