GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Features Description • SMPTE 424M, 292M, and 259M-C compliant • Supports data rates of 270, 1483.5, 1485, 2967, 2970Mb/s • Supports DVB-ASI at 270Mb/s The GS2975A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. • Pb-free and RoHS Compliant • Auto and Manual Modes for rate selection • Standards indication in Auto Mode • 4:1 input multiplexer patented technology • Choice of dual reclocked data outputs or one data output and one recovered clock output • Footprint and drop-in compatible with existing GS2975 designs • Loss of Signal (LOS) Output • Lock Detect Output • On-chip Input and Output Termination • Differential 50Ω inputs and outputs • Mute, Bypass and Autobypass functions • SD/HD indication output to control GS2978 Dual Slew-Rate Cable Driver • Single 3.3V power supply • Operating temperature range: 0°C to 70°C The GS2975A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 424M, SMPTE 292M, or SMPTE 259M-C compliant digital video signal. Applications • SMPTE 424M, SMPTE 292M and SMPTE 259M-C Serial Digital Interfaces The GS2975A removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50Ω transmission lines. The GS2975A can operate in either auto or manual rate selection mode. In Auto mode the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS2975A can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS2975A can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The GS2975A offers a choice of dual reclocked data outputs or one data output and one recovered clock output. The device is footprint and drop-in compatible with existing GS2975 designs, with no additional application changes required. The GS2975A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous sub-components are RoHS compliant. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 www.gennum.com 1 of 27 Functional Block Diagram XTAL XTAL OUT+ OUT- XTAL+ XTAL- XTAL OSC LF+ LF- KBB BUFFER RE-TIMER M U X DATA BUFFER DDO 0 DDO_MUTE RCO_MUTE DDI 0 DDI 1 DDI 2 PHASE FREQUENCY DETECTOR D A T A M U X CHARGE PUMP M U X VCO CLOCK BUFFER RCO/DDO1 DATA/CLOCK PHASE DETECTOR M U X DIVIDER DIVIDER DDI 3 BYPASS LOGIC CONTROL LOGIC DDI_SEL[1:0] SS[2:0] AUTO/MAN SD/HD LOCKED LOS AUTOBYPASS BYPASS GS2975A Functional Block Diagram Revision History Version ECR PCN Date Changes and/or Modifications 4 151358 – April 2009 Added 2.5k reel option to section 6.6 Ordering Information. Changed the maximum input swing value from 800mV to 1100mV in Table 2-2: AC Electrical Characteristics. 3 150068 – June 2008 Removed references to GND_DRV in Section 1.1 GS2975A Pin Assignment and Table 1-1: Pin Descriptions. 2 147068 – August 2007 1 146316 − July 2007 0 143947 43428 February 2007 GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 Typo: Functional Block Diagram on page 2. Typo: Pin 64 in Table 1-1& TAC Figure 5-1 on page 22, Pins 38/40 & 44/46 in Table 1-1. Converting to Data Sheet. Removed ‘Proprietary and Confidential’ footer. Updated AC Electrical Characteristics table. Added junction - board thermal resistance parameter to 6.3 Packaging Data. Added section 6.4 Marking Diagram. 2 of 27 Contents Features.................................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Functional Block Diagram ..............................................................................................................................2 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................4 1.1 GS2975A Pin Assignment ..............................................................................................................4 1.2 GS2975A Pin Descriptions .............................................................................................................5 2. Electrical Characteristics ............................................................................................................................8 2.1 Absolute Maximum Ratings ..........................................................................................................8 2.2 DC Electrical Characteristics ........................................................................................................8 2.3 AC Electrical Characteristics ..................................................................................................... 10 3. Input/Output Circuits ............................................................................................................................... 13 4. Detailed Description.................................................................................................................................. 16 4.1 Slew Rate Phase Lock Loop (S-PLL) ......................................................................................... 16 4.2 VCO .................................................................................................................................................... 17 4.3 Charge Pump ................................................................................................................................... 17 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector .................................. 18 4.5 Phase Acquisition Loop — The Phase Detector ................................................................... 18 4.6 4:1 Input Mux .................................................................................................................................. 19 4.7 Automatic and Manual Data Rate Selection ......................................................................... 19 4.8 Bypass Mode ................................................................................................................................... 20 4.9 DVB-ASI Operation ....................................................................................................................... 20 4.10 Lock and LOS ................................................................................................................................ 20 4.11 Output Drivers and Output Mute .......................................................................................... 21 5. Typical Application Circuit ..................................................................................................................... 22 6. Package & Ordering Information .......................................................................................................... 23 6.1 Package Dimensions ..................................................................................................................... 23 6.2 Recommended PCB Footprint ................................................................................................... 24 6.3 Packaging Data ............................................................................................................................... 25 6.4 Marking Diagram ........................................................................................................................... 25 6.5 Solder Reflow Profiles .................................................................................................................. 26 6.6 Ordering Information ................................................................................................................... 26 GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 3 of 27 1. Pin Out GND XTAL_OUTXTAL_OUT+ XTAL+ XTAL- NC NC NC NC NC NC VEE_CP VCC_CP LF+ NC LF- 1.1 GS2975A Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 DDI0 DDI0_VTT 1 2 47 VCC_DDO DDI0 3 46 DDO0 GND 4 45 RSV DDI1 5 44 DDI1_VTT 6 43 DDO0 GND 42 VEE_RCO 41 40 VCC_RCO RCO/DDO1 – – DDI1 7 GND 8 DDI2 9 GS2975A 64-pin QFN (Top View) VEE_DDO DDI2_VTT – DDI2 10 39 RSV 11 38 RCO/DDO1 GND 12 37 DDI3 13 36 DATA/CLOCK DDO_MUTE DDI3_VTT 14 35 RCO_MUTE KBB SD/HD GND VEE_DIG LOCKED LOS VCC_DIG NC SS2 SS1 SS0 VEE_VCO VCC_VCO AUTO/MAN DDI_SEL0 GND 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AUTOBYPASS DDI3 DDI_SEL1 BYPASS – Ground Pad (bottom of package) Figure 1-1: 64-Pin QFN GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 4 of 27 1.2 GS2975A Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Type Description 1, 3 DDI0, DDI0 Input Serial digital differential input 0. 2 DDI0_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0. GND Passive Recommended connect to GND. 5, 7 DDI1,DDI1 Input Serial digital differential input 1. 6 DDI1_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1. 9, 11 DDI2, DDI2 Input Serial digital differential input 2. 10 DDI2_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2. 13, 15 DDI3, DDI3 Input Serial digital differential input 3. 14 DDI3_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3. DDI_SEL[1:0] Logic Input Serial digital input select. 4, 8, 12,16, 32, 43, 49 17, 18 19 BYPASS Logic Input DDI_SEL1 DDI_SEL0 INPUT SELECTED 0 0 DDI0 0 1 DDI1 1 0 DDI2 1 1 DDI3 Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO/MAN Logic Input Auto/Manual select. When set HIGH, the standard is automatically detected from the input data rate. When set LOW, the user must program the input standard using the SS[2:0] pins. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 5 of 27 Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description 24, 25, 26 SS[0:2] Bi-directional When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . 27 NC No Connect 28 LOCKED Output SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 0 1 0 270 1 0 1 1483.5/1485 1 1 0 2967/2970 Not connected internally. Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 LOS Output Loss of Signal. Set HIGH when there are no transitions on the active DDI[3:0] input. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD Output This signal will be set LOW by the device when the reclocker has locked to 2.97Gb/s (2.967Gb/s) or 1.485Gb/s (1.4835Gb/s), or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 270Mbps. 34 KBB Analog Input Controls the loop bandwidth of the PLL. 35 RCO_MUTE Power Serial clock or secondary data output mute. Assert LOW for reduced power consumption, see 2.2 DC Electrical Characteristics. When RCO_MUTE = LOW, the RCO/DDO1 output is powered down. When RCO_MUTE = HIGH, the RCO/DDO1 output is active. NOTE: This is not a logic input pin. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 6 of 27 Table 1-1: Pin Descriptions (Continued) Pin Number 36 Name Type Description DDO_MUTE Logic Input Mutes the DDO0 and/or RCO/DDO1 outputs. DDO_MUTE RCO_MUTE DATA/CLOCK DDO0 RCO/DDO1 1 1 0 DATA CLOCK 1 1 1 DATA DATA 0 1 0 MUTE CLOCK 0 1 1 MUTE MUTE 1 0 X DATA Power down 0 0 X MUTE Power down NOTE: MUTE = Outputs latched at previous data bit. Power down = Outputs pulled to Vcc through 50Ω resistor. 37 DATA/CLOCK Logic Input Data/Clock select. When set HIGH, the RCO/DDO1 pin will output a copy of the serial digital output (DDO0). When set LOW, the RCO/DDO1 pin will output a re-timed clock (RCO). 38, 40 RCO/DDO1, Output RCO/DDO1 39, 45 41 Serial clock or secondary data output. When RCO_MUTE is connected to VCC, the serial digital differential clock or secondary data output will be presented. RSV Reserved Do not connect. VCC_RCO Power Most positive power supply connection for the RCO/DDO1 and RCO/DDO1 output driver. Connect to 3.3V. 42 VEE_RCO Power Most negative power supply connection for the RCO/DDO1 and RCO/DDO1 output driver. Connect to GND. 44, 46 47 DDO0, DDO0 Output VCC_DDO Power Differential Serial Digital Outputs. Most positive power supply connection for the DDO0/DDO0 output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO0/DDO0 output driver. Connect to GND. 50, 51 XTAL_OUT+, XTAL_OUT- Output Differential outputs of the reference oscillator used for monitoring or test purposes. 52, 53 XTAL+, XTAL- Input Reference crystal input. Connect to the GO1535 as shown in the Typical Application Circuit on page 22. 54 - 59 NC No Connect Not connected internally. VEE_CP Power Most negative power supply connection for the internal charge pump. 60 Connect to GND. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 7 of 27 Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 64 – LF+, LF- Passive Loop filter capacitor connection. Connect as shown in the Typical Application Circuit on page 22. NC No Connect Not connected internally. Recommended connect to GND. Center Pad – Ground pad on bottom of package. Solder to main ground plane following recommendations under Recommended PCB Footprint on page 24 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage Range -0.5V to +3.6 VDC Input Voltage Range Vee - 0.5V to Vcc + 0.5V Operating Temperature Range -20°C to 85°C Storage Temperature Range -50°C < Ts < 125°C Input ESD Voltage 4kV HBM, 100V MM Solder Reflow Temperature 260°C NOTE: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristic sections is not implied. 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Symbol Conditions Min Typ Max Units Supply Voltage VCC Operating Range 3.135 3.3 3.465 V Supply Current ICC RCO/DD01 enabled – 142 170 mA ICC RCO/DDO1 disabled – 123 152 mA GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 8 of 27 Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Symbol Conditions Min Typ Max Units Power Consumption – RCO/DD01 enabled – 468 590 mW – RCO/DD01 disabled – 404 528 mW Logic Inputs VIH High 2.0 – – V DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, DDO_MUTE VIL Low – – 0.8 V Logic Outputs VOH IOH = -2mA 2.4 – – V VOL IOL = 2mA – – 0.4 V VIH High 2.0 – – V VIL Low – – 0.8 V VOH IOH = -2mA 2.4 – – V VOL IOL = 2mA – – 0.4 V VOH High – VCC - 0.075 – V VOL Low – VCC - 0.300 – V RCO_MUTE – I = -1.5mA VCC - 0.165 VCC VCC + 0.165 V Serial Input Voltage – Common Mode 1.65 + (VSID/2) – VCC (VSID/2) V Serial Output Voltage – Common Mode – VCC - (VOD/2) – V SD/HD, LOCKED, LOS Bi-Directional Pins (Manual Mode) SS[2:0], AUTO/MAN = 0 Bi-Directional Pins (Auto Mode) SS[2:0], AUTO/MAN = 1 XTAL_OUT+, XTAL_OUT- DDO0/DDO0, RCO/DDO1 / RCO/DDO1 GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 9 of 27 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Symbol Conditions Min Typ Max Units Notes Serial Input Data Rate – – 270 – 2970 Mb/s – Serial Input Jitter Tolerance – Worst case modulation (e.g. square wave modulation) 0.8 – – UI – 270, 1485, 2970 Mb/s PLL Lock Time - Asynchronous tALOCK – – 1.5 10 ms – PLL Lock Time - Synchronous t SLOCK KBB = Float, CLF=47nF SD/HD = 0 – 0.5 4 μs – KBB = Float, CLF=47nF SD/HD = 1 – 5 20 μs – Serial Output Rise/Fall Time SDO0 and RCO/DDO1 (20% 80%) trSDO,trRCO 50Ω load (on chip) – 110 – ps – tfSDO,tfRCO 50Ω load (on chip) – 110 – ps – Serial Digital Input Signal Swing VSID Differential with internal 100Ω input termination 100 – 1100 mVp-p – 300 450 600 mVp-p – See Figure 2-1 Serial Digital Output Signal Swing VOD 100Ω load differential See Figure DDO0 and RCO/DDO1 DDO0 to DDO1 skew DDskew – – 156 – ps 1 DDO0 to RCO skew DRskew 2970 Mb/s, 1485 Mb/s – 28 – ps 2 270 Mb/s – 37 – ps 2 270 Mb/s – 0.02 0.07 UI 3 1485 Mb/s – 0.06 0.10 UI 4 2970 Mb/s – 0.10 0.15 UI 4 270 Mb/s – 0.02 0.07 UI 3 1485 Mb/s – 0.06 0.10 UI 4 2970 Mb/s – 0.11 0.16 UI 4 Bypass mode, 2970 Mb/s DDO0 enabled – 15 – ps – Bypass mode, 2970 Mb/s DDO0 and DDO1 enabled – 20 – ps – Serial Output Jitter on DDO0 tOJ (RCO/DDO1 disabled) Serial Output Jitter on DDO0 and DDO1 tOJ (Both DDO0 and DDO1enabled) Additive Jitter tAJ GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 10 of 27 Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Symbol Conditions Min Typ Max Units Notes Loop Bandwidth BWLOOP 2.97 Gb/s, KBB = VCC – 1.75 – MHz – 2.97 Gb/s, KBB = FLOAT – 3.5 – MHz – 2.97 Gb/s, KBB = GND, <0.1dB Peaking – 7.0 – MHz – 1.485 Gb/s, KBB = VCC – 0.875 – MHz – 1.485 Gb/s, KBB = FLOAT – 1.75 – MHz – 1.485 Gb/s, KBB = GND, <0.1dB Peaking – 3.5 – MHz – 270 Mb/s, KBB = VCC – 0.16 – MHz – 270 Mb/s, KBB = FLOAT – 0.32 – MHz – 270 Mb/s, KBB = GND, <0.1dB Peaking – 0.64 – MHz – NOTES: 1. DDO0 to DDO1 skew alignment as defined here: . DDO0 DDO1 DDSKEW 2. DDO0 to RCO skew alignment as defined here: DDO0 RCO DR SKEW 3. KBB = Float, PRN = 223-1, input jitter = 40psp-p. 4. KBB = Float, PRN = 223-1, input jitter = 20psp-p. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 11 of 27 VCC VCC _ VSID 2 VSID 2 Single-Ended Swing (DDIx) VSID 2 Single-Ended Swing (DDIx) VSID Differential Swing (DDIx-DDIx) VDD VCC _ VSID 2 + VSID 2 0 _ VSID 2 Figure 2-1: Serial Digital Input Signal Swing VCC VCC _ VOD 2 VOD 2 Single-Ended Swing (DDO0, DDO1, RCO) VOD 2 Single-Ended Swing (DDO0,DDO1, RCO) VOD Differential Swing (DDO0-DDO0) (DDO1-DDO1) (RCO-RCO) VDD VCC _ VOD 2 + VOD 2 0 _ VOD 2 Figure 2-2: Serial Digital Output Signal Swing GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 12 of 27 3. Input/Output Circuits VREF Figure 3-1: TTL Inputs LF+ LF- Figure 3-2: Loop Filter 250R 250R 10p 5K 5K XTAL+ XTAL- Figure 3-3: Crystal Input GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 13 of 27 1K 1K XTAL OUT- XTAL OUT+ Figure 3-4: Crystal Output Buffer 50 50 DDO0 / RCO/DDO1 DDO0 / RCO/DDO1 Figure 3-5: Serial Data Outputs, Serial Clock Outputs KBB VTH1 VTH2 Figure 3-6: KBB Figure 3-7: Indicator Outputs: SD/HD, LOCKED, LOS GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 14 of 27 24k SS[2:0] AUTO/MAN Figure 3-8: Standard Select/Indication Bi-directional Pins DDI[3:0] 50 1k 1k DDI_VTT 50 DDI[3:0] Figure 3-9: Serial Data Inputs GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 15 of 27 4. Detailed Description The GS2975A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS2975A will recover the embedded clock signal and re-time the data from a SMPTE 424M, SMPTE 292M, or SMPTE 259M-C compliant digital video signal. Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock Loop (S-PLL) on page 16 to on page 21 describes each aspect of the GS2975A in detail. 4.1 Slew Rate Phase Lock Loop (S-PLL) The term “slew” refers to the output phase of the PLL in response to a step change at the input. Linear PLLs have an output phase response characterized by an exponential response whereas an S-PLL’s output is a ramp response (see Figure 4-1). Because of this non-linear response characteristic, traditional small signal analysis is not possible with an S-PLL. PHASE (UI) 0.2 INPUT 0.1 OUTPUT 0.0 SLEW PLL RESPONSE PHASE (UI) 0.2 INPUT 0.1 OUTPUT 0.0 LINEAR (CONVENTIONAL) PLL RESPONSE Figure 4-1: PLL Characteristics GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 16 of 27 The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of an S-PLL is independent of the transition density of the input data. Pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. The loop bandwidth of a linear PLL will change proportionally with this change in transition density. With an S-PLL, the loop bandwidth is defined by the jitter at the data input. This translates to infinite loop bandwidth with a zero jitter input signal. This allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. The loop bandwidth of the GS2975A’s PLL is defined at 0.2UI of input jitter. The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA) loop. This loop is active when the device is not locked and is used to achieve lock to the supported data rates. Second is the phase acquisition (PA) loop. Once locked, the PA loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 VCO The internal VCO of the GS2975A is an LC oscillator. It is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. Integrated into the VCO is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 Charge Pump During frequency acquisition, the charge pump has two states, “pump-up” and “pump-down,” which is produced by a leading or lagging phase difference between the input and the VCO frequency. During phase acquisition, there are two levels of “pump-up” and two levels of “pump down” produced for leading and lagging phase difference between the input and VCO frequency. This is to allow for greater precision of VCO control. The charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, CLF. The instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 17 of 27 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector An external crystal of 14.140MHz is used as a reference to keep the VCO centered at the last known data rate. This allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. The crystal reference is also used to clock internal timers and counters. To keep the optimal performance of the reclocker over all operating conditions, the crystal frequency must be 14.140MHz, +/-50ppm. The GO1535 meets this specification and is available from Gennum. The GO1535 requires an external resistor to be placed in series with the crystal. The optimal value of this resistor can range from 100 to 150 ohms, and this value will depend upon the design. For systems which expect to see a higher noise floor, the higher resistor value is recommended. The higher resistor value will work to decrease the loop gain of the oscillator, as well as attenuate noise. The VCO is divided by a selected ratio which is dependant on the input data rate. The resultant is then compared to the crystal frequency. If the divided VCO frequency and the crystal frequency are within 1% of each other, the PLL is considered to be locked to the input data rate. 4.5 Phase Acquisition Loop — The Phase Detector The phase detector is a digital quadrature phase detector. It indicates whether the input data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the input data transition is aligned to the falling edge of I-clk and the output data is re-timed on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 18 of 27 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] Selected Input 00 DDI0 01 DDI1 10 DDI2 11 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS2974 Cable Equalizer. There are on-chip 50Ω termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS2975A can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The “search algorithm” cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). 270Mb/s 1.485(1.4835)Gb/s 2.970(2.697)Gb/s Figure 4-3: Data Rate Search Pattern GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 19 of 27 In Manual mode, the data rate can be programmed and the SS[2:0] pins become inputs. In this mode, the search algorithm is disabled and the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] Data Rate (Mb/s) 010 270 101 1485 (1483.5) 110 2970 (2967) 4.8 Bypass Mode In Bypass mode, the GS2975A passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH, the GS2975A will be in Bypass mode. When AUTOBYPASS is set HIGH, the GS2975A will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO0/DDO0 or DDO1/DDO1 will produce invalid data. 4.9 DVB-ASI Operation The GS2975A will also re-clock DVB-ASI at 270 Mb/s. In auto mode, the device will automatically lock to the incoming 270Mb/s signal. In manual mode, the SS[2:0] pins must be set to 010 (270 Mb/s) to ensure proper operation. 4.10 Lock and LOS The LOCKED signal is an active high output which indicates when the PLL is locked. The internal lock logic of the GS2975A includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of data transitions at the DDIx input. In order for this output to be asserted, transitions must not be present for a period of tLA = 5 - 10μs. After this output has been asserted, LOS will de-assert within tLD = 0 - 5μs after the appearance of a transition at the DDIx input. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 20 of 27 t LA t LD DATA LOS Figure 4-4: LOS signal timing NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. 4.11 Output Drivers and Output Mute The GS2975A offers a choice of dual reclocked data outputs or one data output and one recovered clock output. Table 4-3 shows the correlation of the output pins to the corresponding input select pins. Table 4-3: Configuration of Output Drivers and Output Mute Pins DDO_MUTE RCO_MUTE DATA/CLOCK DDO0 RCO/DDO1 1 1 0 DATA CLOCK 1 1 1 DATA DATA 0 1 0 MUTE CLOCK 0 1 1 MUTE MUTE 1 0 X DATA Power Down 0 0 X MUTE Power Down NOTE: MUTE = Outputs latched at previous data bit. Power down = Outputs pulled to Vcc through 50Ω resistor. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 21 of 27 5. Typical Application Circuit GO1535 (14.140MHz) 47n 3.3V GND 49 XTAL_OUT+ 52 51 XTAL+ XTAL_OUT- 53 54 NC XTAL- 56 55 NC NC 58 57 NC NC 59 NC 61 62 63 60 VEE_CP VCC_CP GND 3.3V 46 45 Zo = 50 D ATA O U T P U T 44 43 42 1 0n 3.3V 40 RCO/DDO1 DDI2 RSV DDI2_VT DDI2 RCO/DDO1 GND D ATA / C L O C K DDI3 DDO_MUTE DDI3_VT RCO_MUTE 39 Zo = 50 CLOCK OUTPUT 38 37 D ATA / C L O C K 36 DDO_MUTE 35 RCO_MUTE 34 DDI3 KBB SD/HD GND VEE_DIG 33 32 31 LOS VCC_DIG 30 29 LOCKED NC 27 28 SS2 SS1 26 VEE_VC0 SS0 25 17 DDI_SEL0 DDI_SEL1 SD/HD 24 GND DDI_SEL0 16 1 0n 47 41 VCC_VCO 15 48 VCC_RCO GS2975A 23 14 10n VEE_RCO 22 11 13 Zo = 50 GND DDI1 12 D ATA I N P U T 3 DDI1_VT 8 10 10n DDO0 AUTO/MAN Zo = 50 DDI1 7 9 D ATA I N P U T 2 RSV 21 6 10n DDO0 GND AUTOBYPASS Zo = 50 DDI0 BYPASS D ATA I N P U T 1 VEE_DDO VCC_DDO DDI0_VT 20 5 DDI0 19 4 LF+ 64 3 LF- NC 10n 2 DDI_SEL1 Zo = 50 18 1 D ATA I N P U T 0 50 100 10n 10n 10n 3.3V 3.3V LOS LOCKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS2975A Typical Application Circuit NOTE: The GS2975A is drop-in compatible with the GS2975 application circuit. In the GS2975 application circuit pin 37 is connected to ground. If the GS2975A is dropped into the GS2975 application circuit, the RCO/DDO1 and RCO/DDO1 pins will output the recovered clock. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 22 of 27 6. Package & Ordering Information A 9.00 B 4.50 0.40+/-0.05 6.1 Package Dimensions 0.3+/-0.05 7.10+/-0.15 3.55 45° 45 9.00 PIN 1 AREA 7.10+/-0.15 4.50 ° 3.55 CENTRE TAB 2X 2X 0.15 C 0.10 C 0.20 REF 0.15 C 0.25+/-0.05 0.50 C 64X C A B 0.10 C 0.05 64X 0.90 +/- 0.10 +0.03 0.02-0.02 0.08 C SEATING PLANE GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 ALL DIMENSIONS IN MM 23 of 27 6.2 Recommended PCB Footprint 0.25 0.50 0.55 CENTER PAD 8.70 7.10 7.10 8.70 NOTE: All dimensions are in millimeters. The center pad of the PCB footprint should be connected to the ground plane by a minimum of 36 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimization. GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 24 of 27 6.3 Packaging Data Parameter Value Package Type 9mm x 9mm 64-pin QFN Moisture Sensitivity Level (per JEDEC J-STD-020C) 3 Junction to Case Thermal Resistance, θj-c 9.1°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 21.5°C/W Junction to Board Thermal Resistance, θj-b 5.6°C/W Psi, Ψ 0.2°C/W Pb-free and RoHS Compliant Yes 6.4 Marking Diagram Pin 1 ID GS2975A XXXXE3 YYWW GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 XXXX - Lot/Work Order ID YYWW - Date Code YY - 2-digit year WW - 2-digit week number 25 of 27 6.5 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 6-1. The recommended standard Pb reflow profile is shown in Figure 6-2. Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred) 60-150 sec. Temperature 10-20 sec. 230°C 220°C 3°C/sec max 183°C 6°C/sec max 150°C 100°C 25°C Time 120 sec. max 6 min. max Figure 6-2: Standard Pb Solder Reflow Profile 6.6 Ordering Information Part Number Package Temperature Range GS2975A GS2975ACNE3 Pb-free 64-pin QFN 0°C to 70°C GS2975A GS2975ACNTE3Z Pb-free 64-pin QFN 2,500pc Reel 0°C to 70°C GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 26 of 27 DOCUMENT IDENTIFICATION CAUTION DATA SHEET ELECTROSTATIC SENSITIVE DEVICES The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION GENNUM CORPORATE HEADQUARTERS Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada E-mail: [email protected] www.gennum.com OTTAWA SNOWBUSH IP - A DIVISION OF GENNUM GERMANY 232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Hainbuchenstraße 2 80935 Muenchen (Munich), Germany Phone: +49-89-35831696 Phone: +1 (613) 270-0458 Phone: +1 (416) 925-5643 Fax: +49-89-35804653 Fax: +1 (613) 270-0429 Fax: +1 (416) 925-0581 E-mail: [email protected] CALGARY E-mail: [email protected] 3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada Web Site: http://www.snowbush.com Phone: +1 (403) 284-2672 UNITED KINGDOM MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 NORTH AMERICA WESTERN REGION Bayshore Plaza 2107 N 1st Street, Suite #300 San Jose, CA 95131 United States Phone: +1 (408) 392-9454 Phone: +1 (416) 848-0328 Fax: +1 (408) 392-9427 JAPAN KK E-mail: [email protected] NORTH AMERICA EASTERN REGION Fax: +44 1279 714171 Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan INDIA Phone: +81 (03) 3349-5501 Phone: +1 (905) 632-2996 #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Fax: +81 (03) 3349-5505 Fax: +1 (905) 632-2055 E-mail: [email protected] E-mail: [email protected] Phone: +91 (674) 653-4815 TAIWAN Fax: +91 (674) 259-5733 6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C. North Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom Phone: +44 1279 714170 Web Site: http://www.gennum.co.jp 4281 Harvester Road Burlington, Ontario L7L 5M4 Canada KOREA 8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828 Phone: +82-2-414-2991 Phone: (886) 2-8732-8879 Fax: +82-2-414-2998 Fax: (886) 2-8732-8870 E-mail: [email protected] E-mail: [email protected] Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2006 Gennum Corporation. All rights reserved. www.gennum.com GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual Differential Outputs Data Sheet 41487 - 4 April 2009 27 of 27 27