Features • • • • • • • • • • • Reference Oscillator up to 15 MHz (Tuned) Oscillator Buffer Output (for AM Up/Down Conversion) Two Programmable 16-bit Dividers Fine-tuning Steps Possible Fast Response Time Due to Integrated Loop Push-pull Stage 3-wire Bus (Enable, Clock and Data; 3V and 5V Microcontrollers Acceptable) Four Programmable Switching Outputs (Open Drain) Three DACs for Software Controlled Tuner Alignment Low-power Consumption High Signal to Noise Ratio (SNR) Integrated Band Gap – Only One Supply Voltage Necessary Frequency Synthesizer for Radio Tuning 1. Description The ATR4256 is a synthesizer IC for FM receivers and an AM up-conversion system in BiCMOS technology. Together with the AM/FM IC ATR4258 or ATR4255, it comprises a complete AM/FM car radio front-end, which is also recommended for RDS (Radio Data System) applications. It is controlled by a 3-wire bus and also contains switches and Digital to Analog Converters (DACs) for software-controlled alignment of the AM/FM tuner. The ATR4256 is the pin-compatible successor IC of U4256BM-R. Figure 1-1. ATR4256 Block Diagram SWO1 SWO2 SWO3 SWO4 7 8 9 10 Tuning OSCIN OSCOUT MX2LO CLK DATA EN 13 12 15 Oscillator Switching outputs DAC3 3-bit 18 OSC buffer 3-wire bus interface Rdivider FMOSCIN 19 FMpreamp Ndivider Phase detector 20 14 V5 DAC2 4 DAC1 3 DAC AM/FM 2 DAC1 PDO PD 6 11 GND DAC2 VRef 1 Current sources Band gap GNDAN DAC3 V Ref 17 16 5 VS 4867D–AUDR–01/08 OSCOUT 14 13 12 7 8 9 SWO1 SWO2 SWO3 11 GND OSCIN 15 6 VS 2 Pin Symbol 1 PDO Phase detector output 2 PD Pulsed current output 3 DAC1 Digital-to-analog converter 1 4 DAC2 Digital-to-analog converter 2 5 DAC3 Digital-to-analog converter 3 6 VS Supply voltage, analog part 7 SWO1 Switching output 1 8 SWO2 Switching output 2 9 SWO3 Switching output 3 10 SWO4 Switching output 4 SWO4 10 ATR4256 V5 DATA 16 5 DAC3 MX2LO CLK 17 4 DAC2 EN 18 FMOSCIN 19 2 PD 3 GNDAN Pin Description 20 Table 2-1. 1 Pinning SSO20 PDO Figure 2-1. DAC1 2. Pin Configuration Function 11 GND 12 OSCOUT Ground, digital part 13 OSCIN 14 V5 15 MX2LO 16 DATA 17 CLK Clock 18 EN Enable 19 FMOSCIN 20 GNDAN Reference oscillator output Reference oscillator input Capacitor band gap Oscillator buffer output Data input FM-oscillator input Ground, analog part ATR4256 4867D–AUDR–01/08 ATR4256 3. Functional Description For a tuned FM-broadcast receiver, the following parts are needed: • Voltage-controlled Oscillator (VCO) • Antenna Amplifier Tuned Circuit • RF Amplifier Tuned Circuit Typical modern receivers with electronic tuning are tuned to the desired FM frequency by the frequency synthesizer IC ATR4256. The special design allows the user to build software-controlled tuner alignment systems. Two programmable DACs (Digital-to-Analog Converter) support the computer-controlled alignment. The output of the PLL is a tuning voltage which is connected to the VCO of the receiver IC. The output of the VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the oscillator signal (VCO) are both input to the mixer that translates the desired FM-channel signal to the fixed IF signal. For FM, the double-conversion system of the receiver requires exactly 10.7 MHz for the first IF frequency, which determines the center frequency of the software-controlled integrated second IF filter. If this oscillator tuning feature is not used, the internal capacitors have to be switched off and the oscillator has to be operated with high-quality external capacitors to ensure that the operational frequency is exactly 10.250 MHz. When dimensioning the oscillator circuit, it is important that the additional capacitors enable the oscillator to operate through its complete tracking range. The oscillating ability depends very strongly on the used crystal oscillator. Initializing the oscillator should be established without switching any additional capacitors to guarantee that the oscillator starts to operate properly. Due to the lower quality of the integrated capacitors compared to discrete capacitors, the amount of the switched integrated capacitors should always be minimized. (If necessary reduce tracking range or use a different crystal oscillator.) The ATR4256 has a very fast response time of maximum 800 µs (at 2 mA, fStep = 50 kHz, measured on the MPX signal). It has a high signal to noise ratio. Only one supply voltage is necessary, due to an integrated band gap. 3 4867D–AUDR–01/08 4. Input/Output Interface Circuits 4.1 PDO (Pin 1) PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. 4.2 PD (Pin 2) PD is the current charge pump output of the PLL. The current can be controlled by setting the appropriate bits. The loop filter has to be designed corresponding to the chosen pump current and the internal reference frequency. A recommendation can be found in the application circuit. The charge-pump current can be chosen by setting Bit 71 and Bit 70 as follows: Table 4-1. Current Charge-pump Output IPD (µA) B71 B70 25 0 0 100 0 1 500 1 0 2000 1 1 Figure 4-1. VS Internal Components at PDO Connection VS VS PDO PD 4 ATR4256 4867D–AUDR–01/08 ATR4256 4.3 FMOSCIN (Pin 19) FMOSCIN is the preamplifier input for the FM oscillator signal. Figure 4-2. Internal Components at FMOSCIN V5 FMOSCIN 4.4 MX2LO (Pin 15) MX2LO is the buffered output of the crystal oscillator. This signal can be used as a reference frequency for ATR4255 or ATR4258. The oscillator buffer output can be switched by the OSCB bit (B69) as follows. Table 4-2. Figure 4-3. MX2LO Settings MX2LO AC Voltage B69 ON 0 OFF 1 Internal Components at MX2LO V5 V5 OSCIN MX2LO 5 4867D–AUDR–01/08 4.5 Function of DAC1, DAC2 in FM and AM Mode (Pin 3 and Pin 4) For automatic tuner alignment, the DAC1 and DAC2 of the ATR4256 can be controlled by setting the gain of VPDO and offset values. Figure 4-4 shows the principle of the operation. In FM Mode the gain is in the range of 0.69 × V(PDO) to 2.16 × V(PDO). The offset range is +0.56V to –0.59V. For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filters. For alignment, offset and gain are set to have the best tuner tracking. Figure 4-4. Principal Operation for Alignment Bit 34 PDO (FM) Gain +/- DAC1,2 Vref (AM) (3V) Offset The DAC mode can be controlled by setting Bit 34 as follows Table 4-3. DAC Mode DAC Mode B34 FM 0 AM 1 If Bit 34 = 1 (AM Mode), then DAC1 and DAC2 can be used as standard DAC converters. The internal voltage of 3V is connected to the gain and offset input of DAC1 and DAC2 (only in AM Mode). The gain is in the range of 0.46 × 3V to 3.03 × 3V. The offset range is +1.46V to –1.49V. Figure 4-5. Internal Components at DAC1 and DAC2 Output VS DAC1,2 6 ATR4256 4867D–AUDR–01/08 ATR4256 4.6 DAC1, DAC2 in FM Mode (Pin 3 and Pin 4) The gains of DAC1 and DAC2 have a range of 0.69 × V(PDO) to 2.16 × V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps; one step is approximately (2.16 – 0.46) × V(PDO) / 255 = 0.005764 × V(PDO). The gain of DAC1 can be controlled by B36 to B43 (bits 0 to 7 of DAC1 Gain), and the gain of DAC2 by B0 to B7 (bits 0 to 7 of DAC2 Gain) as follows: Table 4-4. DAC Gain Setting, FM Mode Gain DAC1, Approximately Gain DAC2, Approximately 0.69 × V(PDO) 0.69576 × V(PDO) 0.70153 × V(PDO) 0.70729 × V(PDO) ... 0.99549 × V(PDO) ... 2.14847 × V(PDO) 2.15424 × V(PDO) 2.16 × V(PDO) B43 B42 B41 B40 B39 B38 B37 B36 B7 0 0 0 0 ... 0 ... 1 1 1 B6 0 0 0 0 ... 0 ... 1 1 1 B5 0 0 0 0 ... 1 ... 1 1 1 B4 0 0 0 0 ... 1 ... 1 1 1 B3 0 0 0 0 ... 0 ... 1 1 1 B2 0 0 0 0 ... 1 ... 1 1 1 B1 0 0 1 1 ... 0 ... 0 1 1 B0 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 53 ... 253 254 255 Offset = 31 (intermediate position) The offset of DAC1 and DAC2 has a range of 0.56V to –0.59V. This range is divided into 64 steps; one step is approximately 1.15V / 63 = 18.25 mV. The offset of DAC1 can be controlled by B44 to B49 (bits 0 to 5 of DAC1 Offset), and the offset of DAC2 by B8 to B13 (bits 0 to 5 of DAC2 Offset) as follows: Table 4-5. DAC Offset Setting, FM Mode Offset DAC1, Approximately Offset DAC2, Approximately 0.56V 0.5417V 0.5235V 0.5052V ... +0.0059V ... 0.5535V –0.5717V –0.59V B49 B48 B47 B46 B45 B44 B13 0 0 0 0 ... 0 ... 1 1 1 B12 0 0 0 0 ... 1 ... 1 1 1 B11 0 0 0 0 ... 1 ... 1 1 1 B10 0 0 0 0 ... 1 ... 1 1 1 B9 0 0 1 1 ... 1 ... 0 1 1 B8 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 31 ... 61 62 63 Gain = 53 (intermediate position) 7 4867D–AUDR–01/08 4.7 DAC1, DAC2 in AM Mode (Pin 3 and Pin 4) In AM mode the DAC input voltage V(PDO) is internally connected to 3V. The gains of DAC1 and DAC2 have a range of 0.46 × 3V to 3.03 × 3V. V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps; one step is approximately (3.03 – 0.46) × 3V / 255 = 0.01007 × 3V. The gain of DAC1 can be controlled by B36 to B43 (bits 0 to 7 of DAC1 Gain) and the gain of DAC2 by B0 to B7 (bits 0 to 7 of DAC2 gain) as follows: Table 4-6. DAC Gain, AM Mode Gain DAC1, Approximately Gain DAC2, Approximately 0.4607 × 3V 0.4710 × 3V 0.4812 × 3V 0.4915 × 3V ... 1.0029 × 3V ... 3.0097 × 3V 3.0196 × 3V 3.0296 × 3V B43 B42 B41 B40 B39 B38 B37 B36 B7 0 0 0 0 ... 0 ... 1 1 1 B6 0 0 0 0 ... 0 ... 1 1 1 B5 0 0 0 0 ... 1 ... 1 1 1 B4 0 0 0 0 ... 1 ... 1 1 1 B3 0 0 0 0 ... 0 ... 1 1 1 B2 0 0 0 0 ... 1 ... 1 1 1 B1 0 0 1 1 ... 0 ... 0 1 1 B0 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 53 ... 253 254 255 Offset = 31 (intermediate position) Remark: V(PDO) is 3V in AM mode. The offset of DAC1 and DAC2 has a range of +1.46V to –1.49V. This range is divided into 64 steps; one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can be controlled by B44 to B49 (bits 0 to 5 of DAC1 Offset) and the offset of DAC2 by B8 to B13 (bits 0 to 5 of DAC2 Offset) as follows: Table 4-7. DAC Offset, AM Mode Offset DAC1 Approximately Offset DAC2 Approximately 1.4606V 1.4138V 1.3665V 1.3196V ... –0.0079V ... –1.3975V –1.4447V –1.4917V B49 B48 B47 B46 B45 B44 B13 0 0 0 0 ... 0 ... 1 1 1 B12 0 0 0 0 ... 1 ... 1 1 1 B11 0 0 0 0 ... 1 ... 1 1 1 B10 0 0 0 0 ... 1 ... 1 1 1 B9 0 0 1 1 ... 1 ... 0 1 1 B8 0 1 0 1 ... 1 ... 1 0 1 Decimal Gain Decimal Gain 0 1 2 3 ... 31 ... 61 62 63 Gain = 53 (intermediate position) 8 ATR4256 4867D–AUDR–01/08 ATR4256 4.8 DAC3 (Pin 5) The DAC3 output voltage can be controlled by B66 to B68 (bits 0 to 2 of DAC3) as follows: Table 4-8. DAC3 Offset Setting DAC3 Offset, Approximately B68 B67 B66 0.55V 0 0 0 1.25V 0 0 1 1.90V 0 1 0 2.60V 0 1 1 3.30V 1 0 0 4.10V 1 0 1 4.80V 1 1 0 5.45V 1 1 1 Figure 4-6. Internal Components at DAC3 VS DAC3 4.9 EN, DATA, CLK (Pins 16 to 18) All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and CLOCK. The bus is designed for microcontrollers which operate with 3V supply voltage. Details of the data transfer protocol are shown in “3-wire Bus Description” on page 12. Figure 4-7. Internal Components at EN, DATA, CLK V5 EN DATA CLK 9 4867D–AUDR–01/08 4.10 SWO1, SWO2, SWO3 and SWO4 (Pins 7 to 10) All switching outputs are “open drain” and can be set and reset by software control. Details are described in the data transfer protocol. The switching output SWO1 to SWO4 can be controlled as follows (B30 to B33): Table 4-9. SWO1 to SWO4 Setting Switch Output B30 + X SWOx = ON (switch to GND) 0 SWOx = OFF 1 X = 0 to 3 Figure 4-8. Internal Components at SWO1, SWO2, SWO3 and SWO4 SWO1 SWO2 SWO3 SWO4 4.11 I OSCIN, OSCOUT (Pin 12 and Pin 13) A crystal resonator (up to 15 MHz) is connected between OSCIN and OSCOUT in order to generate the reference frequency. By using the ATR4256 in connection with ATR4255 or ATR4258, the crystal frequency must be 10.25 MHz. The complete application circuit is shown in Figure 6-2. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100 mVrms. In this case, pin OSCOUT has to be open. The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The values are coded binary. The tuning can be controlled by B78 to B85 as follows: Table 4-10. B85 = 1 [pF] 0 0.5 1.0 1.5 ... 63.0 63.5 10 Crystal Tuning Capacitance B85 = 0 [pF] 8.0 8.5 9.0 19.5 ... 71.0 71.5 B84 1 1 1 1 ... 0 0 B83 1 1 1 1 ... 0 0 B82 1 1 1 1 ... 0 0 B81 1 1 1 1 ... 0 0 B80 1 1 1 1 ... 0 0 B79 1 1 0 0 ... 0 0 B78 1 0 1 0 ... 0 0 ATR4256 4867D–AUDR–01/08 ATR4256 Figure 4-9. Internal Components at OSCIN and OSCOUT V5 OSCIN V5 OSCOUT Figure 4-10. Internal Connection of Tuning Capacity for Crystal Oscillator Cx1 Cx2 INV 8 pF 32 pF ... 0.5 pF 0.5 pF 32 pF 8 pF ... B78 B84 B85 11 4867D–AUDR–01/08 5. Application Information Figure 5-1. FMOSCIN Sensitivity Vi (mVrms on 50Ω) 150 100 50 0 0 20 40 60 80 100 120 140 160 Frequency (MHz) 6. 3-wire Bus Description The register settings of ATR4256 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits are transmitted sequentially during each command. One command is used to program all the bits of one register. The different registers available (see “Data Transfer” on page 14) are addressed by the length of the command (number of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge on EN. EN has to be kept HIGH during the bus command. The sequence of transmitted bits during one command starts with the LSB of the first byte and ends with the MSB of the last byte of the register addressed. To transmit one bit (0 or 1) DATA has to be set to the appropriate value (LOW or HIGH) and a LOW to HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is used to determine the length of the command. The bus protocol and the register addressing of ATR4256 are compatible to the addressing used in ATR4255 and ATR4258. That means ATR4256 and ATR4255 (or ATR4258) can be operated on the same 3-wire bus as shown in the application circuit. 12 ATR4256 4867D–AUDR–01/08 ATR4256 Figure 6-1. 3-wire Bus Timing Diagram tR tF VHIGH Enable tHEN tS tR VLOW tF VHIGH Data VLOW tHDA tS tF tR VHIGH Clock VLOW tH tL Figure 6-2. 3-wire Pulse Diagram 16-bit command EN DATA LSB BYTE 1 MSB LSB BYTE 2 MSB CLK 24-bit command EN DATA LSB MSB LSB BYTE 1 BYTE 2 MSB LSB BYTE 3 MSB CLK e.g. R-Divider 0 2 21 22 23 24 25 26 27 R-Divider 28 29 210 211 212 213 214 215 OSCB P-2 P-2 DAC3 IPD 0 P-2 Status 0 0 Addr. 13 4867D–AUDR–01/08 6.1 Data Transfer Table 6-1. Control Registers A MSB BYTE 3 ADDR. STATUS 0 0 IPD 0 LSB MSB B69 LSB MSB BYTE 1 LSB R-Divider OSCB 0=on, P-22 P-21 P-20 1=off B71 B70 BYTE 2 DAC3 B68 B67 B66 215 214 213 212 210 211 29 28 B65 B64 B63 B62 B61 B60 B59 B58 27 26 B57 B56 25 24 23 22 21 20 B55 B54 B53 B52 B51 B50 B MSB BYTE 3 ADDR. 0 1 LSB MSB BYTE 2 LSB MSB STATUS 1 B33 B32 LSB N-Divider AM=1 SWO4 SWO3 SWO2 SWO1 0 FM=0 0=on, 0=on, 0=on, 0=on, DAC 1=off 1=off 1=off 1=off B35 B34 BYTE 1 B31 B30 215 214 213 212 210 211 29 28 B29 B28 B27 B26 B25 B24 B23 B22 27 26 B21 B20 25 24 23 22 21 20 B19 B18 B17 B16 B15 B14 C MSB BYTE 2 ADDR. 0 0 LSB MSB BYTE 1 DAC1 OFFSET LSB DAC1 GAIN O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 D MSB BYTE 2 ADDR. 0 LSB MSB BYTE 1 DAC2 OFFSET LSB DAC2 GAIN 1 O-25 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20 B13 B12 B11 B10 B9 B8 B7 LSB MSB B6 B5 B4 B3 B2 B1 B0 E MSB BYTE 2 ADDR. 1 0 8 pF 32 pF 16 pF 8 pF 4 pF 2 pF B85 B84 14 BYTE 1 Oscillator tuning function B83 B82 B81 B80 LSB Not used 1 pF 0.5 pF B79 B78 X X X X X X B77 B76 B75 B74 B73 B72 ATR4256 4867D–AUDR–01/08 ATR4256 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Analog supply voltage, pin 6 VS 8 to 12 V Input voltage BUS; pins 16, 17 and 18 VI –0.3 to +5.3 V Output current switches; pins 7, 8, 9 and 10 (see Figure 4-8 on page 10) IO –1 to +5 mA Drain voltage switches; pins 7, 8, 9 and 10 VOD 15 V Ambient temperature range Tamb –40 to +85 °C Storage temperature range Tstg –40 to +125 °C Junction temperature Electrostatic handling M.M. Tj 125 °C VESD 300 V Symbol Value Unit RthJA 140 K/W 8. Thermal Resistance Parameters Junction ambient, when soldering to PCB 9. Operating Range All voltages are referred to GND (Pin 11) Parameters Symbol Min. Typ. Max. Unit VS 8 8.5 12 V Tamb –40 +85 °C Input frequency FMOSCIN, pin 19 fin 15 160 MHz Programmable N, R divider SF 2 65535 fXTAL 0.1 15 Supply voltage range, pin 6 Ambient temperature Crystal reference oscillator, pins 12 and 13 MHz 15 4867D–AUDR–01/08 10. Electrical Characteristics Test Conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C. No. 1 1.1 2 2.1 3 3.1 4 Parameters Min. Typ. Max. Unit Type* 6 VS 8 8.5 12 V A 6 IS 5 10 25 mA A f = 0.1 to 15 MHz 13 OSC 100 mVrms B At pin15: 47 pF and 1 kΩ 15 VMX2LO 80 120 200 mVpp B 15 VMX2LO 1.8 2.0 2.2 V A 19 FMOSC FMOSC 40 150 mVrms mVrms B B Supply Current Analog supply current OSCIN Input voltage OSC Buffer (MX2LO) 4.2 Output DC voltage 6 Symbol Analog supply voltage Output AC voltage 5.1 Pin Supply Voltage 4.1 5 Test Conditions FMOSCIN Input voltage f = 15 to 120 MHz f = 120 to 160 MHz Pulsed Current Output PD 6.1 Output current B71 to B70 = “00” PD = 2.5V 2 ±IPD 20 25 30 µA A 6.2 Output current B71 to B70 = “01” PD = 2.5V 2 ±IPD 80 100 120 µA A 6.3 Output current B71 to B70 = “10” PD = 2.5V 2 ±IPD 400 500 600 µA A 6.4 Output current B71 to B70 = “11” PD = 2.5V 2 ±IPD 1500 2000 2400 µA A 6.5 Leakage current PD = 2.5V 2 ±IPDL 20 nA A 7 PDO 7.1 Saturation voltage HIGH 3, 4 8.0 8.5 V A 7.2 Saturation voltage LOW 3, 4 0 0.4 V A 100 nA A 400 mV A 1 mA C VS – 0.6 V A 8 SWO1, SWO2, SWO3, SWO4 (Open Drain) 8.1 Output leakage current HIGH Pin 7, 8, 9, 10 over R against 8.5V 7, 8, 9, 10 ISWOH 8.2 Output voltage LOW I = 1 mA 7, 8, 9, 10 VSWOL 100 9 DAC1, DAC2 9.1 Output current 3, 4 IDAC1, 2 9.2 Output voltage 3, 4 VDAC1, 2 9.3 Maximum offset range (FM) Offset = 0, Gain = 53 3, 4 0.45 0.56 0.65 V A 9.4 Minimum offset range (FM) Offset = 63, Gain = 53 3, 4 –0.45 –0.57 –0.65 V A 0.3 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATR4256 4867D–AUDR–01/08 ATR4256 10. Electrical Characteristics (Continued) Test Conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C. No. Parameters Test Conditions Pin 9.5 Maximum gain range (FM) Gain = 255, Offset = 31 9.6 Minimum gain range (FM) Gain = 0, Offset = 31 10 DAC3 Symbol Min. Typ. Max. Unit Type* 3, 4 0.63 0.69 0.75 A 3, 4 2.1 2.16 2.23 A 10.1 Output current 5 IDAC3 1 mA C 10.2 Output voltage B68 to B66 = “000” 5 VDAC3 0.4 0.55 0.7 V A 10.3 Output voltage B68 to B66 = “001” 5 VDAC3 1.1 1.25 1.4 V A 10.4 Output voltage B68 to B66 = “010” 5 VDAC3 1.8 1.90 2.1 V A 10.5 Output voltage B68 to B66 = “011” 5 VDAC3 2.4 2.60 2.8 V A 10.6 Output voltage B68 to B66 = “100” 5 VDAC3 3.2 3.30 3.5 V A 10.7 Output voltage B68 to B66 = “101” 5 VDAC3 3.8 4.10 4.3 V A 10.8 Output voltage B68 to B66 = “110” 5 VDAC3 4.5 4.80 5.0 V A Output voltage B68 to B66 = “111” 5 VDAC3 5.2 5.45 5.7 V A VBUSH VBUSL 2.7 –0.3 5.3 +0.8 V V A 1.0 MHz A ns ns D 10.9 11 3-wire Bus, ENABLE, DATA, CLOCK 11.1 Input voltage HIGH LOW 11.2 Clock frequency 17 11.3 Period of CLK HIGH LOW 17 11.4 Rise time EN, DATA, CLK 16 to 18 tr 400 ns D 11.5 Fall time EN, DATA, CLK 16 to 18 tf 100 ns D 11.6 Set-up time 16 to 18 ts 100 ns D 11.7 Hold time EN 18 tHEN 250 ns D 11.8 Hold time DATA 16 tHDA 0 ns D 16 to 18 tH tL 250 250 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 17 4867D–AUDR–01/08 Figure 10-1. Application Circuit EN CLK DATA GND C12 100 nF C9 R5 (1) (1) 5.1k (1) depends on crystal C8 47 pF 19 20 C1 18 17 R2 16 10.25 MHz 15 14 13 12 11 OSC BUS 600 10 pF LOGIC fOSC FM VCO Switches DACs 1 Vtune 2 3 5 4 6 R4 8.2k C6 C15 330 pF C14 C7 10 nF C4 10 nF 10 nF 7 8 9 10 SWO1 SWO2 SWO3 SWO4 C5 C16 100 nF 100 mF R3 10 nF DAC1 100 DAC2 DAC3 VS 8V to 12V 18 ATR4256 4867D–AUDR–01/08 4867D–AUDR–01/08 Ant FM 75Ω R307 47 T111 J109 T302 BC848 C311 100n D302 S391D BC 858C T301 T102 BC858 S391D 4µ7 L301 10n 220n D301 C302 2k2 R308 R105 100 100 µH C315 R306 470k 220n C316 L303 2m2 2k2 R311 6p8 C319 L302 R104 470 F102 68k R102 390 R313 470n C111 C112 10µ 2µ2 C106 L102 R112 47k R103 1k 10n C117 R115 1k 12p C306 3p9 C102 T101 BFR93A 10p C56 S391D 10n D103 C103 D101 2 F101 10n C104 18p BB804 27p 6p8 C107 1n C108 C109 1 44 100p 43 F201 C in F201 BB804 D102 C113 100n 10n C209 R29 10 C110 4n7 3 42 4 41 68k R122 68k R121 C314 10n 10n C307 100n C201 5 40 100n C308 6 39 R34 27 7 38 12 C116 100n C115 100n R151 8k2 14 15 30 22p C152 330p 1n C134 R131 5k6 BB804 F131 47p 1 20 C131 C132 13 31 220n C207 220n C208 32 D131 C133 6p8 220n 11 22µ 10 C114 9 33 X301 ATR4255 10µ 35 34 C205 10n C206 1k5 R305 C203 8 36 470n C204 R111 200k C202 37 1µ KR201 R304 1k3 C158 10n 10n 3 18 17 28 C151 2 19 16 29 KR202 4 17 18 27 20 DAC3 5 10n 21 6 7 14 1n 10n C312 8 13 9 12 Q151 12p* 10 11 12p* 10.25 MHz C153 C154 22 23 F302 R106 10 C157 SWO1 SWO3 SWO2 SWO4 10n 15 100n R303 1k C310 24 C155 ATR4256 16 C309 220n 25 C156 10n 19 26 C159 KF302 GND EN CLK DATA IF2OUT INT DEV MULTIP VS (8.5V to 10.5V) METER ADJAC MPX *depends on Q151 R152 10 10 R407 ATR4256 Figure 10-2. Application Board Schematic 19 11. Ordering Information Extended Type Number Package Remarks ATR4256-TKSY SSO20 Tube ATR4256-TKQY SSO20 Taped and reeled 12. Package Information 5.7 5.3 Package SSO20 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.05 0.25 0.65 5.85 20 0.15 6.6 6.3 11 technical drawings according to DIN specifications 1 10 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 20 Revision No. History 4867D-AUDR-01/08 • Section 9 “Operating Range” on page 15 changed 4867C-AUDR-10/07 • Put datasheet in the newest template • El. Char. table: row 5.1 changed 4867B-AUDR-06/06 • Put data sheet in a new template • Pb-free logo on page 1 deleted ATR4256 4867D–AUDR–01/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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