Cypress CY7C025AV-20AC 3.3v 4k/8k/16k x 16/18 dual-port static ram Datasheet

CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
CER
LBL
LBR
OEL
OER
[1]
I/O8/9L–I/O15/17L
[2]
8/9
8/9
I/O
Control
I/O0L–I/O7/8L
12/13/14
A0L–A11/1213L
Address
Decode
[3]
12/13/14
[3]
[1]
8/9
8/9
I/O
Control
[2]
I/O0L–I/O7/8R
Address
Decode
True Dual-Ported
RAM Array
I/O8/9L–I/O15/17R
12/13/14
[3]
A0R–A11/12/13R
[3]
12/13/14
A0L–A11/12/13L
CEL
OEL
R/WL
SEML [4]
A0R–A11/12/13R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[4]
BUSYL
INTL
UBL
LBL
BUSYR
INTR
UBR
LBR
M/S
Notes:
1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
2. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
3. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised October 12, 2004
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
A7L
A6L
A9L
A8L
UBL
LBL
NC [5]
A11L
A10L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C024AV (4K × 16)
CY7C025AV (8K × 16)
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
A7R
A6R
A5R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
GND
I/O15R
ŒR
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R/WR
GND
SEMR
CER
UBR
LBR
NC[6]
A11R
A10R
A9R
A8R
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
Notes:
5. A12L on the CY7C025AV.
6. A12R on the CY7C025AV.
Document #: 38-06052 Rev. *E
Page 2 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
A7L
A6L
A9L
A8L
UBL
LBL
NC [7]
A11L
A10L
Top View
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
I/O15L
I/O16L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
CY7C0241AV (4K × 18)
CY7C0251AV (8K × 18)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
NC
NC
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O9L I/O7R
I/O8L I/O9R
I/O7L I/O10R
I/O6L I/O11R
I/O5L I/O12R
I/O4L I/O13R
I/O3L I/O14R
I/O2L I/O15R
GND GND
I/O1L I/O16R
I/O0L OER
OEL R/WR
GND
VCC
SEMR
R/WL
CER
SEML
UBR
CEL
LBR
UBL
NC [8]
LBL
A11R
A113L
A10R
A12L
A9R
A11L
A8R
A10L
A7R
A9L
A6R
A8L
A5R
A7L
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
74
2
73
3
72
4
71
5
6
70
69
7
8
68
9
67
10
66
11
65
12
64
13
63
14
62
61
15
60
16
59
17
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CY7C026AV (16K × 16)
NC
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
NC
NC
NC
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
GND
I/O15R
OER
R/WR
GND
SEMR
CER
UBR
LBR
A13R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
Notes:
7. A12L on the CY7C0251AV.
8. A12R on the CY7C0251AVC.
Document #: 38-06052 Rev. *E
Page 3 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
A7L
A6L
A9L
A8L
A11L
A10L
UBL
LBL
A12L
OEL
VCC
R/WL
SEML
CEL
I/O1L
I/O0L
I/O4L
I/O3L
I/O2L
GND
I/O10L
I/O9L
I/O7L
I/O6L
I/O5L
100-Pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C036AV (16K × 18)
NC
NC
NC
A13L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A13R
NC
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
I/O15R
GND
I/O16R
OER
R/WR
GND
SEMR
CER
UBR
LBR
A12R
A11R
A10R
A9R
A8R
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A7R
A6R
A5R
NC
NC
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
I/O15L
I/O16L
Selection Guide
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-25
Unit
Maximum Access Time
20
25
ns
Typical Operating Current
120
115
mA
Typical Standby Current for ISB1
(Both ports TTL Level)
35
30
mA
Typical Standby Current for ISB3
(Both ports CMOS Level)
10
10
µA
Document #: 38-06052 Rev. *E
Page 4 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable.
R/WL
R/WR
Read/Write Enable.
OEL
OER
Output Enable.
A0L–A13L
A0R–A13R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for
16K).
I/O0L–I/O17L
I/O0R–I/O17R
Data Bus Input/Output.
SEML
SEMR
Semaphore Enable.
UBL
UBR
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18
devices).
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18
devices).
INTL
INTR
Interrupt Flag.
BUSYL
BUSYR
Busy Flag.
M/S
Master or Slave Select.
VCC
Power.
GND
Ground.
NC
No Connect.
Architecture
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV consist of an array of 4K, 8K, and 16K words of 16 and
18 bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
Functional Description
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV
/036AV are low-power CMOS 4K, 8K, and 16K ×16/18
dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 16/18-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
32/36-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
Document #: 38-06052 Rev. *E
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are available in 100-pin Thin Quad Plastic Flatpacks
(TQFP).
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Page 5 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Interrupts
Semaphore Operation
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for
the CY7C026AV/36AV) is the mailbox for the right port and the
second-highest memory location (FFE for the CY7C024AV/
41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the
CY7C026AV/36AV) is the mailbox for the left port. When one
port writes to the other port’s mailbox, an interrupt is generated
to the owner. The interrupt is reset when the owner reads the
contents of the mailbox. The message is user defined.
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV provide eight semaphore latches, which are separate
from the dual-port memory locations. Semaphores are used to
reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request input
pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV provide on-chip arbitration to resolve simultaneous
memory location access (contention). If both ports’ CEs are
asserted and an address match occurs within tPS of each
other, the busy logic will determine which port has access. If
tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address
match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Document #: 38-06052 Rev. *E
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within tSPS of each other, the
semaphore will definitely be obtained by one side or the other,
but there is no guarantee which side will control the
semaphore.
Page 6 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O9–I/O17
I/O0–I/O8
H
X
X
X
X
H
X
X
X
H
H
H
High Z
High Z
Deselected: Power-Down
L
L
X
L
H
H
Data In
High Z
Write to Upper Byte Only
L
L
X
H
L
H
High Z
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
High Z
Read Upper Byte Only
L
H
L
H
L
H
High Z
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
High Z
Operation
High Z
Deselected: Power-Down
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[9]
Left Port
Function
R/WL
CEL
Right Port
OEL
A0L–13L
INTL
R/WR
CER
OER
A0R–13R
INTR
X
X
X
X
X
L[11]
Set Right INTR Flag
L
L
X
FFF[12]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
FFF (or 1/3FFF)
H[10]
X
X
L[10]
L
L
X
1FFE (or 1/3FFE)
X
L
1FFE[12]
H[11]
X
X
X
X
X
Set Left INTL Flag
Reset Left INTL Flag
X
X
X
L
Table 3. Semaphore Operation Example
Function
I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Notes:
9. See Functional Description for specific highest memory locations by device.
10. If BUSYR=L, then no change.
11. If BUSYL=L, then no change.
12. See Functional Description for specific addresses by device.
Document #: 38-06052 Rev. *E
Page 7 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
DC Input Voltage[14]............................... –0.5V to VCC + 0.5V
Maximum Ratings [13]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
Storage Temperature ................................. –65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VCC + 0.5V
Ambient Temperature
VCC
Commercial
Range
0°C to +70°C
3.3V ± 300 mV
Industrial[15]
–40°C to +85°C
3.3V ± 300 mV
Electrical Characteristics Over the Operating Range
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Parameter
Description
Min.
2.4
VOH
Output HIGH Voltage (VCC=3.3V)
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Typ.
-25
Max.
Min.
Typ.
Max.
Unit
2.4
V
0.4
2.0
0.4
V
0.8
V
2.0
V
0.8
IOZ
Output Leakage Current
–10
10
–10
10
µA
IIX
Input Leakage Current
–10
10
–10
10
µA
ICC
Operating Current (VCC = Max., IOUT = 0
mA) Outputs Disabled
Com’l.
Standby Current (Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
Com’l.
ISB1
ISB2
ISB3
ISB4
120
175
Ind.[15]
35
45
Ind.[15]
Standby Current (One Port TTL Level) CEL Com’l.
| CER ≥ VIH, f = fMAX
Ind.[15]
75
Standby Current (Both Ports CMOS Level) Com’l.
CEL & CER ≥ VCC−0.2V, f = 0
Ind.[15]
10
Standby Current (One Port CMOS Level) Com’l.
CEL | CER ≥ VIH, f = fMAX[16]
Ind.[15]
70
110
500
95
115
165
mA
135
185
mA
30
40
mA
40
50
mA
65
95
mA
75
105
mA
10
500
µA
10
500
µA
60
80
mA
70
90
mA
Capacitance[17]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
10
pF
10
pF
Notes:
13. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
14. Pulse width < 20 ns.
15. Industrial parts are available in CY7C026AV and CY7C036AV only.
16. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
17. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06052 Rev. *E
Page 8 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
AC Test Loads and Waveforms
3.3V
3.3V
R1 = 590Ω
OUTPUT
OUTPUT
C = 30 pF
RTH = 250Ω
R1 = 590Ω
OUTPUT
C = 30pF
R2 = 435Ω
C = 5 pF
R2 = 435Ω
VTH = 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
10%
GND
90%
90%
10%
≤ 3 ns
≤ 3 ns
Switching Characteristics Over the Operating Range [18]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Parameter
Description
Min.
-25
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
20
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[19]
CE LOW to Data Valid
20
25
ns
tDOE
OE LOW to Data Valid
12
13
ns
tLZOE[20, 21, 22]
tHZOE[20, 21, 22]
tLZCE[20, 21, 22]
tHZCE[20, 21, 22]
tPU[22]
tPD[22]
tABE[19]
OE Low to Low Z
20
3
CE LOW to Power-Up
25
3
ns
15
3
12
0
ns
ns
3
12
CE HIGH to High Z
ns
3
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
ns
15
0
ns
ns
CE HIGH to Power-Down
20
25
ns
Byte Enable Access Time
20
25
ns
Write Cycle
tWC
Write Cycle Time
20
25
ns
tSCE[19]
CE LOW to Write End
15
20
ns
tAW
Address Valid to Write End
15
20
ns
tHA
Address Hold From Write End
0
0
ns
tSA[19]
Address Set-up to Write Start
0
0
ns
tPWE
Write Pulse Width
15
20
ns
tSD
Data Set-up to Write End
15
15
ns
Notes:
18. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
19. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
20. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
21. Test conditions used are Load 3.
22. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
Document #: 38-06052 Rev. *E
Page 9 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics Over the Operating Range (continued)[18]
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20
Parameter
Description
Min.
-25
Max.
0
Min.
Max.
Unit
15
ns
tHD
Data Hold From Write End
tHZWE[21, 22]
R/W LOW to High Z
0
ns
tLZWE[21, 22]
R/W HIGH to Low Z
tWDD[23]
Write Pulse to Data Delay
45
50
ns
tDDD[23]
Write Data Valid to Read Data Valid
30
35
ns
12
3
0
ns
Busy Timing[24]
tBLA
BUSY LOW from Address Match
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
20
20
ns
tBLC
BUSY LOW from CE LOW
20
20
ns
tBHC
BUSY HIGH from CE HIGH
17
17
ns
tPS
Port Set-up for Priority
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
tBDD[25]
BUSY HIGH to Data Valid
Interrupt
17
ns
20
25
ns
Timing[24]
tINS
INT Set Time
20
20
ns
tINR
INT Reset Time
20
20
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
5
ns
tSPS
SEM Flag Contention Window
5
tSAA
SEM Address Access Time
Data Retention Mode
The CY7C024AV/025AV/ 026AV and CY7C0241AV/ 0251AV/
036AV are designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
5
ns
20
25
ns
Timing
Data Retention Mode
VCC
3.0V
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
CE
tRC
V
IH
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0V).
Parameter
ICCDR1
Test Conditions[26]
@ VCCDR = 2V
Max.
Unit
50
µA
Notes:
23. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
24. Test conditions used are Load 2.
25. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
26. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06052 Rev. *E
Page 10 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[27, 28, 29]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2 (Either Port CE/OE Access)[27, 30, 31]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[27, 29, 30, 31]
tRC
ADDRESS
tOHA
tAA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes:
27. R/W is HIGH for read cycles.
28. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
29. OE = VIL.
30. Address valid prior to or coincident with CE transition LOW.
31. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06052 Rev. *E
Page 11 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Write Cycle No.1: R/W Controlled Timing[32, 33, 34, 35]
tWC
ADDRESS
tHZOE [38]
OE
tAW
CE
[36, 37]
tPWE[35]
tSA
tHA
R/W
tHZWE[38]
DATA OUT
tLZWE
NOTE 39
NOTE 39
tSD
tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[32, 33, 34, 40]
tWC
ADDRESS
tAW
CE
[36, 37]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes:
32. R/W must be HIGH during all address transitions.
33. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
34. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
35. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
36. To access RAM, CE = VIL, SEM = VIH.
37. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
38. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
39. During this period, the I/O pins are in the output state, and input signals must not be applied.
40. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06052 Rev. *E
Page 12 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[41]
tOHA
tSAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[42, 43, 44]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes:
41. CE = HIGH for the duration of the above timing (both write and read cycle).
42. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
43. Semaphores are reset (available to both ports) at cycle start.
44. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06052 Rev. *E
Page 13 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[45]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note:
45. CEL = CER = LOW.
Document #: 38-06052 Rev. *E
Page 14 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[46]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSYL
Busy Timing Diagram No.2 (Address Arbitration)[46]
Left Address Valid First:
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note:
46. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06052 Rev. *E
Page 15 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE 1FFF (OR 1/3FFF)
tHA[47]
CE L
R/W L
INT R
tINS [48]
Right Side Clears INT R:
tRC
READ 7FFF
(OR 1/3FFF)
ADDRESSR
CE R
tINR [48]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE 1FFE (OR 1/3FFE)
tHA[47]
CE R
R/W R
INT L
tINS[48]
Left Side Clears INT L:
tRC
READ 7FFE
OR 1/3FFE)
ADDRESSR
CE L
tINR[48]
R/W L
OE L
INT L
Notes:
47. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
48. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06052 Rev. *E
Page 16 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
CY7C024AV-20AC
A100
Package Type
100-Pin Thin Quad Flat Pack
Operating
Range
Commercial
CY7C024AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C024AV-25AI
A100
100-Pin Thin Quad Flat Pack
Industrial
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C025AV-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C025AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C025AV-25AI
A100
100-Pin Thin Quad Flat Pack
Industrial
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
CY7C026AV-20AC
A100
Package Type
100-Pin Thin Quad Flat Pack
Operating
Range
Commercial
CY7C026AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C026AV-25AI
A100
100-Pin Thin Quad Flat Pack
Industrial
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C0241AV-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C0241AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C0251AV-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C0251AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C036AV-20AC
A100
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C036AV-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C036AV-25AI
A100
100-Pin Thin Quad Flat Pack
Industrial
Document #: 38-06052 Rev. *E
Page 17 of 19
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06052 Rev. *E
Page 18 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document History Page
Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18
Dual Port Static RAM
Document Number: 38-06052
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
110204
11/11/01
SZV
Change from Spec number: 38-00838 to 38-06052
*A
122302
12/27/02
RBI
Power-up requirements added to Maximum Ratings Information
*B
128958
9/03/03
JFU
Added CY7C025AV-25AI to Ordering Information
*C
237622
See ECN
YDT
Removed cross information from features section
*D
241968
See ECN
WWZ
Added CY7C024AV-25AI to Ordering Information
*E
276451
See ECN
SPN
Corrected x18 for 026AV to x16
Document #: 38-06052 Rev. *E
Page 19 of 19
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