Catalyst CAT25080VI-GT3 8-kb and 16-kb spi serial cmos eeprom Datasheet

CAT25080, CAT25160
8-Kb and 16-Kb SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
„ 10 MHz SPI compatible
The CAT25080/25160 are 8-Kb/16-Kb Serial CMOS
EEPROM
devices
internally
organized
as
1024x8/2048x8 bits. They feature a 32-byte page
write buffer and support the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip
¯¯ ) input. In addition, the required bus signals
Select (CS
are a clock input (SCK), data input (SI) and data
¯¯¯¯¯ input may be used to
output (SO) lines. The HOLD
pause any serial communication with the
CAT25080/25160 device. These devices feature
software and hardware write protection, including
partial as well as full array protection.
„ 1.8V to 5.5V supply voltage range
„ SPI modes (0,0) & (1,1)
„ 32-byte page write buffer
„ Self-timed write cycle
„ Hardware and software protection
„ Block write protection
– Protect 1/4, 1/2 or entire EEPROM array
„ Low power CMOS technology
„ 1,000,000 program/erase cycles
„ 100 year data retention
„ Industrial temperature range
„ RoHS-compliant 8 lead PDIP, SOIC, TSSOP and
8-pad TDFN, UDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V)
TSSOP (Y)
TDFN (VP2)
UDFN (HU2)
¯¯
CS
1
8 VCC
SO
2
¯¯¯¯¯
7 HOLD
¯¯¯
WP
3
6 SCK
VSS
4
5 SI
VCC
SI
CS
WP
Function
¯¯
CS
Chip Select
SO
Serial Data Output
¯¯¯
WP
Write Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock
¯¯¯¯¯
HOLD
Hold Transmission Input
VCC
Power Supply
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SO
HOLD
SCK
PIN FUNCTION
Pin Name
CAT25080
CAT25160
GND
For Ordering Information details, see page 16.
1
Doc. No. 1122 Rev. A
CAT25080, CAT25160
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
–65 to +150
ºC
–0.5 to VCC + 0.5
V
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND(4)
TDR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, TA=-40°C to +85°C unless otherwise specified.
Symbol Parameter
ICC
Supply Current
Test Conditions
Min
Read, Write, VCC = 5.0V, fSCK = 10MHz,
SO open
Max
2
Units
mA
ISB1
Standby Current
¯¯ = VCC , ¯¯¯
WP = VCC,
VIN = GND or VCC , CS
VCC = 5.0V
2
µA
ISB2
Standby Current
¯¯ = VCC , ¯¯¯
WP = GND,
VIN = GND or VCC , CS
VCC = 5.0V
4
µA
VIN = GND or VCC
IL
Input Leakage Current
ILO
¯¯ = VCC , VOUT = GND or VCC
Output Leakage Current CS
-2
2
µA
-1
1
µA
VIL
Input Low Voltage
-0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC + 0.5
V
VOL1
Output Low Voltage
VCC > 2.5V, IOL = 3.0mA
0.4
V
VOH1
Output High Voltage
VCC > 2.5V, IOH = -1.6mA
VOL2
Output Low Voltage
VCC > 1.8V, IOL = 150µA
VOH2
Output High Voltage
VCC > 1.8V, IOH = -100µA
VCC - 0.8V
V
0.2
VCC - 0.2V
V
V
PIN CAPACITANCE(3)
TA = 25˚C, f = 1.0MHz, VCC = +5.0V
Symbol
COUT
CIN
Test
Conditions
Output Capacitance (SO)
¯¯ , SCK, SI, ¯¯¯,
¯¯¯¯¯)
Input Capacitance (CS
WP HOLD
Min
Typ
Max
Units
VOUT = 0V
8
pF
VIN = 0V
8
pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is
not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and
JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. 1122 Rev. A
2
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
A.C. CHARACTERISTICS
TA = -40°C to +85°C, unless otherwise specified.(1)
VCC = 1.8V-5.5V
Symbol
VCC = 2.5V-5.5V
Parameter
Min.
Max.
Min.
Max.
Units
fSCK
Clock Frequency
DC
5
DC
10
MHz
tSU
Data Setup Time
30
20
ns
tH
Data Hold Time
30
20
ns
tWH
SCK High Time
75
40
ns
tWL
SCK Low Time
75
40
ns
tLZ
¯¯¯¯¯ to Output Low Z
HOLD
50
25
ns
tRI(2)
tFI(2)
Input Rise Time
2
2
µs
Input Fall Time
2
2
µs
tHD
¯¯¯¯¯ Setup Time
HOLD
0
0
ns
tCD
¯¯¯¯¯ Hold Time
HOLD
10
10
ns
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
50
20
ns
tHZ
¯¯¯¯¯ to Output High Z
HOLD
100
25
ns
tCS
¯¯ High Time
CS
50
15
ns
tCSS
¯¯ Setup Time
CS
50
15
ns
tCSH
¯¯ Hold Time
CS
50
15
ns
tWPS
¯¯¯
WP Setup Time
10
10
ns
tWPH
¯¯¯
WP Hold Time
10
10
ns
tWC(4)
Write Cycle Time
75
0
40
0
ns
ns
5
5
ms
Power-Up Timing(2)(3)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
Units
1
1
ms
ms
Notes:
(1) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
¯¯ after a valid write sequence to the end of the internal write cycle.
(4) tWC is the time from the rising edge of CS
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1122 Rev. A
CAT25080, CAT25160
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
The CAT25080/160 devices support the Serial Periphe–
ral Interface (SPI) bus protocol, modes (0,0) and (1,1).
The device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
Reading data stored in the CAT25080/160 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT25080/160, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25080/160.
¯¯ : The chip select input pin is used to enable/disable
CS
¯¯ is high, the SO output is
the CAT25080/160. When CS
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT25080/160 must be preceded by a high to low
transition and concluded with a low to high transition of
¯¯ input.
the CS
¯¯ input pin, the
After a high to low transition on the CS
CAT25080/160 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication proto–
col follows the timing from Figure 1.
¯¯¯:
WP The write protect input pin will allow all write
operations to the device when held high. When ¯¯¯
WP
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
Table 1: Instruction Set
Instruction
¯¯¯¯¯: The ¯¯¯¯¯
HOLD
HOLD input pin is used to pause trans–
mission between host and CAT25080/160, without
having to retransmit the entire sequence at a later
¯¯¯¯¯ must be taken low and to
time. To pause, HOLD
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
pausing, the ¯¯¯¯¯
HOLD input should be tied to VCC,
either directly or through a resistor.
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
Figure 1. Synchronous Data Timing
tCS
V IH
CS
VIL
SCK
VIH
tWL
tWH
VIL
tH
tSU
VIH
SI
tCSH
tCSS
VALID IN
VIL
tRI
tFI
tV
SO
VOH
HI-Z
tHO
tDIS
HI-Z
VOL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
4
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
STATUS REGISTER
user with the WRSR command and are non-volatile.
The user is allowed to protect a quarter, one half or the
entire memory, by setting these bits according to Table
3. The protected blocks then become read-only.
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The ¯¯¯¯
RDY (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically set
to 1 during an internal write cycle, and reset to 0 when
the device is ready to accept commands. For the host,
this bit is read only.
The WPEN (Write Protect Enable) bit acts as an enable
for the ¯¯¯
WP pin. Hardware write protection is enabled
when the ¯¯¯
WP pin is low and the WPEN bit is 1. This
condition prevents writing to the status register and to
the block protected sections of memory. While
hardware write protection is active, only the non-block
protected memory can be written. Hardware write
protection is disabled when the ¯¯¯
WP pin is high or the
WPEN bit is 0. The WPEN bit, ¯¯¯
WP pin and WEL bit
combine to either permit or inhibit Write operations, as
detailed in Table 4.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device is
in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the
Table 2. Status Register
7
6
5
4
3
2
1
0
WPEN
0
0
0
BP1
BP0
WEL
¯¯¯¯
RDY
Table 3. Block Protection Bits
Status Register Bits
BP1
BP0
0
0
0
1
1
0
1
1
Array Address Protected
Protection
None
No Protection
25080: 0300-03FF
25160: 0600-07FF
25080: 0200-03FF
25160: 0400-07FF
25080: 0000-03FF
25160: 0000-07FF
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 4. Write Protect Conditions
WPEN
¯¯¯
WP
WEL
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1122 Rev. A
CAT25080, CAT25160
WRITE OPERATIONS
¯¯ input high after the WREN instruction, as
take the CS
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 2. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The CAT25080/160 device powers up into a write
disable state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to
the memory array or to the status register. In addition,
the address of the memory location(s) to be written
must be outside the protected area, as defined by BP0
and BP1 bits from the status register.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 3. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25080/160. Care must be taken to
Figure 2. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 3. WRDI Timing
CS
SCK
SI
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
6
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16-bit
address and data as shown in Figure 4. Only 10
significant address bits are used by the CAT25080 and
11 by the CAT25160. The rest are don’t care bits, as
shown in Table 5. Internal programming will start after
¯¯ transition. During an internal write
the low to high CS
cycle, all commands, except for RDSR (Read Status
Register) will be ignored. The ¯¯¯¯
RDY bit will indicate if the
¯¯¯¯ high), or the the
internal write cycle is in progress (RDY
¯¯¯¯ low).
device is ready to accept commands (RDY
Page Write
After sending the first data byte to the CAT25080/160,
the host may continue sending data, up to a total of 32
bytes, according to timing shown in Figure 5. After each
data byte, the lower order address bits are automatically
incremented, while the higher order address bits (page
address) remain unchanged. If during this process the
end of page is exceeded, then loading will “roll over” to
the first byte in the page, thus possibly overwriting
previoualy loaded data. Following completion of the
write cycle, the CAT25080/160 is automatically returned
to the write disable state.
Table 5. Byte Address
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25080
A9 - A0
A15 - A10
16
CAT25160
A10 - A0
A15 - A11
16
Figure 4. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
SCK
BYTE ADDRESS*
OPCODE
SI
0
0
0
0
0
0
1
AN
0
DATA IN
A0 D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. Page WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24-31 32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SCK
SI
0
0
0
0
0
DATA IN
BYTE ADDRESS*
OPCODE
0
1
0
AN
A0
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table. (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1122 Rev. A
CAT25080, CAT25160
Write Protection
¯¯¯) pin can be used to protect the
The Write Protect (WP
Block Protect bits BP0 and BP1 against being
inadvertently altered. When ¯¯¯
WP is low and the WPEN
bit is set to “1”, write operations to the Status Register
¯¯ is still low will
are inhibited. ¯¯¯
WP going low while CS
interrupt a write to the status register. If the internal
write cycle has already been initiated, ¯¯¯
WP going low will
have no effect on any write operation to the Status
Register. The ¯¯¯
WP pin function is blocked when the
WPEN bit is set to “0”. The ¯¯¯
WP input timing is shown in
Figure 7.
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 6. Only
bits 2, 3 and 7 can be written using the WRSR
command.
Figure 6. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
DATA IN
0
0
3
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 7. ¯¯¯
WP Timing
t WPS
t WPH
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
8
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
READ OPERATIONS
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25080/160 will shift out the contents
of the status register on the SO pin (Figure 9). The
status register may be read at any time, including during
an internal write cycle.
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by a 16-bit address (see Table 5 for
the number of significant address bits).
After receiving the last address bit, the CAT25080/160
will respond by shifting out data on the SO pin (as
shown in Figure 8). Sequentially stored data can be
read out by simply continuing to run the clock. The
internal address pointer is automatically incremented to
the next higher address as data is shifted out. After
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address, and
the read cycle can be continued indefinitely. The read
¯¯ high.
operation is terminated by taking CS
Figure 8. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
2
1
SCK
BYTE ADDRESS*
OPCODE
SI
0
0
0
0
0
0
1
1
AN
A0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
0
MSB
* Please check the Byte Address Table (Table 5).
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 9. RDSR Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
6
5
11
12
13
14
2
1
SCK
OPCODE
SI
0
0
0
0
0
DATA OUT
SO
HIGH IMPEDANCE
7
4
3
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1122 Rev. A
CAT25080, CAT25160
Hold Operation
The ¯¯¯¯¯
HOLD input can be used to pause communication
¯¯¯¯¯
between host and CAT25080/160. To pause, HOLD
must be taken low while SCK is low (Figure 10). During
¯¯
the hold condition the device must remain selected (CS
low). During the pause, the data output pin (SO) is tristated (high impedance) and SI transitions are ignored.
¯¯¯¯¯ must be taken high
To resume communication, HOLD
while SCK is low.
DESIGN CONSIDERATIONS
The CAT25080/160 devices incorporate Power-On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state. The device will
power up into Standby mode after VCC exceeds the
POR trigger level and will power down into Reset mode
when VCC drops below the POR trigger level. This bidirectional POR behavior protects the device against
‘brown-out’ failure following a temporary loss of power.
The CAT25080/160 device powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued prior any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a
successful byte/page write or status register write, the
device goes into a write disable mode. The CS input
must be set high after the proper number of clock cycles
to start the internal write cycle. Access to the memory
array during an internal write cycle is ignored and
programming is continued. Any invalid op-code will be
ignored and the serial output pin (SO) will remain in the
high impedance state.
¯¯¯¯¯ Timing
Figure 10. HOLD
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1122 Rev. A
10
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
PACKAGE OUTLINES
8-lEAD 300MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
c
A1
L
e
eB
b2
b
SYMBOL
A
A1
A2
b
b2
c
D
E
E1
e
eB
L
MIN
NOM
MAX
4.57
0.38
3.05
0.36
1.14
0.21
9.02
7.62
6.09
0.46
0.26
7.87
6.35
2.54 BSC
7.87
2.92
3.81
0.56
1.77
0.35
10.16
8.25
7.11
9.65
3.81
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions are in millimeters.
(2)
Complies with JEDEC specification MS001
(3)
Dimensioning and tolerancing per ANSI Y14.5M-1982.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1122 Rev. A
CAT25080, CAT25160
8-LEAD 150 MIL SOIC (V)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
A1
A
b
C
D
E
E1
e
h
L
q1
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
1.27 BSC
0.50
1.27
8°
0.25
0.40
0°
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions are in millimeters.
(2)
Complies with JEDEC specification MS-012.
Doc. No. 1122 Rev. A
12
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
4
1
PIN #1 IDENT.
0.25
q1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
q1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0.00
NOM
0.90
3.00
6.4
4.40
0.65 BSC
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8.00
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions are in millimeters.
(2)
Complies with JEDEC Standard MO-153
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1122 Rev. A
CAT25080, CAT25160
8-PAD TDFN (2 x 3mm) PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
SYMBOL
MIN
NOM
MAX
A
A1
A2
A3
b
D
D2
E
E2
e
L
0.70
0.00
0.45
0.75
0.02
0.55
0.20 REF
0.25
2.00
1.40
3.00
1.30
0.50 TYP
0.30
0.80
0.05
0.65
0.20
1.90
1.30
2.90
1.20
0.20
E2
0.30
2.10
1.50
3.10
1.40
0.40
PIN 1 ID
L
b
e
3xe
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
(2)
All dimensions are in millimeters.
Complies with JEDEC specification MO-229.
Doc. No. 1122 Rev. A
14
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25080, CAT25160
8-PAD UDFN (2 x 2mm) PACKAGE (HU2)
DETAIL A
PIN#1
INDENTIFICATION
PIN#1 INDEX AREA
TOP VIEW
SYMBOL
MIN
SIDE VIEW
NOM
BOTTOM VIEW
MAX
DETAIL A
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1)
All dimensions are in millimeters.
(2)
Complies with JEDEC specification MO-229.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 1122 Rev. A
CAT25080, CAT25160
ORDERING INFORMATION
Prefix
Device # Suffix
CAT
25160
V
Company ID
Product Number
25080: 8-Kb
25160: 16-Kb
L:
V:
Y:
VP2:
HU2:
Package
PDIP
SOIC, JEDEC
TSSOP
TDFN (2 x 3mm)
UDFN (2 x 2mm)
I
Temperature Range
I = Industrial (-40ºC to 85ºC)
-G
T3
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Tape & Reel
T: Tape & Reel
3: 3000 units/Reel
Notes:
(1)
All packages are RoHS-compliant (Lead-free, Halogen-free).
(2)
The standard lead finish is NiPdAu.
(3)
The device used in the above example is a CAT25160VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4)
For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. 1122 Rev. A
16
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev.
Comments
12/06/2006
A
Initial Issue
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax:
408.542.1200
www.catsemi.com
Document No: 1122
Revision:
A
Issue date:
12/06/06
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