LINER LTC2383-16 16-bit, 1msps, low power sar adc with serial interface Datasheet

LTC2383-16
16-Bit, 1Msps, Low Power
SAR ADC with Serial Interface
FEATURES
DESCRIPTION
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The LTC®2383-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2383-16 has a
±2.5V fully differential input range. The LTC2383-16
consumes only 13mW and achieves ±2LSB INL max, no
missing codes at 16-bits and 92dB SNR.
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1Msps Throughput Rate
±2LSB INL (Max)
Guaranteed 16-Bit No Missing Codes
Low Power: 13mW at 1Msps, 13μW at 1ksps
92dB SNR (typ) at fIN = 20kHz
Guaranteed Operation to 125°C
2.5V Supply
Fully Differential Input Range ±2.5V
External 2.5V Reference Input
No Pipeline Delay, No Cycle Latency
1.8V to 5V I/O Voltages
SPI-Compatible Serial I/O with Daisy-Chain Mode
Internal Conversion Clock
16-pin MSOP and 4mm × 3mm DFN Packages
The LTC2383-16 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisychain mode. The fast 1Msps
throughput with no cycle latency makes the LTC2383-16
ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2383-16
automatically powers down between conversions, leading to reduced power dissipation that scales with the
sampling rate.
APPLICATIONS
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Medical Imaging
High Speed Data Acquisition
Portable or Compact Instrumentation
Industrial Process Control
Low Power Battery-Operated Instrumentation
ATE
LTC238X-16 SAR ADC Family
PART NUMBER
RESOLUTION
SPEED
POWER
LTC2383-16
16
1Msps
13mW
LTC2382-16
16
500ksps
6.5mW
LTC2381-16
16
250ksps
3.25mW
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
32k Point FFT fS = 1Msps, fIN = 20kHz
2.5V
0
1.8V TO 5V
SNR = 92.2dB
THD = –106.2dB
SINAD = 92dB
SFDR = 110.4dB
–20
50Ω
LT6350
100Ω
IN+
0.1μF
VDD
OVDD
LTC2383-16
3300pF
IN–
50Ω
SINGLE-ENDEDTO-DIFFERENTIAL
DRIVER
100Ω
REF
GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
2.5V
23816 TA01
47μF
(X5R, 0805 SIZE)
–40
SAMPLE CLOCK
AMPLITUDE (dBFS)
10μF
ANALOG INPUT
0V TO 2.5V
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
500
238316 TA02
238316f
1
LTC2383-16
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF)..............................................2.8V
Analog Input Voltage (Note 3)
IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND –0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND –0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2383C ................................................ 0°C to 70°C
LTC2383I .............................................–40°C to 85°C
LTC2383H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
CHAIN
1
VDD
2
GND
3
+
4
IN–
5
GND
6
REF
7
REF
8
IN
16 GND
15 OVDD
17
GND
TOP VIEW
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
14 SDO
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
MS PACKAGE
16-LEAD (4mm s 5mm) PLASTIC MSOP
DE PACKAGE
16-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 110°C/W
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2383CMS-16#PBF
LTC2383CMS-16#TRPBF
238316
16-Lead Plastic MSOP
0°C to 70°C
LTC2383IMS-16#PBF
LTC2383IMS-16#TRPBF
238316
16-Lead Plastic MSOP
–40°C to 85°C
LTC2383HMS-16#PBF
LTC2383HMS-16#TRPBF
238316
16-Lead Plastic MSOP
–40°C to 125°C
LTC2383CDE-16#PBF
LTC2383CDE-16#TRPBF
23836
16-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2383IDE-16#PBF
LTC2383IDE-16#TRPBF
23836
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
238316f
2
LTC2383-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
MIN
(Note 5)
l
VIN –
Absolute Input Range (IN–)
(Note 5)
l
VIN+ – VIN–
Input Differential Voltage range
VIN = VIN+ – VIN–
l
VCM
Common-Mode Input Range
l
VREF/2–
0.05
IIN
Analog Input Leakage Current
l
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
TYP
MAX
UNITS
VREF
V
–0.05
VREF
V
–VREF
+VREF
V
VREF/2+
0.05
V
±1
μA
–0.05
Sample Mode
Hold Mode
VREF/2
45
5
pF
pF
70
dB
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
Resolution
16
Bits
No Missing Codes
l
16
Bits
l
–2
±0.8
2
LSB
LSB
Transition Noise
0.6
(Note 6)
LSBRMS
INL
Integral Linearity Error
DNL
Differential Linearity Error
l
–1
±0.4
1
Bipolar Zero-Scale Error
l
–6
±0.25
6
BZE
(Note 7)
Bipolar Zero-Scale Error Drift
FSE
UNITS
l
Bipolar Full-Scale Error
3
(Note 7)
l
–14
Bipolar Full-Scale Error Drift
±3
LSB
mLSB/°C
14
±0.1
LSB
ppm/°C
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER
CONDITIONS
SINAD
fIN = 20kHz
Signal-to-(Noise + Distortion) Ratio
MIN
TYP
l
88.5
92
89
SNR
Signal-to-Noise Ratio
fIN = 20kHz
l
THD
Total Harmonic Distortion
fIN = 20kHz, First 5 Harmonics
l
Spurious Free Dynamic Range
fIN = 20kHz
SFDR
MAX
dB
92
–106
UNITS
dB
–99
dB
108
dB
–3dB Input Bandwidth
30
MHz
Aperture Delay
2
ns
30
ps
250
ns
Aperture Jitter
Transient Response
Full-Scale Step
238316f
3
LTC2383-16
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VREF
Reference Voltage
(Note 5)
l
MIN
IREF
Load Current
(Note 9)
l
TYP
2.4
MAX
UNITS
2.6
V
910
μA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
TYP
MAX
UNITS
0.8 • OVDD
VIN = 0V to OVDD
l
–10
OVDD – 0.2
V
0.2 • OVDD
V
10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500 μA
l
5
pF
VOL
Low Level Output Voltage
IO = 500 μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
V
–10
0.2
V
10
μA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
Supply Voltage
CONDITIONS
l
OVDD
Supply Voltage
IDD
Supply Current
Power Down Mode
Power Down Mode
1Msps Sample Rate
Conversion Done
Conversion Done (H-Grade)
PD
Power Dissipation
Power Down Mode
Power Down Mode
1Msps Sample Rate
Conversion Done
Conversion Done (H-Grade)
MIN
TYP
MAX
UNITS
2.375
2.5
2.625
V
1.71
l
l
l
5.25
V
5.2
0.5
0.5
6.5
40
110
mA
μA
μA
13
1.25
1.25
16.25
100
275
mW
μW
μW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
tCONV
Conversion Time
tACQ
Acquisition Time
tCYC
Time Between Conversions
CONDITIONS
MIN
l
tACQ = tCYC –tCONV – tBUSYLH (Note 10)
TYP
MAX
UNITS
1
Msps
l
610
l
250
ns
l
1
us
l
20
730
ns
tCNVH
CNV High Time
tBUSYLH
CNV ↑ to BUSY Delay
CL = 20pF (Note 11)
l
ns
tCNVL
Minimum Low Time for CNV
(Note 11)
l
200
tSCK
SCK Period
(Notes 11, 12)
l
10
ns
tSCKH
SCK High Time
l
4
ns
20
ns
ns
238316f
4
LTC2383-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
tSCKL
SCK Low Time
CONDITIONS
tSSDISCK
SDI Setup Time From SCK ↑
tHSDISCK
tSCKCH
MIN
TYP
MAX
UNITS
l
4
ns
(Note 11)
l
4
ns
SDI Hold Time From SCK ↑
(Note 11)
l
1
ns
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
tDSDO
SDO Data Valid Delay from SCK ↑
CL = 20pF (Note 11)
l
tHSDO
SDO Data Remains Valid Delay from SCK ↑
CL = 20pF (Note 10)
l
tDSDOBUSYL
9.5
1
ns
ns
SDO Data Valid Delay from BUSY ↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL ↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL ↑
(Note 11)
l
13
ns
tSSCKRDL
SCK Setup Time from RDL/SDI ↓
(Note 10)
l
1
ns
(Note 10)
l
16
ns
tHSCKRDL
SCK Hold Time from RDL/SDI ↓
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 1MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±2.5V input with
a 2.5V reference voltage.
Note 9: fSMPL = 1MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tWIDTH
0.2*OVDD
tDELAY
tDELAY
0.8*OVDD
0.8*OVDD
0.2*OVDD
0.2*OVDD
50%
50%
238316F01
Figure 1. Voltage Levels for Timing Specifications
238316f
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LTC2383-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
fSMPL = 1Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
1600000
1.0
2.0
1400000
1.5
DNL ERROR (LSB)
0.5
0.0
–0.5
1000000
COUNTS
INL ERROR (LSB)
1200000
0.5
1.0
0.0
600000
400000
–1.0
–0.5
200000
–1.5
–2.0
0
32766
–1.0
16384
32768
49152
OUTPUT CODE
65536
0
16384
32768
49152
OUTPUT CODE
238316 G01
–60
–80
92
–85
–80
–100
–120
88
87
–160
86
–180
100
200
300
FREQUENCY (kHz)
400
85
500
SINAD
89
–140
0
SNR
90
32769
32770
THD, Harmonics
vs Input Frequency
93
91
SNR, SINAD (dBFS)
–40
32768
CODE
238316 G03
SNR, SINAD vs Input Frequency
SNR = 92.2dB
THD = –106.2dB
SINAD = 92dB
SFDR = 110.4dB
–20
32767
238316 G02
32k Point FFT fS = 1Msps,
fIN = 20kHz
0
65536
HARMONICS, THD (dBFS)
0
AMPLITUDE (dBFS)
800000
–90
–95
–100
THD
–105
–110
2ND
–115
–120
3RD
–125
0
25
50
–130
75 100 125 150 175 200
FREQUENCY (kHz)
0
25
50
75 100 125 150 175 200
FREQUENCY (kHz)
238316 G05
238316 G06
238316 G04
SNR, SINAD vs Input level,
fIN = 20kHz
SNR, SINAD vs Temperature
THD, Harmonics vs Temperature
94.00
93.0
–100.00
HARMONICS, THD (dBFS)
93.50
SNR
SINAD
SNR, SINAD (dBFS)
SNR, SINAD (dBFS)
92.5
92.0
93.00
92.50
92.00
SNR
SINAD
91.5
–105.00
THD
2ND
–110.00
3RD
–115.00
91.50
91.0
–40
–30
–20
–10
INPUT LEVEL (dB)
0
238316 G07
91.00
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (ºC)
238316 G08
–120.00
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (ºC)
3653 G03
238316f
6
LTC2383-16
TYPICAL PERFORMANCE CHARACTERISTICS
fSMPL = 1Msps, unless otherwise noted.
INL/DNL vs Temperature
Full-Scale Error vs Temperature
FULL-SCALE ERROR (LSB)
MAX INL
INL/DNL ERROR (LSB)
Offset Error vs Temperature
0.3
2.5
0.5
MAX DNL
0
MIN DNL
–0.5
MIN INL
–1
–55 –35 –15
2.0
–FS
1.5
+FS
1.0
Supply Current vs Temperature
1
IREF
Supply Current vs Sampling Rate
6
IVDD + IOVDD + IREF
25
POWER SUPPLY CURRENT (mA)
POWER-DOWN CURRENT (μA)
IVDD
2
5 25 45 65 85 105 125
TEMPERATURE (°C)
238316 G12
Shutdown Current vs Temperature
30
3
0
238316 G11
6
4
0.1
–0.1
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
238316 G10
5
0.2
0.5
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
OFFSET ERROR (LSB)
1
POWER SUPPLY CURRENT (mA)
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
20
15
10
5
5
4
3
2
1
IOVDD
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
238316 G13
0
–55 –35 –15
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0
200
400
600
800
SAMPLING RATE (kHz)
1000
238316 G14
238316 G15
238316f
7
LTC2383-16
PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2383-16 operates in Normal Mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2383-16 operates in Chain Mode and the RDL/SDI
pin functions as SDI, the daisychain serial data input.
RDL/SDI (Pin 12): When CHAIN is low, the part is in Normal
Mode and the pin is treated as a bus enabling input. When
CHAIN is high, the part is in chain mode and the pin is
treated as a serial data input pin where data from another
ADC in the daisychain is input.
VDD (Pin 2): 2.5V Digital Power Supply. The range of
VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10μF
ceramic capacitor.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisychain data from another ADC
is shifted out on the rising edges of this clock MSB first.
GND (Pins 3, 6, 10 and 16): Ground.
SDO (Pin 14): Serial Data Output. The conversion result or
daisychain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pins 7, 8): Reference Input. The range of REF is 2.4V
to 2.6V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47μF ceramic capacitor
(X5R, 0805 size).
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
CNV (Pin 9): Convert Input. A rising edge on this input
initiates a new conversion. When the conversion is done,
the part powers down as long as CNV is held high. When
CNV is returned low, the part powers up in preparation
for the next conversion.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground
plane.
BUSY (Pin 11): BUSY indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished.
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 2.5V
OVDD = 1.8V to 5V
LTC2383-16
IN+
+
16-BIT SAMPLING ADC
IN–
SPI
PORT
–
CONTROL LOGIC
CHAIN
SDO
RDL/SDI
SCK
CNV
BUSY
GND
238316 BD01
238316f
8
LTC2383-16
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
POWER-UP
POWER-DOWN
CNV
ACQUIRE
BUSY
CONVERT
SCK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
238316 TD02
238316f
9
LTC2383-16
OVERVIEW
The LTC2383-16 is a low noise, low power, high speed 16-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2383-16 supports a
large ±2.5V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2383-16 achieves ±2LSB INL max,
no missing codes at 16-bits and 92dB SNR.
Fast 1Msps throughput with no cycle latency makes the
LTC2383-16 ideally suited for a wide variety of high speed
applications. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2383-16
dissipates only 13mW at 1Msps, while an auto power-down
feature is provided to further reduce power dissipation
during inactive periods.
CONVERTER OPERATION
The LTC2383-16 operates in two phases. During the
acquisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins
to sample the differential analog input voltage. A rising
edge on the CNV pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/65536) using
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 16-bit digital output
code for serial transfer.
OUTPUT CODE (TWO’S COMPLEMENT)
APPLICATIONS INFORMATION
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
–FSR/2
238316 F02
Figure 2. LTC2383-16 Transfer Function
circuit shown in Figure 3. The diodes at the input provide
ESD protection. In the acquisition phase, each input sees
approximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
the CIN capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
REF
RON
CIN
IN+
BIAS
VOLTAGE
REF
IN–
RON
CIN
TRANSFER FUNCTION
The LTC2383-16 digitizes the full-scale voltage of 2 × REF
into 216 levels, resulting in an LSB size of 76μV with
REF = 2.5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
ANALOG INPUT
The analog inputs of the LTC2383-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent
238316 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2383-16
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high
impedance inputs of the LTC2383-16 without gain error.
A high impedance source should be buffered to minimize
settling time during acquisition and to optimize the
distortion performance of the ADC. Minimizing settling
238316f
10
LTC2383-16
APPLICATIONS INFORMATION
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2383-16. The amplifier
provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC inputs draw.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
Another filter network consisting of LPF2 and the 100Ω series
input resistors should be used between the buffer and ADC
inputs to both minimize the noise contribution of the buffer
and to help minimize disturbances reflected into the buffer
from sampling transients. Long RC time constants at the
analog inputs will slow down the settling of the analog inputs.
Therefore, LPF2 requires a wider bandwidth than LPF1. A
buffer amplifier with a low noise density must be selected to
minimize degradation of the SNR. With the 482kHz lowpass
filter shown in Figure 4, the LT6350 provides the full data
sheet performance of the LTC2383-16.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
LPF2
50Ω
SINGLE-ENDEDINPUT SIGNAL LPF1
500Ω
LT6350
100Ω
IN+
3300pF
6600pF
50Ω
100Ω
SINGLE-ENDED- BW = 482kHz
BW = 48kHz TO-DIFFERENTIAL
DRIVER
LTC2383-16
IN–
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2383-16. The LT6350 ADC
driver is recommended for performing single-ended-todifferential conversions.The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±2.5V differential input range of the
LTC2383-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2383-16 up to 125°C.
Figure 5 shows the LT6350 being used to convert a 0V
to 2.5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the singleended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5a,
the LT6350 drives the LTC2383-16 to full datasheet
performance without degrading the SNR or THD .
LT6350
8
0V to 2.5V
1
+
–
RINT
4
OUT1
0V to
2.5V
5
OUT2
2.5V to
0V
RINT
2
+
–
–
+
VCM = VREF/2
238316 F05
Figure 5. LT6350 Converting a 0V-2.5V Single-Ended Signal
to a ±2.5V Differential Input Signal
0
SNR = 92.2dB
THD = –106.2dB
SINAD = 92dB
SFDR = 110.4dB
–20
–40
AMPLITUDE (dBFS)
time is important even for DC inputs, because the ADC
inputs draw a current spike when entering acquisition.
–60
–80
–100
–120
–140
–160
238316 F04
–180
0
100
200
300
FREQUENCY (kHz)
400
500
238316 F05a
Figure 4. Input Signal Chain
Figure 5a. 32k Point FFT Plot for Circuit Shown in Figure 5
238316f
11
LTC2383-16
APPLICATIONS INFORMATION
The LT6350 can also be used to buffer and convert singleended signals larger than the input range of the LTC2383-16
in order to maximize the signal swing that can be digitized.
Figure 6 shows the LT6350 converting a 0V-5V single-ended
input signal to the ±2.5V differential input range of the
LTC2383-16. In this case, the first amplifier in the LT6350
is configured as an inverting amplifier stage, which acts to
attenuate the input signal down to the 0V-2.5V input range
of the LTC2383-16. In the inverting amplifier configuration,
the single-ended input signal source no longer directly
drives a high impedance input of the first amplifier. The
input impedance is instead set by resistor RIN. RIN must
be chosen carefully based on the source impedance of the
signal source. Higher values of RIN tend to degrade both
the noise and distortion of the LT6350 and LTC2383-16 as a
system. R1, R2 and R3 must be selected in relation to RIN to
achieve the desired attenuation and to maintain a balanced
input impedance in the first amplifier. Table 1 shows the
Table 1. SNR, THD vs RIN for 0-5V Single-Ended Input Signal.
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k
1k
1k
2k
665
92
–101
10k
5k
5k
10k
3.3k
91
–100
100k
50k
50k
100k
16k
91
–94
R2 = 1.24k
200pF
R2 = 1k
150pF
LT6350
4
8
R4 = 665Ω
R3 = 2k
+
–
RINT
1
RIN = 2k
2
R1 = 1k
0V to 5V
OUT1
RINT
–
+
5
OUT2
2.5V to
0V
RIN = 10k
238316 F06
±10V
–60
–80
–100
–120
2
R1 = 1.24k
4
OUT1
2.5V to
0V
5
OUT2
0V to
2.5V
RINT
+
–
–
+
VCM = VREF/2
238316 F07
Figure 7. LT6350 Converting a ±10V Single-Ended Signal to
a ±2.5V Differential Input Signal
0
SNR = 92dB
THD = –97dB
SINAD = 91.2dB
SFDR = 99.7dB
–20
–40
–60
–80
–100
–120
–140
–140
–160
–160
–180
RINT
220pF
AMPLITUDE (dBFS)
–40
+
–
1
SNR = 92dB
THD = –101dB
SINAD = 91.4dB
SFDR = 103dB
–20
8
10μF R4 = 1.1k
R3 = 10k
+ VCM = VREF/2
–
75pF
0
LT6350
0V to
2.5V
Figure 6. LT6350 Converting a 0V-5V Single-Ended Signal to
a ±2.5V Differential Input Signal
AMPLITUDE (dBFS)
The LT6350 can also be used to buffer and convert large,
true bipolar signals which swing below ground to the ±2.5V
differential input range of the LTC2383-16. Figure 7 shows
the LT6350 being used to convert a ±10V true bipolar signal
for use by the LTC2383-16. The input impedance is again
set by resistor RIN. Table 2 shows the resulting SNR and
THD for several values of RIN. Figure 7a shows the resulting
FFT when using the LT6350 as shown in Figure 7.
VCM
VREF
10μF
resulting SNR and THD for several values of RIN , R1, R2
and R3 in this configuration. Figure 6a shows the resulting
FFT when using the LT6350 as shown in Figure 6.
–180
0
100
200
300
FREQUENCY (kHz)
400
500
238316 F06a
Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6
0
100
200
300
FREQUENCY (kHz)
400
500
238316 F07a
Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7
238316f
12
LTC2383-16
APPLICATIONS INFORMATION
Table 2. SNR, THD vs RIN for ±10V Single-Ended Input Signal.
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
10k
1.24k
1.24k
10k
1.1k
92
–96
50k
6.19k
6.19k
50k
5.49k
91
–96
100k
12.4k
12.4k
100k
11k
91
–96
ADC REFERENCE
The LTC2383-16 requires an external reference to define its
input range. A low noise, low temperature drift reference
is critical to achieving the full datasheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6652-2.5 is particularly well suited for
use with the LTC2383-16. The LTC6652-2.5 offers 0.05%
(max) initial accuracy and 5ppm/°C (max) temperature
coefficient for high precision applications. The LTC6652-2.5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2383-16 up to 125°C. We recommend bypassing the
LTC6652-2.5 with a 47μF ceramic capacitor (X5R, 0805
size) close to the REF pin. All performance curves shown
in this datasheet were obtained using the LTC6652-2.5.
The REF pin of the LTC2383-16 draws charge (QCONV)
from the 47μF bypass capacitor during each conversion
cycle. The reference replenishes this charge with a DC
current, IREF = QCONV/tCYC. The DC current draw of the
REF pin, IREF, depends on the sampling rate and output
code. If the LTC2383-16 is used to continuously sample
a signal at a constant rate, the LTC6652-2.5 will keep the
deviation of the reference voltage over the entire code
span to less than 0.5LSBs.
When idling, the REF pin on the LTC2383-16 draws only a
small leakage current (< 1μA). In applications where a burst
of samples is taken after idling for long periods as shown
in Figure 8, IREF quickly goes from approximately 0μA to
a maximum of 910μA at 1Msps. This step in DC current
draw triggers a transient response in the reference that
must be considered since any deviation in the reference
output voltage will affect the accuracy of the output code. In
applications where the transient response of the reference
is important, the fast settling LTC6655-2.5 reference
is recommended. Inserting a 1Ω resistor between the
47μF bypass capacitor and reference output as shown in
Figure 9 helps to improve the transient settling time and
minimize the reference voltage deviation.
VOUT_S
LTC6655-2.5
VOUT_F
1Ω
47μF
LTC2383-16
238316 F09
Figure 9. LTC6655-2.5 Driving REF of LTC2381-16
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm, the
ADC’s spectral content can be examined for frequencies
outside the fundamental. The LTC2383-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
CNV
IDLE
PERIOD
IDLE
PERIOD
238316 F08
Figure 8. CNV Waveform Showing Burst Sampling
238316f
13
LTC2383-16
APPLICATIONS INFORMATION
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 10 shows that the LTC2383-16 achieves
a typical SINAD of 92dB at a 1MHz sampling rate with a
20kHz input.
0
SNR = 92.2dB
THD = –106.2dB
SINAD = 92dB
SFDR = 110.4dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
500
238316 F10
Figure 10. 32k Point FFT of the LTC2383-16
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2383-16 achieves a typical SNR of 92dB at a
1MHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD = 20 log
V 22 + V 32 + V 42 + … + VN 2
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2383-16 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2383-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2383-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2383-16
has a power-on-reset (POR) circuit that will reset the
LTC2383-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2383-16 conversion is controlled by CNV. A rising
edge on CNV will start a conversion. Once a conversion has
been initiated, it cannot be restarted until the conversion
is complete. For optimum performance, CNV should be
driven by a clean low jitter signal. Converter status is
indicated by the BUSY output which remains high while
the conversion is in progress. To ensure that no errors
occur in the digitized results, any additional transitions
on CNV should occur within 40ns from the start of the
conversion or after the conversion has been completed.
Once the conversion has completed, the LTC2383-16
begins acquiring the input signal.
V1
238316f
14
LTC2383-16
APPLICATIONS INFORMATION
Internal Conversion Clock
DIGITAL INTERFACE
The LTC2383-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 730ns. With a minimum acquisition time of 250ns, throughput performance
of 1Msps is guaranteed without any external
adjustments.
The LTC2383-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2383-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
Auto Power-Down
The LTC2383-16 automatically powers down after a
conversion has been completed as long as CNV remains
high. During power down, the data from the last conversion
can be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. To power up
the part, bring CNV low at least 200ns (tCONVL) before the
initiation of the next conversion. The auto power-down
feature will reduce the power dissipation of the LTC238316 as the sampling frequency is reduced. Since the time
required to power up the part does not change at lower
sample rates, the LTC2383-16 can remain powered-down
for a larger fraction of the conversion cycle (tCYC), thereby
reducing the average power dissipation which scales
linearly with sampling rate as shown in Figure 11.
The serial output data is clocked out on the SDO pin
when an external clock is applied to the SCK pin if SDO
is enabled. Clocking out the data after the conversion will
yield the best performance. With a shift clock frequency
of at least 60MHz, a 1Msps throughput is still achieved.
The serial output data changes state on the rising edge
of SCK and can be captured on the falling edge or next
rising edge of SCK. D15 remains valid till the first rising
edge of SCK.
The serial interface on the LTC2383-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2383-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
POWER SUPPLY CURRENT (mA)
6
5
4
3
2
1
0
0
200
400
600
800
SAMPLING RATE (kHz)
1000
238316 F11
Figure 11. Power Supply Current of the LTC2383-16
Versus Sampling Rate
238316f
15
LTC2383-16
TIMING DIAGRAM
Normal Mode, Single Device
Figure 12 shows a single LTC2383-16 operated in Normal
Mode with CHAIN and RDL/SDI tied to ground. With RDL/
SDI grounded, SDO is enabled and the MSB(D15) of the
new conversion data is available at the falling edge of BUSY.
This is the simplest way to operate the LTC2383-16.
When CHAIN = 0, the LTC2383-16 operates in Normal
mode. In Normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high-impedance. If RDL/SDI is low, SDO is driven.
CONVERT
DIGITAL HOST
CNV
BUSY
CHAIN
IRQ
LTC2383-16
RDL/SDI
SDO
DATA IN
SCK
CLK
238316 F12a
ACQUIRE
CONVERT
ACQUIRE
CONVERT
POWER-DOWN
CHAIN = 0
POWER-UP
tCYC
tCNVH
tCNVL
CNV
tACQ = tCYC – tCONV – tBUSYLH
tCONV
BUSY
tACQ
tSCK
tBUSYLH
tSCKH
1
SCK
2
3
tHSDO
tDSDOBUSYL
SDO
14
15
16
tSCKL
tDSDO
D15
D14
D13
D1
D0
238316 F12
(RDL/SDI = 0)
Figure 12. Using a Single LTC2383-16 in Normal Mode
238316f
16
LTC2383-16
TIMING DIAGRAM
Normal Mode, Multiple Devices
time in order to avoid bus conflicts. As shown in Figure 13,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO. To ensure the MSB is properly
output and captured, SCK must be held low at least 1ns
before and 16ns after bringing RDL/SDI low.
Figure 13 shows multiple LTC2383-16 devices operating
in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2383-16 to drive SDO at a
RDL2
RDL1
CONVERT
CNV
CNV
CHAIN
CHAIN
BUSY
IRQ
LTC2383-16
LTC2383-16
SDO
B
DIGITAL HOST
SDO
A
RDL/SDI
RDL/SDI
SCK
SCK
DATA IN
CLK
238316 F13
ACQUIRE
CONVERT
ACQUIRE
CONVERT
POWER-DOWN
POWER-UP
CHAIN = 0
tCNVL
CNV
tCONV
BUSY
tBUSYLH
RDL/SDIA
RDL/SDIB
tSCK
tHSCKRDL
1
SCK
2
3
tSSCKRDL
SDO
14
15
16
17
tHSDO
D15A
D14A
D13A
18
19
30
31
32
tSCKL
tDSDO
tEN
Hi-Z
tSCKH
tDIS
D1A
D0A
Hi-Z
D15B
D14B
D13B
D1B
D0B
Hi-Z
238316 F13
Figure 13. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
238316f
17
LTC2383-16
TIMING DIAGRAM
When CHAIN = OVDD, the LTC2383-16 operates in Chain
Mode. In Chain Mode, SDO is always enabled and RDL/SDI
serves as the serial data input pin (SDI) where daisychain
data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 14 shows an example with
two daisy chained devices. The MSB of converter A will
appear at SDO of converter B after 16 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
CONVERT
OVDD
OVDD
CNV
CHAIN
RDL/SDI
SDO
A
DIGITAL HOST
LTC2383-16
LTC2383-16
RDL/SDI
CNV
CHAIN
BUSY
B
IRQ
DATA IN
SDO
SCK
SCK
CLK
238316 F14a
POWER-DOWN
CONVERT
ACQUIRE
CONVERT
POWER-UP
ACQUIRE
CHAIN = OVDD
RDL/SDIA = 0
tCYC
tCNVL
CNV
BUSY
tCONV
tBUSYLH
tSCKCH
SCK
1
2
3
14
tSCKH
15
tSSDISCK
16
18
30
31
32
tSCKL
tHSDO
tHSDISCK
SDOA = RDL/SDIB
17
tDSDO
D15A
D14A
D13A
D1A
D0A
D15B
D14B
D13B
D1B
D0B
tDSDOBUSYL
SDOB
D15A
D14A
D1A
D0A
238316 F14
Figure 14. Chain Mode Timing Diagram
238316f
18
LTC2383-16
BOARD LAYOUT
To obtain the best performance from the LTC2383-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1571A, the
evaluation kit for the LTC2383-16.
Partial Top Silkscreen
238316 BL01
238316f
19
LTC2383-16
BOARD LAYOUT
Partial Layer 1 Component Side
238316 BL02
Partial Layer 2 Ground Plane
238316 BL03
238316f
20
LTC2383-16
BOARD LAYOUT
Partial Layer 3 PWR Plane
238316 BL04
Partial Layer 4 Bottom Layer
238316 BL05
238316f
21
AIN –
E7
VREF/2
EXT
R39
ØΩ
JP5
HD1X3-100
EXT_CM
AIN+
R14
Ø
+2.5V
3
2
1
COUPLING
AC
DC
C46
1μF
COUPLING
AC
DC
C8
1μF
C47
OPT C48
10μF
6.3V
4
2
5
4
+3.3V
C2
0.1μF
R3
CLK
33Ω
TO CPLD
R41
OPT
R40
1k
R18
1k
R9
1k
C49
OPT
C63
10μF
6.3V
3
V+
C43
1μF
C55
1μF
6
C45 V –
10μF
2 +IN2
8 +IN1
V–
C62
10μF
R37
1k
R34
ØΩ
C61
10μF
6.3V
C42
15pF
R32
ØΩ
V+
C44
1μF
C57
0.1μF
V+
C59
1μF
OUT2 5
–IN1
OUT1 4
U15
7 LT6350CMS8
SHDN
U2
R6 3 U8
3
NC7SZ04P5X NC7SVU04P5X
1k
R15
1k
HD1X3-100
JP2
CM
C18
OPT
C17
10μF
JP1
HD1X3-100
R5
49.9Ω
1206
2
5
+3.3V
C1
0.1μF
R2
1k
+3.3V
2
CLKIN
1
3
C5
0.1μF
2
C60
1μF
C58
OPT
R35
OPT
R36
49.9Ω
R45
ØΩ
R32
49.9Ω
R31
OPT
SDO
C10
OPT
1
3
5
7
9
11
13
9V TO
10V
R1
100Ω
IN–
IN+
C10
0.1μF
C6
10μF
6.3V
C39
OPT R1
NPO 100Ω
C9
10μF
6.3V
C19
3300pF
1206 NPO
+2.5V
+3.3V
U10
LTC6652AHMS8-2.5
8
1
DNC GND
2
7
VIN
GND
3
6
V
SHDN OUT
5
4
GND GND
R38
OPT
C11
0.1μF
9V TO 10V
C7
0.1μF
C12
1μF
1
2
3
E6
EXT_REF
J3
DC590
2
4
6
8
10
12
14
CNV
SCK
SDO
BUSY
R1
ØΩ
R7
1k
3
2
1
C56
0.1μF
JP6
FS
EXT
6652
3
3
R17 R13
2k
1k
U9
NC7SZ04P5X
2
4
VSS
6
5
7
3
2
1
C15
0.1μF
U7
C14
0.1μF 8 24LC025-I/ST
VCC
SCL
SCK
SDA
WP
CNV
ARRAY
A2
EEPROM
A1
A0
4
5
+3.3V
R10
4.99k
R11
4.99k
CLKOUT
C16 1
0.1μF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
3
5
2 CNVST_33
FROM CPLD
U4
NC7SVU04P5X
+3.3V
C4
0.1μF
R12
4.99k
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
R4
7 33Ω 4
8
+3.3V
C3
0.1μF
R8
33Ω
DC590 DETECT
TO CPLD
PR\
Q
CLR\
Q\
5
2
D
VCC
1
CP
GND
+3.3V
C13
0.8VREF
0.1μF
VREF
6
U3
NL17SZ74
+3.3V
4
HD1X3-100
U6
OPT NC7SZ66P5X 5
CNV
VCC
9
2 B
A 1
13 SCK
OE
4
14 SDO
GND
11 BUSY
3
12 RD
C20
47μF
6.3V
0805
RDL/SDI
LTC2383-16
JP4
REF
HD1X3-100
VDD 2
OVDD 15
7
8
1
3
REF
REF1
GND
GND
GND
GND
+
–
–
+
22
3
6
10
16
1
R1
33Ω
LTC2383-16
BOARD LAYOUT
Partial Schematic of Demoboard
238316f
LTC2383-16
PACKAGE DESCRIPTION
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
0.70 ±0.05
2.20 ±0.05
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(SEE NOTE 6)
1.70 ± 0.05
16
R = 0.05
TYP
3.30 ±0.05
3.60 ±0.05
0.40 ± 0.10
9
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45°
CHAMFER
(DE16) DFN 0806 REV Ø
8
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.45 BSC
3.15 REF
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1
0.23 ± 0.05
0.45 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
16151413121110 9
3.20 – 3.45
(.126 – .136)
0.254
(.010)
DETAIL “A”
0o – 6o TYP
0.280 p 0.076
(.011 p .003)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.305 p 0.038
(.0120 p .0015)
TYP
0.53 p 0.152
(.021 p .006)
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
NOTE:
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1234567 8
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
238316f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2383-16
TYPICAL APPLICATION
ADC Driver: Single-Ended Input to Differential Output with Filter
0
SNR = 92.2dB
THD = –106.2dB
SINAD = 92dB
SFDR = 110.4dB
–20
LPF1
LT6350
4
500Ω
8
6600pF
1
+
–
RINT
RINT
2
BW = 48kHz
LPF2
50Ω
+
–
100Ω
–40
IN+
3300pF
+
–
5
LTC2383-16
50Ω
100Ω
BW = 482kHz
IN–
238316 TA03
AMPLITUDE (dBFS)
SINGLE-ENDED
INPUT SIGNAL
–60
–80
–100
–120
–140
VCM = VREF/2
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
500
238316 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2393-16
16-Bit, 1Msps Parallel/Serial ADC
5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2392-16, LTC2391-16
LTC2392-16
16-Bit, 500Ksps Parallel/Serial ADC
5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2393-16, LTC2391-16
LTC2391-16
16-Bit, 250Ksps Parallel/Serial ADC
5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin Compatible with the LTC2393-16, LTC2392-16
LTC1864/LTC1864L
16-bit, 250ksps/150ksps 1-Channel μPower ADC
5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
LTC1865/LTC1865L
16-bit, 250ksps/150ksps 2-Channel μPower ADC
5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-8 Package
LTC2302/LTC2306
12-Bit, 500ksps, 1-/2-Channel, Low Noise, ADC
5V Supply, 14mW at 500ksps, 10-Pin DFN Package
ADCs
LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC
3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package
DACs
LTC2641
16-Bit Single Serial VOUT DACs
±1LSB INL, ±1LSB DNL, MSOP-8 Package, 0V to 5V Output
LTC2630
12-/10-/8-Bit Single VOUT DACs
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12Bits)
REFERENCES
LTC6652
Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6655
Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
AMPLIFIERS
LT6350
Low Noise Single-Ended-To-Differential ADC Driver Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time, DFN-8 or
MSOP-8 Packages
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with Unity
Gain/AV = 5/AV = 10
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz,
TSOT23-6 Package
LT6202/LT6203
Single/Dual 100MHz Rail-to-Rail Input/Output
Noise Low Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
LTC1992
Low Power, Fully Differential Input/Output
Amplifier/Driver Family
1mA Supply Current
238316f
24 Linear Technology Corporation
LT 0810 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010