iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 1/26
FEATURES
APPLICATIONS
♦ Resolution of up to 8192 angle steps per sine/cosine period
♦ Binary and decimal resolution settings, e.g. 500, 512, 1000,
1024; programmable angle hysteresis
♦ Conversion time of just 250 ns including amplifier settling
♦ Count-safe vector follower principle, real-time system with a
70 MHz sampling rate
♦ Direct sensor connection; selectable input gain
♦ Front-end signal conditioning features offset (8 bits), amplitude
ratio (5 bits) and phase (6 bits) calibration
♦ Input frequency of up to 250 kHz
♦ Incremental A QUAD B outputs with a selectable minimum
transition distance (e.g. 0.25 µs for 1 MHz at A)
♦ Index signal processing adjustable in position and width
♦ Serial output of absolute angle data at clock rates of up to
10 MHz
♦ Error monitoring: frequency, amplitude, configuration (CRC)
♦ Multiturn counting up to 24 bits
♦ Device setup from serial EEPROM or 2-wire interface
♦ ESD protection and TTL-/CMOS-compatible outputs
♦ Interpolator IC for position data
acquisition from analog
sine/cosine sensors
♦ Optical linear/rotary encoders
♦ MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright © 2011 iC-Haus
http://www.ichaus.com
iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 2/26
DESCRIPTION
iC-NQI is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts
sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data.
The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be directly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals
with regard to offset, amplitude ratio and phase errors. Front-end gain can be set in stages graded to
suit all common differential sensor signals from approximately 20 mVpp to 1.5 Vpp, and also single-end
sensor signals from 40 mVpp to 3 Vpp respectively.
Two serial interfaces have been included to permit
configuration of the device: I2 C for the connection of
an EEPROM and a 2-wire interface for configuration
from a microcontroller. A low signal at pin NPRG is
required to release the 2-wire interface for programming, whereas a high signal at pin NPRG preselects
the serial output of measurement data.
For measurement data output, the fast synchronousserial 2-wire interface can follow an SSI protocol
at clock rates of up to 4 Mbit/s, or a BiSS unidirectional protocol featuring error messages and a
CRC-protected transmission at clock rates of up to
10 Mbit/s. A configurable period counter can supplement the measurement data by a multiturn count of
up to 24 bits.
At the same time any changes in output data are
converted into incremental A QUAD B encoder signals. Here, the minimum transition distance can be
adapted to suit the system on hand (limitations due
to counter input frequency, cable length, EMI). A synchronized index signal is generated and output to Z if
enabled by the PZERO and NZERO inputs.
If the EEPROM is detected following a power-down
reset, the CRC-protected chip setup is read in automatically.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 3/26
CONTENTS
PACKAGES
4
ABSOLUTE MAXIMUM RATINGS
5
THERMAL DATA
5
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS: Diagrams . . . . . . .
6
8
OPERATING REQUIREMENTS: 2W Interface
9
SIGNAL MONITORING and ERROR
MESSAGES
17
TEST FUNCTIONS
18
19
19
20
21
21
21
PARAMETER and REGISTER
10
SERIAL 2-WIRE INTERFACE
Serial data output . . . . . . . . . . . . .
Examples of data output with SSI protocol
Bidirektional register communication . . .
Register communication: read . . . . . .
Register communication: write . . . . . .
SIGNAL CONDITIONING
11
EEPROM INTERFACE
22
CONVERTER FUNCTIONS
12
MAXIMUM CONVERTER FREQUENCY
Serial data output . . . . . . . . . . . . . . .
Incremental output to A, B and Z . . . . . . .
13
13
14
APPLICATION HINTS
Principle Input Circuits . . . . . . . . . . . . .
Basic Circuits . . . . . . . . . . . . . . . . . .
23
23
24
EVALUATION BOARD
24
INCREMENTAL SIGNALS
15
DESIGN REVIEW: Notes On Chip Functions
25
.
.
.
.
.
.
.
.
.
.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 4/26
PACKAGES TSSOP20 (according to JEDEC Standard)
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
PIN FUNCTIONS
No. Name Function
1
20
2
19
3
18
4
17
5
16
NSIN
PCOS
NCOS
PSIN
VDDA
NZERO
GNDA
PZERO
7
B
8
NQI
A
Code...
6
...yyww
VREF
NERR
15
SCL
14
SDA
13
Z
DAT
9
12
10
11
GND
VDD
CLK
NPRG
1
2
3
4
5
6
PCOS
NCOS
VDDA
GNDA
VREF
A
Input Cosine +
Input Cosine +5 V Supply Voltage (analog)
Ground (analog)
Reference Voltage Output
Incremental Output A
Analog signal COS+ (TMA mode)
PWM signal for Offset Sine (Calib.)
7 B
Incremental Output B
Analog signal COS- (TMA mode)
PWM signal for Offset Cosine (Calib.)
8 Z
Output Index Z
PWM signal for Phase/Ratio (Calib.)
9 GND
Ground
10 VDD
+5 V Supply Voltage (digital)
11 NPRG Programming Enable Input (active low)
12 CLK
2W Interface, clock line
13 DAT
2W Interface, data output
14 SDA
EEPROM interface, data line
Analog signal SIN+ (TMA mode)
15 SCL
EEPROM interface, clock line
Analog signal SIN- (TMA mode)
16 NERR Error Input/Output, active low
17 PZERO Input Zero Signal +
18 NZERO Input Zero Signal 19 PSIN
Input Sine +
20 NSIN
Input Sine -
External connections linking VDDA to VDD and GND to GNDA are required.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 5/26
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VDDA
Voltage at VDDA
-0.3
6
V
G002 VDD
G003 Vpin()
Voltage at VDD
-0.3
6
V
-0.3
6
V
Voltage at
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL,
SDA, CLK, DAT, NPRG, A, B, Z
G004 Imx(VDDA) Current in VDDA
V() < VDDA + 0.3 V
V() < VDD + 0.3 V
-50
50
mA
G005 Imx(GNDA) Current in GNDA
-50
50
mA
G006 Imx(VDD)
Current in VDD
-50
50
mA
G007 Imx(GND) Current in GND
-50
50
mA
G008 Imx()
Current in
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL, SDA,
CLK, DAT, NPRG, A, B, Z
-10
10
mA
G009 Ilu()
Pulse Current in all pins
(Latch-up Strength)
according to Jedec Standard No. 78;
Ta = 25 °C, pulse duration 10 ms,
VDDA = VDDAmax , VDD = VDDmax ,
Vlu() = (-0.5...+1.5) x Vpin()max
-100
100
mA
G010 Vd()
ESD Susceptibility at all pins
HBM 100 pF discharged through 1.5 kΩ
2
kV
G011 Tj
Junction Temperature
-40
150
°C
G012 Ts
Storage Temperature Range
-40
150
°C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V ±10 %
Item
No.
T01
Symbol
Parameter
Conditions
Unit
Min.
Ta
Operating Ambient Temperature Range
TSSOP20 ET -40/125
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
-25
-40
Typ.
Max.
85
125
°C
°C
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 6/26
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001
VDDA,
VDD
Permissible Supply Voltage
4.5
5.5
V
002
I(VDDA)
Supply Current in VDDA
003
I(VDD)
Supply Current in VDD
fin() = 200 kHz; A, B, Z open
15
mA
fin() = 200 kHz; A, B, Z open
20
004
Von
Turn-on Threshold VDDA, VDD
3.2
mA
005
006
Vhys
Turn-on Threshold Hysteresis
200
Vc()hi
Clamp Voltage hi at
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF
007
Vc()lo
008
Vc()hi
Vc()hi = V() - VDDA;
I() = 1 mA, other pins open
4.4
V
mV
0.3
1.6
V
Clamp Voltage lo at
I() = -1 mA, other pins open
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF, NERR,
SCL, SDA, CLK, DAT, NPRG, A,
B, Z
-1.6
-0.3
V
Clamp Voltage hi at
NERR, SCL, SDA, CLK,
DAT, NPRG, A, B, Z
0.3
1.6
V
0.6
VDDA
− 1.1
V
-10
-15
10
15
mV
mV
Vc()hi = V() - VDD;
I() = 1 mA, other pins open
Input Amplifiers PSIN, NSIN, PCOS, NCOS
101
Vin()sig
Permissible Input Voltage Range
102
Vos()
Input Offset Voltage
Vin() and G() in accordance with table GAIN;
G ≥ 20
G < 20
103
TCos
Input Offset Voltage
Temperature Drift
see 102
±10
µV/K
104
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
105
GA
Gain Accuracy
G() in accordance with table GAIN
95
102
%
106
107
GArel
Gain SIN/COS Ratio Accuracy
G() in accordance with table GAIN
97
103
fhc
Cut-off Frequency
G = 80
G = 2.667
230
650
kHz
kHz
108
SR
Slew Rate
G = 80
G = 2.667
4
9
V/µs
V/µs
%
Sin/D Conversion: Accuracy
201
AAabs
Absolute Angle Accuracy without referred to 360° input signal, G = 2.667,
calibration
Vin = 1.5 Vpp, HYS = 0
-1.0
1.0
DEG
202
AAabs
Absolute Angle Accuracy after
calibration
referred to 360° input signal, HYS = 0, internal
signal amplitude of 2 ... 4 Vpp
-0.5
+0.5
DEG
203
AArel
Relative Angle Accuracy
referred to output signal period of A/B,
G = 2.667, Vin = 1.5 Vpp, SELRES = 1024,
FCTR = 0x0004 ... 0x00FF, fin < finmax
(see table 14)
-10
10
%
Reference Voltage
I(VREF) = -1 mA ... +1 mA
48
52
%
VDDA
Oscillator Frequency
presented at SCL with subdivision
of 2048;
VDDA = VDD = 5 V ±10 %
VDDA = VDD = 5 V
52
60
90
83
MHz
MHz
±0.35
Reference Voltage VREF
801
VREF
Oscillator
A01 fosc()
A02
TCosc
Oscillator Frequency Temperature Drift
A03
VCosc
Oscillator Frequency Power Supply Dependance
VDDA = VDD = 5 V
72
-0.1
%/K
+10.6
%/V
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 7/26
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Zero Comparator
B01
Vos()
Input Offset Voltage
V() = Vcm()
-20
20
mV
B02
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
B03
Vcm()
Common-Mode Input Voltage
Range
1.4
VDDA1.5
V
B04
Vdm()
Differential Input Voltage Range
0
VDDA
V
V
Incremental Outputs A, B, Z and 2W Interface Output DAT
D01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(); I() = -4 mA
0.4
D02 Vs()lo
Saturation Voltage lo
I() = 4 mA
0.4
V
D03 tr()
Rise Time
CL() = 50 pF
60
ns
D04 tf()
Fall Time
CL() = 50 pF
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
60
1
ns
MΩ
2W Interface: Clock Input CLK, Programming Enable NPRG
E01
Vt()hi
Threshold Voltage hi
E02
Vt()lo
Threshold Voltage lo
2
E03
Vt()hys
Hysteresis
E04
Ipu(CLK)
Pull-up Current in CLK
E05
E06
Ipd(NPRG) Pull-down Current in NPRG
V() = 1 ... VDD
fclk(CLK)
Permissible Clock Frequency at
CLK
SSI protocol
BiSS B/C or C unidir. protocols
Register communication (NPRG = lo)
E07
tp(CLKDAT)
Propagation Delay: CLK edge vs. RL(DAT) ≥ 1 kΩ (see Fig. 4)
DAT output
10
E08
tbusy()
Processing Time
0
E09
tbusy()r
Processing Time Register Communication (start bit delay)
NPRG = lo; with read access to EEPROM
E10
tidle()
Interface Blocking Time
NPRG = lo; powering up with no EEPROM
V
0.8
V
Vt()hys = Vt()hi - Vt()lo
300
mV
V() = 0 ... VDD - 1 V
-240
-120
-25
20
120
300
µA
4
10
0.25
MHz
MHz
MHz
50
ns
0
1
µA
0
2
ms
1.5
ms
2
V
EEPROM Interface, Control Logic: Inputs SDA, NERR
F01
Vt()hi
Threshold Voltage hi
F02
Vt()lo
Threshold Voltage lo
F03
Vt()hys
Hysteresis
F04
tbusy()cfg
Duration of Startup Configuration error free EEPROM access
Vt()hys = Vt()hi - Vt()lo
0.8
V
300
mV
5
7
ms
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
Write/Read Clock at SCL
G02 Vs()lo
Saturation Voltage lo
I() = 4 mA
20
G03 Ipu()
Pull-up Current
V() = 0 ... VDD - 1 V
G04 ft()
Fall Time
CL() = 50 pF
G05 tmin()lo
Error Signal Indication Time at
NERR (lo signal)
CLK = hi (keine Datenausgabe), amplitude or
frequeny error
G06 Tpwm()
Error Signal PWM Cycle Duration fosc() subdivided 222
at NERR
G07 RL()
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)
-600
-300
100
kHz
0.45
V
-75
µA
60
10
60.7
1
ns
ms
ms
MΩ
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 8/26
CHARACTERISTICS: Diagrams
0%
60%
40%
0%
twhi()/T
110%
90%
50%
100%
AArel ±10%
AArel ±10%
Figure 1: Definition of relative angle error.
$ tMTD
Figure 2: Definition of minimum transition distance.
0.15°
0.1°
0.05°
0
-0.05°
-0.1°
-0.15°
0°
90°
180°
270°
Figure 3: Typical residual absolute angle error after calibration.
360°
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 9/26
OPERATING REQUIREMENTS: 2W Interface
Operating Conditions: VDD = 5 V ±10 %, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item
No.
Symbol
Parameter
Conditions
Fig.
Unit
Min.
Max.
Serial Data Output: SSI (Pin NPRG = hi, SELSSI = 1)
I001 TCLK
Permissible Clock Period
4
250
2x ttos
ns
I002 tCLKh
Clock Signal Hi Level Duration
CFGTOS = 0x01
4
25
ttos
ns
I003 tCLKl
Clock Signal Lo Level Duration
4
25
ttos
ns
5, 6
100
2x ttos
ns
Serial Data Output: BiSS B, BiSS C unidir. (Pin NPRG = hi, SELSSI = 0, BiSSMOD = 0 resp. 1)
I004 TCLK
Permissible Clock Period
CFGTOS selected in accordance with
table 31
I005 tCLKh
Clock Signal Hi Level Duration
5, 6
25
ttos
ns
I006 tCLKl
Clock Signal Lo Level Duration
5, 6
25
ttos
ns
7
4
Bidirectional Register Communication (pin NPRG = lo)
I007 TCLK
Permissible Clock Period
CFGTOR selected in accordance with
table 31
I008 tCLKh
Clock Signal Hi Level Duration
I009 tCLKh
Clock Signal Hi Level Duration
I010 tCLKl
Clock Signal Lo Level Duration
7
I011 tCLK0h
"Logic 0" Hi Level Duration
7
10
30
%
TCLK
I012 tCLK1h
"Logic 1" Hi Level Duration
7
70
90
%
TCLK
7
read out of register data
7
Figure 4: Serial SSI data output (NPRG = hi).
Figure 5: Serial BiSS B data output (NPRG = hi).
Figure 6: Serial BiSS C unidir. data output (NPRG = hi).
Figure 7: Bidirectional register communication (NPRG = lo).
30
µs
ttor
ns
70
%
TCLK
indefinite
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 10/26
PARAMETER and REGISTER
Signal Monitoring
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17
SELAMPL: Amplitude Monitoring, function
AMPL:
Amplitude Monitoring, thresholds
AERR:
Amplitude Error
FERR:
Frequency Error
Register Description . . . . . . . . . . . . . . . . . . . . . . . Page 10
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11
GAIN:
Gain Select
SINOFFS:
Offset Calibration Sine
COSOFFS: Offset Calibration Cosine
REFOFFS: Offset Calibration Reference
RATIO:
Amplitude Calibration
PHASE:
Phase Calibration
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
TMODE:
Test Mode
TMA:
Analog Test Mode
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12
SELRES:
Resolution
HYS:
Hysteresis
FCTR:
Max. Permissible Converter Frequency
BiSS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
CFGTOS:
Interface Timeout
CFGTOR:
Interface Timeout
M2S:
Period Counter Output
BiSSMOD: Protocol Version
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGABZ:
Output A, B, Z
ROT:
Direction of Rotation
CBZ:
Period Counter Configuration
ENRESDEL: Output Turn-On Delay
ZPOS:
Zero Signal Position
CFGZ:
Zero Signal Length
CFGAB:
Zero Signal Logic
SELSSI:
CFGSSI:
RPL:
SSI Compatibility
SSI Output
Register Protection Settings
OVERVIEW
Adr
Bit 7
0x00
BiSSMOD
0x01
0x02
0x03
Bit 6
Bit 5
Bit 4
Bit 2
M2S(1:0)
ENRESDEL
Bit 1
Bit 0
SELRES(4:0)
HYS(2:0)
ZPOS(4:0)
SELSSI
ROT
CFGSSI(1:0)
CBZ
CFGABZ(1:0)
CFGAB(1:0)
0x04
CFGZ(1:0)
RPL(1:0)
AERR
FERR
FCTR(7:0)
0x05
0x06
Bit 3
FCTR(14:8)
CFGTOR(1:0)
0x07
CFGTOS(1:0)
TMODE(2:0)
TMA
Reserved address / internal use (programming to zero recommended)
0x08
GAIN(3:0)
RATIO(3:0)
0x09
SINOFFS(7:0)
0x0A
COSOFFS(7:0)
0x0B
PHASE(5:0)
0x0C
REFOFFS
SELAMPL
AMPL(1:0)
0x0D
0x0E
0x0F
CRC(7:0) check sum over address 0-14 with CRC polynomial: "100100111" (read out of EEPROM)
EEPROM
0x10 0x1F
0x00 - 0xF
EEPROM register section for device configuration
0x20 0x77
0x10 - 0x67
Free EEPROM registers
0x78 0x7F
0x68 - 0x6F
EEPROM: BiSS Identifier, ROM: Device ID iC-NQI V3: 4E 51 56 33 {ADR0} 00 69 43
As no access protections are selected all registers are accessible by read and write operations (see RPL).
Table 5: Register layout
RATIO(4)
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 11/26
SIGNAL CONDITIONING
Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the sensor signal level and
GAIN
programmed to register GAIN according to the following table. Half of the supply voltage is output to VREF
as center voltage to help DC level adaptation.
Adr 0x08, Bit 7:4
Code
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Amplification
80.000
66.667
53.333
40.000
33.333
28.571
26.667
20.000
14.287
10.000
8.000
6.667
5.333
4.000
3.333
2.667
Differential
up to 50 mVpp
up to 60 mVpp
up to 75 mVpp
up to 0.1 Vpp
up to 0.12 Vpp
up to 0.14 Vpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.28 Vpp
up to 0.4 Vpp
up to 0.5 Vpp
up to 0.6 Vpp
up to 0.75 Vpp
up to 1 Vpp
up to 1.2 Vpp
up to 1.5 Vpp
Sine/Cosine input signal levels Vin()
Amplitude
Average value (DC)
Single-ended
Differential
Single-ended
up to 100 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 120 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.15 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.2 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.24 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.28 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.3 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.4 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.56 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.4 V
up to 0.8 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.5 V
up to 1 Vpp
0.8 V ... VDDA - 1.4 V
1.0 V ... VDDA - 1.6 V
up to 1.2 Vpp
0.8 V ... VDDA - 1.4 V
1.1 V ... VDDA - 1.7 V
up to 1.5 Vpp
0.9 V ... VDDA - 1.5 V
1.3 V ... VDDA - 1.9 V
up to 2 Vpp
1.2 V ... VDDA - 1.6 V
1.7 V ... VDDA - 2.1 V
up to 2.4 Vpp
1.2 V ... VDDA - 1.7 V
1.8 V ... VDDA - 2.3 V
up to 3 Vpp
1.3 V ... VDDA - 1.8 V
2.0 V ... VDDA - 2.6 V
Table 6: Gain select
SINOFFS
Adr 0x09, Bit 7:0
RATIO
Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0
COSOFFS
Code
Adr 0x0A, Bit 7:0
Output offset
Code
COS / SIN
Code
COS / SIN
Input offset
0x00
0V
0V
0x00
0x01
1.0000
1.0067
0x10
0x11
1.0000
0.9933
0x01
...
0x7F
0x80
0x81
...
-7.8125 mV
...
-0.9922 V
0V
+7,8125 mV
...
-7.8125* mV / GAIN
...
-0.9922 V / GAIN
0V
+7.8125 mV / GAIN
...
...
0x0F
...
1.1
...
0x1F
...
0.9000
0xFF
+0.9922 V
+0.9922 V / GAIN
Notes
*) With REFOFFS = 0x00 und VDDA = 5 V.
Table 7: Offset calibration sine/cosine
REFOFFS
Code
Adr 0x0B, Bit 1
Reference voltage
0x00
Depending on VDDA
(example of application: MR sensors)
Not depending on VDDA
(example of application: Sin/Cos encoders)
0x01
Table 8: Offset calibration reference
Table 9: Amplitude Calibration
PHASE
Code
Adr 0x0B, Bit 7:2
Phase shift
Code
Phase shift
0x00
0x01
...
0x12
...
0x1F
90°
90.703125°
...
102.65625°
102.65625°
102.65625°
90°
89.296875°
...
77.34375°
77.34375°
77.34375°
0x20
0x21
...
0x32
...
0x3F
Table 10: Phase calibration
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 12/26
CONVERTER FUNCTIONS
SELRES
Code
Adr 0x00, Bit 4:0
Binary
Examples of permissible
resolutions
input frequencies finmax
(FCTR 0x0004, 0x4304)
SELRES
Code
Adr 0x00, Bit 4:0
Decimal
Examples of permissible
resolutions
input frequencies finmax
(FCTR 0x0004, 0x4304)
0x00
0x01
0x02
0x03
0x04
0x05
8192
4096
2048
158 Hz, 635 Hz
317 Hz, 1.27 kHz
634 Hz, 2.54 kHz
0x10
0x11
0x12
0x13
0x14
0x15
2000
1600
1000
800
500
400
650 Hz, 2.6 kHz
812 Hz, 3.3 kHz
1.3 kHz, 5.2 kHz
1.6 kHz, 6.5 kHz
2.6 kHz, 10.4 kHz
3.2 kHz, 13 kHz
0x06
0x07
0x08
0x09
0x0A
0x0B
1024
512
256
128
64
32
1.27 kHz, 5.1 kHz
2.54 kHz, 10.2 kHz
5.1 kHz, 20.3 kHz
10.2 kHz, 40.6 kHz
20.3 kHz, 81.3 kHz
40.6 kHz, 162.5 kHz
0x16
0x17
0x18
0x19
0x1A
0x1B
250 *1
125 *1,2
320
160 *2
80 *4
40 *8
5.2 kHz, 20.8 kHz
5.2 kHz, 20.8 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
0x0C
0x0D
0x0E
0x0F
16
8
-
81.3 kHz (max. 250 kHz @ 0x4202)
162 kHz (max. 250 kHz @ 0x4102)
0x1C
0x1D
0x1E
0x1F
200
100 *2
50 *1,4
25 *1,8
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
Notes
*1
Table 11: Binary resolutions
Not useful with increment A quad B output.
The internal converter resolution is higher
by factor 2, 4 or 8.
*2,4,8
Table 12: Decimal resolutions
HYS
Code
Adr 0x01, Bit 7:5
Hysteresis in
Hysteresis in
degree
LSB
0x00
0°
0x01
0.0879°
0x02
0.1758°
0x03
0.3516°
0x04
0.7031°
0x05
0x06
1.4063°
5.625°
0x07
45°
Notes
*) The absolute error is equivalent to one half the
angle hysteresis
Absolute error*
1 LSB @
12 bit
1/2 LSB @
10 bit
1 LSB @
10 bit
0.044°
1/2 LSB @
8 bit
1 LSB @ 8 bit
0.352°
only
recommended
for calibration
22.5°
Table 13: Hysteresis
0.088°
0.176°
0.703°
2.813°
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 13/26
MAXIMUM CONVERTER FREQUENCY
The converter frequency automatically adjusts to the
value necessary for the input frequency and resolution.
This value ranges from zero to a maximum dependent
on the oscillator frequency which can be set using register FCTR.
down feature can be enabled via the FCTR register.
Should the input frequency exceed the frequency limit
of the selected converter resolution, the LSB is kept
stable and not resolved any further; the interpolation
resolution halves.
Serial data output
For serial data output the possible maximum converter
frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-
If the next frequency limit is overshot, the LSB and the
LSB+1 are kept stable and so on. When the input frequency again sinks below this frequency limit, the fine
resolution automatically returns.
Maximum Converter Frequency For Serial Data Output
Resolution
Protocol
Max. Input Frequency
Restrictions
Requirements
at high input frequencies
FCTR
Min. Res. bin dec BiSS SSI finmax
0x0004
X
X
X
X
fosc()min / 40 / Resolution
–
0x4102
≥8
X
X
X
X
fosc()min / 24 / Resolution
Rel. angle error 2x increased
0x4202
≥ 16
X
X
X
X
2 x fosc()min / 24 / Res.
Rel. angle error 4x increased
0x4303
≥ 32
X
X
X
X
4 x fosc()min / 32 / Res.
Rel. angle error 8x increased
0x4602
≥ 32
X
X
X
4 x fosc()min / 24 / Res.
Resolution lowered by factor of 2
0x4A02 ≥ 64
X
X
X
8 x fosc()min / 24 / Res.
Res. lowered by factor of 2-4
0x4E02 ≥ 128
X
X
X
16 x fosc()min / 24 / Res.
Res. lowered by factor of 2-8
0x5202
≥ 256
X
X
X
32 x fosc()min / 24 / Res.
Res. lowered by factor of 2-16
0x5602
≥ 512
X
X
X
64 x fosc()min / 24 / Res.
Res. lowered by factor of 2-32
0x5A02 ≥ 1024
X
X
X
128 x fosc()min / 24 / Res.
Res. lowered by factor of 2-64
0x5E02 ≥ 2048
X
X
X
256 x fosc()min / 24 / Res.
Res. lowered by factor of 2-128
0x6202
4096
X
X
X
512 x fosc()min / 24 / Res.
Res. lowered by factor of 2-256
Notes
*) Calculated with fosc()min taken from Electrical Characteristics item A01.
Table 14: Possible maximum converter frequency for serial data output.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
0.78
6.2
32.0
1.1
8.5
2.1
16.9
4.2
33.8
8.5
67.7
16.9
135
33.8
250
67.7
135
-
iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 14/26
Incremental output to A, B and Z
There are two criteria which must be considered when
setting the maximum possible converter frequency via
the FCTR register:
1. The maximum input frequency
2. System limitations, e.g. due to slow counters or
cable transmission
When facing system limitations it is useful to preselect a minimum transition distance for the output signals. A digital zero-delay glitch filter then takes care
of a temporal edge-to-edge separation, guaranteeing
spike-free output signals after an ESD impact to the
sensor, for instance.
A serial data output is simultaneously possible at any
time. However, for the transfer of angle data to the
output register the incremental output is halted for one
period of the clock signal applied to pin CLK.
1. Maximum Converter Frequency Defined By The Maximum Input Frequency
Output Frequency Resolution Maximum Input Frequency
Restrictions
fout @ finmax
Requirem.
at high input frequencies
FCTR
A, B
bin dec finmax
0x0004
325 kHz
X
X
fosc()min / 40 / Resolution
None
0x4102
542 kHz
X
X
fosc()min / 24 / Resolution
Relative angle error 2x increased
0x4202
1.08 MHz
X
X
2 x fosc()min / 24 / Res.
Relative angle error 4x increased
0x4303
1.6 MHz
X
X
4 x fosc()min / 32 / Res.
Relative angle error 8x increased
Notes
*) Calculated with fosc()min taken from Electrical Characteristics item A01.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
0.78
6.2
32.0
Table 15: Possible maximum converter frequency for incremental A/B/Z output,
defined by the maximum input frequency
2. Maximum Converter Frequency Defined By The Minimum Transition Distance
Output Frequency Resolution Minimum Transition Distance Restrictions
Example*
fout @ tMTD
Requirem. at A, B
at high input frequencies
tMTD [µsec]
FCTR
A, B
bin dec tMTD
0x00FF 10 kHz
X
X
2048 / fosc()max
None
22.8
0x00FE 10.05 kHz
X
X
2040 / fosc()max
None
22.7
0x00FD 10.09 kHz
X
X
2032 / fosc()max
None
22.6
...
...
...
...
...
...
...
0x0006
366 kHz
X
X
56 / fosc()max
None
0.62
0x0005
427 kHz
X
X
48 / fosc()max
None
0.53
0x0004
512 kHz
X
X
40 / fosc()max
None
0.44
0x4102
854 kHz
X
X
24 / fosc()max
Relative angle error 2x increased
0.27
0x4202
1.7 MHz
X
X
12 / fosc()max
Relative angle error 4x increased
0.13
0x4303
2.8 MHz
X
X
8 / fosc()max
Relative angle error 8x increased
0.09
Notes
*) Calculated with fosc()max taken from El.Char. item A01; the min. transition distance refers to output A vs. output B
without reversing the sense of rotation.
Table 16: Possible maximum converter frequency for incremental A/B/Z output,
defined by the minimum transition distance
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 15/26
INCREMENTAL SIGNALS
CFGABZ
Code
Adr 0x02, Bit 3:2
Mode
A
B
Z
0x00
Normal
A
B
Z
0x01
Control signals for
external period counters
CA
CB
CZ
0x02
Calibration mode
Offset+Phase
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
0x03
Calibration mode
Offset+Amplitude
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
Notes
Figure 8: Offset SIN*
Figure 9: Offs. COS*
Figure 10: Phase*
Figure 11: Offset
SIN*
Figure 12: Offs.
COS*
Figure 13: Amplit.*
*) Trimmed accurately when duty cycle is 50 %;
Recommended trimming order (after selecting GAIN): Offset, Phase, Amplitude Ratio, Offset;
Table 17: Outputs A, B, Z
ROT
Code
Adr 0x02, Bit 5
Code direction
0x00
0x01
Ascending order, B then A
Descending order, A then B
SIN
Table 18: Code direction
COS
cw: F->0
CBZ
Code
Adr 0x02, Bit 4
Clear by zero
0x00
0x01
Disabled
Enabled
FFFFFF
P(23:0)
000000
ccw: 0->F
A
B
Z
Table 19: Reset enable for period counter
-180°
Code
Adr 0x02, Bit 7
Output*
Function
0x00
immediately
An external counter displays the
absolute angle following power on.
0x01
after 5 ms
An external counter only displays
changes vs. the initial power-on
condition (moving halted to
reapply power is precondition.)
Notes
*) Output delay after device configuration and
internal reset.
ENRESDEL
Table 20: Output turn-on delay A, B, Z
-90°
0°
45°
90°
180°
Figure 14: Clear by zero function of the period
counter when enabled by CBZ = 1.
Example for resolution 64 (SELRES = 0x0A), zero signal at 45°
(ZPOS = 0x04,
CFGAB = 0x00) and
the direction of rotation not inverted
(ROT = 0x00, COS leads SIN).
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 16/26
ZPOS
Code
Adr 0x01, Bit 4:0
Position
CFGZ
Code
Adr 0x02, Bit 1:0
Length
0x00
0x08
0x10
0x18
0°
90°
180°
270°
0x00
0x01
0x02.. 03
90°
180°
Synchronization
0x01
...
0x1F
11.25° (1 x 11.25°)
...
348.75° (31 x 11.25°)
CFGAB
Adr 0x03, Bit 5:4
Notes
The zero signal is only output if released by the
input pins (for instance with PZERO = 5 V, NZERO =
VREF).
Code
Z = 1 for
0x00
0x01
B = 1, A = 1
B = 0, A = 1
Table 21: Zero signal position
0x02
0x03
B = 1, A = 0
B = 0, A = 0
Table 22: Zero signal length
Table 23: Zero signal logic
SIN
COS
A
B
Z (CFGZ= 0)
Z (CFGZ= 1)
Z (CFGZ= 2)
-180°
-90°
0°
45°
90°
180° Winkel
Figure 15: Incremental output signals for various length of the zero signal.
Example for resolution 64 (SELRES = 0x0A), a zero signal position of 45° (ZPOS = 0x04, CFGAB = 0x00) and no reversal of the rotational sense (ROT = 0x00, COS leads SIN).
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 17/26
SIGNAL MONITORING and ERROR MESSAGES
Vss
SELAMPL Adr 0x0C, Bit 2
AMPL
Adr 0x0C, Bit 1:0
Max ( |Sin| , |Cos| ) for SELAMPL = 0
Vth
Code
Voltage threshold Vth
Output amplitude*
0x00
0x01
0.60 x VDDA
0.64 x VDDA
1.4 Vpp
2.0 Vpp
0x02
0x03
0.68 x VDDA
0.72 x VDDA
2.6 Vpp
3.1 Vpp
Figure 16: Signal monitoring of minimum amplitude.
Sin2 + Cos2 for SELAMPL = 1
Code
Vthmin ↔ Vthmax
Output amplitude*
0x04
0x05
0.48 ↔ 0.68 x VDDA
0.56 ↔ 0.76 x VDDA
2.4 Vpp ↔ 3.4 Vpp
2.8 Vpp ↔ 3.8 Vpp
0x06
0x07
0.64 ↔ 0.84 x VDDA
0.72 ↔ 0.92 x VDDA
3.2 Vpp ↔ 4.2 Vpp
3.6 Vpp ↔ 4.6 Vpp
Notes
*) Entries are calculated with VDDA = 5 V.
Table 24: Signal amplitude monitoring
AERR
Code
Adr 0x03, Bit 1
Amplitude error message
0x00
0x01
disabled
enabled
FERR
Code
Adr 0x03, Bit 0
Excessive frequency error message
0x00
0x01
disabled
enabled
Note
Input frequency monitoring is operational for
resolutions ≥ 16
Table 26: Frequency error
Configuration error
Messaging always released
Table 27: Configuration error
No error
Amplitude error
Frequency error
Configuration
Undervoltage
System error
Vthmin
Figure 17: Sin2 + Cos2 signal monitoring.
Each phase in the configuration process is signaled by
NERR = low; the signal is only reset following a successful CRC (cyclic redundancy check).
Table 25: Amplitude error
Error keys
Failure mode
Vthmax
Pin NERR
Error bits E1, E0 with
BiSS and SSI
HI
LO/HI = 75 %
(AERR = 0: HI)
LO/HI = 50 %
(FERR = 0: HI)
LO
LO
NERR = low caused
by an external error
signal
11
01
(11)
10
(11)
00
00
00
Table 28: Error keys
If the data transfer from the EEPROM is faulty and the
CRC unsuccessful, then the configuration phase is automatically repeated. The process aborts following a
third unsuccessful attempt and the error message output remains set to low.
To enable the successful diagnosis of faults other types
of error are signaled at NERR using a PWM code as
given in the key on the left.
Two error bits are provided for error messaging via the
serial 2-wire interface; these bits can decode four different types of error. If NERR is held at low by an external source, such as an error message from the system, for example, this can also be verified via the serial
2-wire interface.
Error events are stored for the serial data output and
deleted afterwards. Errors at NERR are displayed for a
minimum of ca. 10 ms, as far as no serial data readout
causes a deletion.
If an error in amplitude occurs the conversion process is terminated and the incremental output signals
halted. An error in amplitude rules out the possibility of
an error in frequency.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 18/26
TEST FUNCTIONS
TMODE
Code
Adr 0x06, Bit 3:1
Signal at Z
Description
0x00
0x01
0x02
0x03
0x04
0x05
Z
A xor B
ENCLK
NLOCK
CLK
DIVC
no test mode
Output A EXOR B
iC-Haus device test
iC-Haus device test
iC-Haus device test
iC-Haus device test
0x06
0x07
PZERO - NZERO
TP
iC-Haus device test
iC-Haus device test
Condition
CFGABZ = 0x00
TMA
Code
Adr 0x06, Bit 0
Pin A
Pin B
Pin SDA
Pin SCL
0x00
0x01
A
COS+
SDA
SIN+
SCL
SIN-
Notes
To permit the verification of GAIN and OFFSET
settings, the input amplifier outputs are available at
the pins. To operate the converter a signal of 4 Vpp
is the ideal here and should not be exceeded. Pin
loads above 1 MΩ are adviceable for accurate
measurements.
EEPROM access is not possible during mode TMA.
B
COS-
Table 30: Analog test mode
Table 29: Test mode
Parameter GAIN ideally adjusts the signal levels to ca.
4 Vpp and should not be touched afterwards.
5V
A: COS+
SDA: Sin+
Both scope display modes are feasible for OFFS (positive values) or RATIO adjustments; regarding the adjustment of PHASE the X/Y mode may be preferred.
For OFFS adjustment towards negative values the test
signals COS- (pin B) and SIN- (pin SCL) are relevant.
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 18: Calibrated signals during analog test
mode.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 19/26
SERIAL 2-WIRE INTERFACE
Depending on the programming enable at pin NPRG
the serial 2-wire interface supports either a fast cyclic
data output of the angle position and period counter
data (for NPRG = 1), or bidirectional register communication for device programming, with write and read access to RAM and EEPROM registers (for NPRG = 0).
Two timeouts are used that prescribe a default minimum clock frequency of f(CLK)min for the master: sensor mode timeout Ttos and register mode timeout Ttor.
For data to be transferred to the interface conversion
is halted for one CLK pulse from Latch. This time must
be taken into consideration with low clock frequencies
when calculating the maximum permissible input frequency.
As long as the configuration error is active, the longest
respective timeouts are set regardless of CFGTOS or
CFGTOR.
CFGTOS
Code
Adr 0x06, Bit 5:4
Timeout ttos
Ref. clock
data output
counts
f(CLK) min*
0x00
0x01
0x02
0x03
typ.
typ.
typ.
typ.
11 kHz
88 kHz
352 kHz
1.41 MHz
CFGTOR
Code
Adr 0x06, Bit 7:6
Timeout ttor
Ref. clock
programming
counts
f(CLK) min*
0x00
0x01
0x02
typ. 1 ms
typ. 256 µs
typ. 32 µs
2049-2060
513-514
67-68
1.4 kHz
5.5 kHz
42 kHz
0x03
not permitted
–
–
Notes
32
A ref. clock count is equal to fosc
(see El. Char.
A01). The permissible max. clock frequency is
specified by item E06.
128 µs
16 µs
4 µs
1 µs
256-259
32-35
8-11
2-5
Serial data output
The position data provided by iC-NQI can contain the
following data values: period counter (P), angle data
(S), two error bits (E1, E0), and 5 or 6 CRC bits.
Signal names
Name
Description
P(23:0)
S(12:0)
E1
E0
(0)
CRC(5:0)
Period counter (0, 8, 12 or 24 bit)
Angle data (3 to 13 bit)
Error bit (amplitude error)
Error bit (frequency error)
Zero bit(s)
CRC bits, inverted output, 5 or 6 bits
Polynomial x5 + x2 + x0 (0x25, resp. 100101)
Polynomial x6 + x1 + x0 (0x43, resp. 1000011)
with period counter output of 12 or 24 bit
Table 32: Signal names
Figure 19: Output with SSI protocol
(error bits optional)
Figure 20: Output with BiSS B protocol
Table 31: 2-wire interface timeout
Figure 21: Output with BiSS C unidirectional protocol
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 20/26
Four parameters are relevant when setting the output
protocol and data content; SELSSI and BiSSMOD select the protocol version, and M2S and CFGSSI define
the optional data content.
SELSSI
Code
Adr 0x02, Bit 6
Description
0x00
0x01
Data output BiSS compatible
Data output with SSI protocol
(in binary format, MSB first)
CFGSSI
Code
Adr 0x03, Bit 7:6
Additional bits
Ring register operation
0x00
0x01
0x02
0x03
E1, E0, zero bit
none
E1, E0, zero bit
none
no
no
yes
yes
Table 36: Output options for SSI protocol
Cycle
CLK
Table 33: Protocol version
DAT
S12
P0
LSB MSB
P7
MSB
S0
LSB
Stop
P7
MSB
P0 S12
LSB MSB
S0
LSB
BiSSMOD
Code
Adr 0x00, Bit 7
Description
0x00
0x01
Data output BiSS B or SSI
Data output BiSS C unidirectional
Stop
Timeout
Latch
Figure 22: Ring operation with SSI protocol.
Table 34: Protocol version
M2S
Code
Adr 0x00, Bit 6:5
Data length
CRC poly.
Zero bit
0x00
0x01
0x02
0x03
P(7:0)
P(11:0)
P(23:0)
yes
yes
yes
no
0x25
0x25
0x43
0x43
Table 35: Period counter output
Examples of data output with SSI protocol
SSI Output Formats
13-bit SSI
Res
Mode Error CRC
10 bit SSI
X
-
T1
T2
T3
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25
S9
S8
S7
S6 ... S0
E1
E0
Example
13 bit SSI
-
-
S12 S11 S10 S9 ... S3
S2
S1
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
S0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
0
0
0
0
0
0
0
0
0
*1
Example
SSI-R -
-
0
S12 S11 S10 S9 ... S3
S2
S1
S0
0
0
0
0
Stop S12 S11 S10 S9
0
0
0
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
*2
Example
0
25-bit SSI
13 bit SSI
X
-
S12 S11 S10 S9 ... S3
S2
S1
S0
E1
E0
Example
8 + 13 SSI
bit*3
X
-
P7
P6
P5
P4 ... P0, S10 S9
S12, S11
S8
S7
S6
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
0
0
0
0
0
0
0
0
S5
S4
S3
S2
S1
S0
E1
E0
0
Stop
0
0
Example
Configuration NPRG = 0, SELSSI = 1, M2S = 0x00, CFGSSI = 0x00, unless otherwise noted.
*1 CFGSSI = 0x01; *2 CFGSSI = 0x03; *3 M2S = 0x01
Caption SSI = SSI protocol
SSI-R = SSI ring operation
Table 37: SSI output formats
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 21/26
Bidirektional register communication
The bidirectional programming mode for write and read
access to RAM and EEPROM registers is active for pin
NPRG = 0. Data is transmitted coded as a PWM which
makes a simple transfer of clock pulse and data to the
master clock line possible. A duty cycle of 75 % represents a logic one, a duty cycle of 25 % a logic zero.
The addressing sequence consists of a start bit (’1’),
the device address (slave ID ’000’), the register address (7 bits), a write/read bit WNR (’1’ for write, ’0’ for
read), a 4-bit CRC, and a stop bit (’0’). The generator
polynomial for the 4-bit CRC is 0x13 (or ’10011’); the
CRC bits are transmitted in inversion.
Register communication: read
The master carries out the addressing sequence with
the WNR bit at ’0’ and subsequently supplies at least
14 clock pulses. iC-NQI responds with a start bit (’1’),
the addressed register byte (Data(7...0)), a 4-bit CRC
(NCRC(3...0)), and a stop bit (’0’). The generator polynomial for the 4-bit CRC is also 0x13 (or ’10011’) and
the CRC bits are again transmitted in inversion.
When reading out the internal registers iC-NQI does
not require any processing time and responds immediately with the addressed register data. When reading
the external EEPROM registers, output of the start bit
is delayed until data is available from the EEPROM.
During this wait period the master must continue the
clock output.
Figure 23: Register communication: read
Register communication: write
To write data to a register the master carries out the
addressing sequence with the WNR bit set to ’1’. After
the second start bit the master transmits the data to be
written which iC-NQI returns bit by bit one clock pulse
later for verification. The 8 bits of write data are anticipated by a 4-bit CRC (as before) and also returned by
iC-NQI, this time not coded as a PWM, however.
Data is transferred to EEPROM registers in the background and can be verified by a read access once
transmission has finished.
Write access to address 0 triggers an internal reset.
This enables the period counter to be set to zero and
the configuration error deleted; the EEPROM is not
read out again.
If access to the addressed register is protected, neither
the start bit nor data are returned (the master ends the
clock output after ca. 20 ms).
Figure 24: Register communication: write
As long as the configuration error is active, iC-NQI
uses the longest respective timeouts regardless of
CFGTOS or CFGTOR and ignores possible protective settings from RPL. When programming for the first
time, the following addressing sequence is thus recommended: first addresses 1 to 12 and then address
0.
RPL
RPL
Adr 0x03, Bit 3:2
Configuration
Addr 0-31
0x00
Read / Write
0x01
Read
0x02
-
0x03
-
User
Addr
32-119
BiSS Identifier
Addr 120-127
Read /
Write
Read /
Write
Read /
Write
Read / Write
Read
Read
Read
Read
Table 38: Register protection settings
iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 22/26
EEPROM INTERFACE
Serial EEPROM components permitting operation
from 3.3 V to 5 V can be connected (such as 24C02, for
example). When the device is switched on the memory
area of bytes 0 to 15 is mapped onto iC-NQI’s registers.
For register communication with the EEPROM an address offset of 16 bytes must be taken into account;
addresses 16-127 are destined for the EEPROM bytes
of addresses 0-111.
If no EEPROM is connected, iC-NQI does not respond to addresses 16-119; reading addresses 120127 transmits the device ID.
iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 23/26
APPLICATION HINTS
Principle Input Circuits
Figure 26: Input circuit for current signals of 11 µA.
Figure 25: Input circuit for voltage signals of 1 Vpp
with no ground reference. When grounds
are not separated the connection NSIN
to VREF must be omitted.
Figure 27: Input circuit for single-side voltage or current source signals with ground reference (adaptation via resistors R3, R4).
Figure 29: Input circuit for differential current sink
sensor outputs, eg. using Opto Encoder
iC-WG.
Figure 28: Simplified input wiring for single-side
voltage signals with ground reference.
Figure 30: Combined input circuit for 11 µA, 1 Vpp
(with 120 Ω termination) or TTL encoder
signals. RS3/4 and CS1 serve as protection against ESD and transients.
iC-NQI
preliminary
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 24/26
Basic Circuits
Figure 31: Circuit for evaluation of magneto-resistor bridge sensors with inremental output.
Figure 32: Circuit for evaluation of magneto-resistor bridge sensors with serial data output.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 25/26
EVALUATION BOARD
The iC-NQI device is equipped with an evaluation
board for test purposes; descriptions are available separately.
DESIGN REVIEW: Notes On Chip Functions
iC-NQI V3
No.
1
Function, Parameter/Code
Description and Application Hints
SELRES
Illegal setting:
0x0E for resolution 4
A minimal resolution of 8 is required for the frequency monitoring function and
period counting as well. Thus, a binary resolution of 4 is not permitted when
using the period counter and the serial interface for data output with the BiSS or
SSI protocol.
A resolution of 4 may be used for solely incremental applications with A/B/Z
output, what then requires the deactivation of the frequency monitoring function
(by FERR set to 0x00).
Table 39: Notes on chip functions regarding iC-NQI chip release V3
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
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Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
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The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
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mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
preliminary
iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 26/26
ORDERING INFORMATION
Type
Package
Order Designation
iC-NQI
TSSOP20 4.4 mm
iC-NQI TSSOP20
iC-NQI TSSOP20 ET -40/125
Evaluation Board
iC-NQI EVAL NQ7D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
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