19-3509; Rev 1; 11/05 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C Features The MAX9723 stereo DirectDrive™ headphone amplifier with BassMax and volume control is ideal for portable audio applications where space is at a premium and performance is essential. The MAX9723 operates from a single 1.8V to 3.6V power supply and includes features that reduce external component count, system cost, board space, and improves audio reproduction. ♦ 62mW, DirectDrive Headphone Amplifier Eliminates Bulky DC-Blocking Capacitors The headphone amplifier uses Maxim’s patented DirectDrive architecture that produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors. The headphone amplifiers deliver 62mW into a 16Ω load, feature low 0.006% THD+N, and high 90dB PSRR. The MAX9723 features Maxim’s industry-leading click-and-pop suppression. The BassMax feature boosts the bass response of the amplifier, improving audio reproduction when using inexpensive headphones. The integrated volume control features 32 discrete volume levels, eliminating the need for an external potentiometer. BassMax and the volume control are enabled through the I2C*/SMBus™compatible interface. Shutdown is controlled through either the hardware or software interfaces. The MAX9723 consumes only 3.7mA of supply current at 1.8V, provides short-circuit and thermal-overload protection, and is fully specified over the extended -40°C to +85°C temperature range. The MAX9723 is available in a tiny (2mm x 2mm x 0.62mm) 16-bump chip-scale package (UCSP™) or 16-pin thin QFN (4mm x 4mm x 0.8mm) package. ♦ Industry-Leading Click-and-Pop Suppression Applications PDA Audio Portable CD Players Mini Disc Players Automotive Multimedia MP3-Enabled Cellular Phones MP3 Players ♦ 1.8V to 3.6V Single-Supply Operation ♦ Integrated 32-Level Volume Control ♦ High 90dB PSRR at 1kHz ♦ Low 0.006% THD+N ♦ ±8kV HBM ESD-Protected Headphone Outputs ♦ Short-Circuit and Thermal-Overload Protection ♦ Low-Power Shutdown Mode (5µA) ♦ Software-Enabled Bass Boost (BassMax) ♦ I2C/SMBus-Compatible Interface ♦ Available in Space-Saving, Thermally Efficient Packages: 16-Bump UCSP (2mm x 2mm x 0.62mm) 16-Pin Thin QFN (4mm x 4mm x 0.8mm) Ordering Information SLAVE ADDRESS 1001100 1001101 1001100 1001101 MAXIMUM GAIN (dB) 0 0 +6 +6 *Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SMBus is a trademark of Intel Corp. PKG CODE -40°C to +85°C 16 UCSP-16 B16-1 -40°C to +85°C 16 TQFN T1644-4 TEMP RANGE MAX9723_EBE-T* MAX9723_ETE+ **Replace the ‘_’ with the one-letter code that denotes the slave address and maximum programmable gain. See the Selector Guide. +Denotes lead-free package. *Future product—contact factory for availability. Pin Configurations appear at end of data sheet. Block Diagram 1.8V TO 3.6V SUPPLY Selector Guide PART MAX9723A MAX9723B MAX9723C MAX9723D PINPACKAGE PART** SCL SDA I2C INTERFACE BBL Σ OUTL INL INR BassMax OUTR VOLUME CONTROL Σ BBR BassMax MAX9723 UCSP is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9723 General Description MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C ABSOLUTE MAXIMUM RATINGS SGND to PGND .....................................................-0.3V to +0.3V VDD to PGND............................................................-0.3V to +4V PVSS to SVSS .........................................................-0.3V to +0.3V C1P to PGND..............................................-0.3V to (VDD + 0.3V) C1N to PGND............................................(PVSS - 0.3V) to +0.3V PVSS, SVSS to PGND ................................................+0.3V to -4V IN_ to SGND ..................................(SVSS - 0.3V) to (VDD + 0.3V) SDA, SCL to PGND ..................................................-0.3V to +4V SHDN to PGND ..........................................-0.3V to (VDD + 0.3V) OUT_ to SGND ............................................................-3V to +3V BB_ to SGND...............................................................-2V to +2V Duration of OUT_ Short Circuit to _GND ....................Continuous Continuous Current Into/Out of: VDD, C1P, PGND, C1N, PVSS, SVSS, or OUT_ ..............±0.85A Any Other Pin.................................................................±20mA Continuous Power Dissipation (TA = +70°C) 4 x 4 UCSP (derate 8.2mW/°C above +70°C) ...........659.2mW 16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ....1349mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Bump Temperature (soldering) Reflow ...........................................................................+230°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL Supply Voltage Range VDD Quiescent Supply Current IDD Shutdown Supply Current IDD_SHDN 3.6 V No load 1.8 4 6.5 mA V SHDN = 0V 5 8.5 µA Turn-On Time tON 200 µs Turn-Off Time tOFF 35 µs Thermal Shutdown Threshold TTHRES +143 °C Thermal Shutdown Hysteresis THYST 12 °C HEADPHONE AMPLIFIER Output Offset Voltage Input Resistance BBR, BBL Input Bias Current VOS RIN Measured between OUT_ and SGND (Note 2) Gain = 0dB, MAX9723A/ MAX9723B All volume levels 2 10 IBIAS_BB PSRR (Note 2) ±4.5 mV Gain = +6dB, MAX9723C/ MAX9723D DC, VDD = 1.8V to 3.6V Power-Supply Rejection Ratio ±0.7 73 ±0.8 ±5 17 27 kΩ ±10 ±100 nA 90 f = 217Hz, 100mVP-P ripple, VDD = 3.0V 87 f = 1kHz, 100mVP-P ripple, VDD = 3.0V 86 f = 20kHz, 100mVP-P ripple, VDD = 3.0V 61 dB _______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Output Power POUT Total Harmonic Distortion Plus Noise THD+N Maximum Gain AMAX Signal-to-Noise Ratio SNR Slew Rate CONDITIONS THD+N = 1%, fIN = 1kHz MIN RL = 32Ω TYP MAX 59 RL = 16Ω (Note 5) 38 0.006 RL = 32Ω, POUT = 45mW, fIN = 1kHz 0.004 MAX9723A/ MAX9723B Gain range bit 5 = 1 0 Gain range bit 5 = 0 -5 MAX9723C/ MAX9723D Gain range bit 5 = 1 +6 Gain range bit 5 = 0 +1 RL = 32Ω, VOUT = 1VRMS BW = 22Hz to 22kHz 99 A-weighted 100 SR mW 60 RL = 16Ω, POUT = 35mW, fIN = 1kHz UNITS % dB dB dB 0.35 V/µs No sustained oscillations 300 pF Output Resistance in Shutdown V = 0V, measured from OUT_ to ROUT_SHDN SHDN SGND 20 kΩ Output Capacitance in Shutdown COUT_SHDN VSHDN = 0V, measured from OUT_ to SGND 60 pF Capacitive Drive Click/Pop Level KCP Charge-Pump Switching Frequency Crosstalk RL = 32Ω, peak voltage, A-weighted, 32 samples per second (Notes 2, 4) MAX9723A/ MAX9723B Into shutdown -69 Out of shutdown -71 Into shutdown -70 Out of shutdown -69 dB MAX9723C/ MAX9723D fCP XTALK 505 L to R or R to L, f = 10kHz, VOUT = 1VP-P, RL = 32Ω, both channels loaded 600 700 80 kHz dB DIGITAL INPUTS (SHDN, SDA, SCL) Input High Voltage VIH Input Low Voltage VIL 0.7 x VDD Input Leakage Current V 0.3 x VDD V ±1 µA 0.4 V 1 µA DIGITAL OUTPUTS (SDA) Output Low Voltage VOL IOL = 3mA Output High Current IOH VSDA = VDD _______________________________________________________________________________________ 3 MAX9723 ELECTRICAL CHARACTERISTICS (continued) MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C TIMING CHARACTERISTICS (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see Timing Diagram.) (Notes 1, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial Clock Frequency fSCL 0 Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs START Condition Hold Time tHD:STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU:STA 0.6 µs Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 0.9 µs ns Maximum Rise Time of SDA and SCL Signals tr 300 ns Maximum Fall Time of SDA and SCL Signals tf 300 ns Setup Time for STOP Condition tSU:STO tSP 100 ns CL_BUS 400 pF Pulse Width of Suppressed Spike Maximum Capacitive Load for Each Bus Line 0.6 µs All specifications are 100% tested at TA = +25°C. Temperature limits are guaranteed by design. Inputs AC-coupled to SGND. Guaranteed by design. Headphone mode testing performed with a 32Ω resistive load connected to GND. Mode transitions are controlled by SHDN. The KCP level is calculated as: 20 x log [(level peak voltage during mode transition, no input signal)/(peak voltage under normal operation at rated power)]. Units are expressed in dB. Note 5: Output power MIN is specified at TA = +25°C. Note 1: Note 2: Note 3: Note 4: 4 _______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25°C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit) VDD = 2.4V RL = 16Ω VDD = 2.4V RL = 32Ω 1 VDD = 3V RL = 16Ω POUT = 10mW 0.01 THD+N (%) 0.1 THD+N (%) 0.1 POUT = 10mW POUT = 20mW 0.01 0.01 POUT = 25mW POUT = 37mW POUT = 23mW 0.001 0.001 1k 10k 100k 0.001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = 3V RL = 32Ω 100 100 MAX9723 toc05 1 100 MAX9723 toc04 10 VDD = 2.4V RL = 16Ω 10 MAX9723 toc06 THD+N (%) 0.1 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9723 toc03 1 MAX9723 toc01 1 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9723 toc02 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = 2.4V RL = 32Ω 10 POUT = 10mW THD+N (%) THD+N (%) THD+N (%) 0.1 1 fIN = 1kHz fIN = 20Hz 0.1 fIN = 10kHz 0.01 1 fIN = 1kHz 0.1 0.01 fIN = 10kHz fIN = 20Hz 0.01 POUT = 30mW 0.001 0.001 100 1k 10k 20 60 40 0 20 60 40 OUTPUT POWER (mW) OUTPUT POWER (mW) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER POWER DISSIPATION vs. OUTPUT POWER 1 fIN = 1kHz fIN = 10kHz 0.1 VDD = 3V RL = 32Ω 10 1 fIN = 1kHz 0.1 fIN = 20Hz fIN = 10kHz fIN = 20Hz 0.01 0.01 180 VDD = 2.4V fIN = 1kHz POUT = POUTL + POUTR OUTPUTS IN PHASE 160 POWER DISSIPATION (mW) 10 MAX9723 toc08 100 MAX9723 toc07 VDD = 3V RL = 16Ω 140 MAX9723 toc09 FREQUENCY (Hz) 100 THD+N (%) 0.001 0 100k THD+N (%) 10 RL = 16Ω 120 100 RL = 32Ω 80 60 40 20 0.001 0 0.001 0 20 40 60 OUTPUT POWER (mW) 80 100 0 20 40 60 OUTPUT POWER (mW) 80 100 0 20 40 60 80 OUTPUT POWER (mW) _______________________________________________________________________________________ 5 MAX9723 Typical Operating Characteristics Typical Operating Characteristics (continued) (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25°C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit) POWER DISSIPATION vs. OUTPUT POWER 200 RL = 32Ω 150 100 60 50 THD+N = 10% 40 30 THD+N = 1% 20 50 10 0 0 0 20 40 60 80 100 120 10 LOAD RESISTANCE (Ω) OUTPUT POWER vs. LOAD RESISTANCE 70 THD+N = 10% 60 50 THD+N = 1% 40 90 80 OUTPUT POWER (mW) OUTPUT POWER (mW) 80 100 30 MAX9723 toc13 VDD = 3V fIN = 1kHz OUTPUT POWER vs. SUPPLY VOLTAGE MAX9723 toc12 100 90 1k 100 OUTPUT POWER (mW) THD+N = 10% 70 60 50 THD+N = 1% 40 30 20 20 10 10 0 fIN = 1kHz RL = 16Ω 0 10 1k 100 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 LOAD RESISTANCE (Ω) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 0 MAX9723 toc14 140 120 -20 -30 THD+N = 10% PSRR (dB) 80 60 40 RL = 32Ω -10 100 THD+N = 1% fIN = 1kHz RL = 32Ω 20 0 -40 -50 -60 -70 -80 -90 -100 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 6 MAX9723 toc11 RL = 16Ω VDD = 2.4V fIN = 1kHz 70 MAX9723 toc15 POWER DISSIPATION (mW) 250 80 OUTPUT POWER (mW) VDD = 3V fIN = 1kHz POUT = POUTL + POUTR OUTPUTS IN PHASE OUTPUT POWER vs. LOAD RESISTANCE MAX9723 toc10 300 OUTPUT POWER (mW) MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C 10 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 100k Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25°C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit) CROSSTALK vs. FREQUENCY CROSSTALK vs. FREQUENCY RIGHT TO LEFT A = 0dB -60 -80 -100 RIGHT TO LEFT A = -10dB -60 -80 LEFT TO RIGHT A = -10dB -120 100 1k 10k 1k BASS BOOST FREQUENCY RESPONSE GAIN FLATNESS vs. FREQUENCY 100k 10k 100k 1 0 -1 AMPLITUDE (dB) R2 = 10kΩ C3 = 0.22µF 5 10k MAX9723 toc19 NO LOAD R1 = 47kΩ R2 = 22kΩ C3 = 0.1µF 0 -2 -3 -4 -5 BassMax DISABLED -5 100 FREQUENCY (Hz) R2 = 36kΩ C3 = 0.068µF 10 10 FREQUENCY (Hz) 20 15 100k MAX9723 toc18 10 -6 -10 -7 100 1k 10k 100k 10 100 1k FREQUENCY (Hz) FREQUENCY (Hz) OUTPUT SPECTRUM vs. FREQUENCY CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT -40 RL = 32Ω VDD = 3V fIN = 1kHz -50 -70 -80 -90 -100 -110 -120 NO HEADPHONE LOAD CHARGE-PUMP LOAD CONNECTED BETWEEN PVSS AND PGND -0.5 OUTPUT VOLTAGE (V) -60 0 MAX9723 toc20 10 -1.0 MAX9723 toc21 AMPLITUDE (dB) -40 -100 LEFT TO RIGHT A = 0dB -120 AMPLITUDE (dBV) VIN = 1VP-P RL = 32Ω A = -10dB -20 CROSSTALK (dB) CROSSTALK (dB) -40 MAX9723 toc17 VIN = 1VP-P RL = 32Ω A = 0dB -20 0 MAX9723 toc16 0 -1.5 -2.0 -2.5 -3.0 -130 -3.5 -140 0 5 10 FREQUENCY (kHz) 15 20 0 25 50 75 100 125 150 175 200 OUTPUT CURRENT (mA) _______________________________________________________________________________________ 7 MAX9723 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1µF, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25°C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit) OUTPUT POWER vs. CHARGE-PUMP CAPACITANCE AND LOAD RESISTANCE MAX9723 toc22 C1 = C2 = 2.2µF 70 OUTPUT POWER (mW) POWER-UP/POWER-DOWN WAVEFORM MAX9723 toc23 75 C1 = C2 = 1µF 65 VDD 2V/div 60 55 C1 = C2 = 0.68µF 50 45 VOUT 10mV/div VDD = 3V fIN = 1kHz THD+N = 1% 40 35 10 20 30 40 50 20ms/div LOAD RESISTANCE (Ω) ENTERING SHUTDOWN EXITING SHUTDOWN MAX9723 toc25 MAX9723 toc24 VSHDN 2V/div VSHDN 2V/div VOUT_ 200mV/div 20µs/div SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 7 SHUTDOWN CURRENT (µA) 3.5 3.0 2.5 NO LOAD INPUTS GROUNDED 2.0 MAX9723 toc27 8 MAX9723 toc26 4.0 8 VOUT_ 200mV/div 40µs/div 4.5 SUPPLY CURRENT (mA) MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C 6 5 4 3 2 1 NO LOAD INPUTS GROUNDED 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) _______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C PIN BUMP THIN QFN UCSP 1 D1 2 3 NAME FUNCTION VDD Power-Supply Input. Bypass VDD to PGND with a 1µF capacitor. C1 C1P Charge-Pump Flying Capacitor Positive Terminal B1 PGND 4 A1 C1N 5 B2 SCL Serial Clock Input. Connect a 10kΩ pullup resistor from SCL to VDD. Charge-Pump Output. Connect to SVSS. Bypass PVSS with a 1µF capacitor to PGND. 6 A2 PVSS 7 A3 SDA 8 B3 SHDN Power Ground. Connect to SGND. Charge-Pump Flying Capacitor Negative Terminal Serial-Data Input. Connect a 10kΩ pullup resistor from SDA to VDD. Shutdown. Drive SHDN low to disable the MAX9723. Connect SHDN to VDD while bit 7 is high for normal operation (see the Command Register section). 9 A4 SGND 10 B4 INL Left-Channel Input Signal Ground. Connect to PGND. 11 C4 INR Right-Channel Input 12 D4 SVSS Headphone Amplifier Negative Power-Supply Input. Connect to PVSS. 13 C3 BBR Right BassMax Input. Connect an external lowpass filter between OUTR and BBR to apply bass boost to the right-channel output. Connect BBR to SGND if BassMax is not used (see the BassMax (Bass Boost) section). 14 D3 OUTR Right Headphone Output 15 D2 OUTL Left Headphone Output 16 C2 BBL EP — EP Left BassMax Input. Connect an external lowpass filter between OUTL and BBL to apply bass boost to the right-channel output. Connect BBL to SGND if BassMax is not used (see the BassMax (Bass Boost) section). Exposed Paddle. Connect EP to SVSS or leave unconnected. Detailed Description The MAX9723 stereo headphone amplifier features Maxim’s patented DirectDrive architecture, eliminating the large output-coupling capacitors required by conventional single-supply headphone amplifiers. The MAX9723 consists of two 62mW Class AB headphone amplifiers, hardware/software shutdown control, inverting charge pump, integrated 32-level volume control, BassMax circuitry, comprehensive click-and-pop suppression circuitry, and an I2C-compatible interface (see the Functional Diagram/Typical Operating Circuit). A negative power supply (PVSS) is created internally by inverting the positive supply (VDD). Powering the amplifiers from VDD and PVSS increases the dynamic range of the amplifiers to almost twice that of other single-supply amplifiers, increasing the total available output power. The MAX9723 DirectDrive outputs are biased at SGND (see Figure 1). The benefit of this 0V bias is that the amplifier outputs do not have a DC component, eliminating the need for large DC-blocking capacitors. Eliminating the DC-blocking capacitors on the output saves board space, system cost, and improves low-frequency response. An I2C-compatible interface allows serial communication between the MAX9723 and a microcontroller. The MAX9723 is available with two different I2C addresses allowing two MAX9723 ICs to share the same bus (see Table 1). The internal command register controls the shutdown status of the MAX9723, enables the BassMax circuitry, sets the maximum gain of the amplifier, and sets the volume level (see Table 2). The MAX9723’s BassMax circuitry improves audio reproduction by boosting the bass response of the amplifier, compensating for any low-frequency attenuation introduced by _______________________________________________________________________________________ 9 MAX9723 Pin Description MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C In addition to the cost and size disadvantages, the DCblocking capacitors required by conventional headphone amplifiers limit low-frequency response and can distort the audio signal. VDD VDD/2 GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD SGND -VDD DirectDrive BIASING SCHEME Figure 1. Traditional Amplifier Output vs. MAX9723 DirectDrive Output the headphone. The MAX9723A and MAX9723B have a maximum amplifier gain of 0dB while the MAX9723C and MAX9723D have a maximum gain of +6dB. Amplifier volume is digitally programmable to any one of 32 levels. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. The DirectDrive output biasing scheme allows the sleeve to be grounded. 2) During an ESD strike, the amplifier’s ESD structure is the only path to system ground. The amplifier must be able to withstand the full ESD strike. The MAX9723 headphone outputs can withstand an ±8kV ESD strike (HBM). 3) When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The DirectDrive outputs of the MAX9723 can be directly coupled to other ground-biased equipment. Charge Pump Traditional single-supply headphone amplifiers have their outputs biased at a nominal DC voltage, typically half the supply, for maximum dynamic range. Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. The MAX9723 features a low-noise charge pump. The 600kHz switching frequency is well beyond the audio range, and does not interfere with the audio signals. This enables the MAX9723 to achieve a 99dB SNR. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. Limiting the switching speed of the charge pump minimizes di/dt noise caused by the parasitic bond wire and trace inductance. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Functional Diagram/Typical Operating Circuit). Maxim’s patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the MAX9723 headphone amplifier outputs to be biased at 0V, almost doubling the dynamic range while operating from a single supply. With no DC component, there is no need for the large DC-blocking capacitors. Instead of two large (typically 220µF) tantalum capacitors, the MAX9723 charge pump requires only two small 1µF ceramic capacitors, thereby conserving board space, reducing cost, and improving the low-frequency response of the headphone amplifier. See the Output Power vs. Charge-Pump Capacitance and Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes. The MAX9723 features a 5µA, low-power shutdown mode that reduces quiescent current consumption and extends battery life. Shutdown is controlled by a hardware or software interface. Driving SHDN low disables the drive amplifiers, bias circuitry, charge pump, and sets the headphone amplifier output impedance to 20kΩ. Similarly, the MAX9723 enters shutdown when bit seven (B7) in the control register is reset. SHDN and B7 must be high to enable the MAX9723. The I2C interface is active and the contents of the command register are not affected when in shutdown. This allows the master to write to the MAX9723 while in shutdown. DirectDrive 10 Shutdown ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C BassMax (Bass Boost) Typical headphones do not have a flat-frequency response. The small physical size of the diaphragm does not allow the headphone speaker to efficiently reproduce low frequencies. This physical limitation results in attenuated bass response. The MAX9723 includes a bass boost feature that compensates for the headphone’s poor bass response by increasing the amplifier gain at low frequencies. The DirectDrive output of the MAX9723 has more headroom than typical single-supply headphone amplifiers. This additional headroom allows boosting the bass frequencies without the output-signal clipping. Program the BassMax gain and cutoff frequency with external components connected between OUT_ and BB_ (see the Functional Diagram/Typical Operating Circuit). Use the I2C-compatible interface to program the command register to enable/disable the BassMax circuit. BB_ is connected to the noninverting input of the output amplifier when BassMax is enabled. BB_ is pulled to SGND when BassMax is disabled. The typical application of the BassMax circuit involves feeding a lowpass version of the output signal back to the amplifier. This is realized MAX9723 MAX9723 Click-and-Pop Suppression The output-coupling capacitor is a major contributor of audible clicks and pops in conventional single-supply headphone amplifiers. The amplifier charges the coupling capacitor to its output bias voltage at startup. During shutdown the capacitor is discharged. This charging and discharging results in a DC shift across the capacitor, which appears as an audible transient at the speaker. Since the MAX9723 headphone amplifier does not require output-coupling capacitors, no audible transients occur. Additionally, the MAX9723 features extensive click-andpop suppression that eliminates any audible transient sources internal to the device. The Power-Up/PowerDown Waveform in the Typical Operating Characteristics shows that there are minimal transients at the output upon startup or shutdown. In most applications, the preamplifier driving the MAX9723 has a DC bias of typically half the supply. The input-coupling capacitor is charged to the preamplifier’s bias voltage through the MAX9723’s input impedance (RIN) during startup. The resulting voltage shift across the capacitor creates an audible click/pop. To avoid clicks/pops caused by the input filter, delay the rise of SHDN by at least 4 time constants, 4 x RIN x CIN, relative to the start of the preamplifier. R R AUDIO INPUT OUT_ R1 BB_ BassMax ENABLE R2 C3 Figure 2. BassMax External Connections using positive feedback from OUT_ to BB_. Figure 2 shows the connections needed to implement BassMax. Maximum Gain Control The MAX9723A and MAX9723B have selectable maximum gains of -5dB or 0dB (see Table 5) while the MAX9723C and MAX9723D have selectable maximum gains of +1dB or +6dB (see Table 6). Bit 5 in the command register selects between the two maximum gain settings. Volume Control The MAX9723 includes a 32-level volume control that adjusts the gain of the output amplifiers according to the code contained in the command register. Volume is programmed through the command register bits [4:0]. Tables 7–10 show all of the available gain settings for the MAX9723A–MAX9723D. The mute attenuation is typically better than 100dB when driving a 32Ω load. Serial Interface The MAX9723 features an I 2 C/SMBus-compatible, 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9723 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9723 is a receive-only slave device relying on the master to generate the SCL signal. The MAX9723 cannot write to the SDA bus except to acknowledge the receipt of data ______________________________________________________________________________________ 11 MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C SDA tBUF tSU, STA tSU, DAT tHD, STA tHD, DAT tLOW tSP tSU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 3. 2-Wire Serial-Interface Timing Diagram from the master. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus. A master device communicates to the MAX9723 by transmitting the proper address followed by the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX9723 SDA line operates as both an input and an open-drain output. A pullup resistor, greater than 500Ω, is required on the SDA bus. The MAX9723 SCL line operates as an input only. A pullup resistor, greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9723 from highvoltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of transmission to the MAX9723. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9723 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. Slave Address The MAX9723 is available with one of two preset slave addresses (see Table 1). The address is defined as the seven most significant bits (MSBs) followed by the Read/Write (R/W) bit. The address is the first byte of information sent to the MAX9723 after the START condition. The MAX9723 is a slave device only capable of being written to. The sent R/W bit must always be a zero when configuring the MAX9723. The MAX9723 acknowledges the receipt of its address even if R/W is set to 1. However, the MAX9723 will not drive SDA. Addressing the MAX9723 with R/W set to 1 causes the master to receive all 1’s regardless of the contents of the command register. Start and Stop Conditions SDA and SCL idle high when the bus is not in use. A master device initiates communication by issuing a Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9723 uses to handshake receipt of each byte of 12 ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C Sr P CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL SCL MAX9723 S 1 2 8 9 NOT ACKNOWLEDGE SDA SDA ACKNOWLEDGE Figure 4. START, STOP, and REPEATED START Conditions Figure 5. Acknowledge Table 1. MAX9723 Address Map Table 3. Shutdown Control, SHDN = 1 PART MODE B7 R/W MAX9723 Disabled 0 MAX9723 Enabled 1 MAX9723 SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 MAX9723A 1 0 0 1 1 0 0 0 MAX9723B 1 0 0 1 1 0 1 0 MAX9723C 1 0 0 1 1 0 0 0 MAX9723D 1 0 0 1 1 0 1 0 Table 2. MAX9723 Command Register B7 B6 B5 B4 B3 B2 B1 B0 SHUTDOWN BassMax ENABLE MAXIMUM GAIN VOLUME data (see Figure 5). The MAX9723 pulls down SDA during the master-generated 9th clock pulse. The SDA line must remain stable and low during the high period of the acknowledge clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may reattempt communication. Write Data Format A write to the MAX9723 includes transmission of a START condition, the slave address with the R/W bit reset to 0 (see Table 1), one byte of data to configure the command register, and a STOP condition. Figure 6 illustrates the proper format for one frame. The MAX9723 only accepts write data, but it acknowledges the receipt of its address byte with the R/W bit set high. The MAX9723 does not write to the SDA bus in the event that the R/W bit is set high. Subsequently, Table 4. BassMax Control MODE B6 BassMax Disabled 0 BassMax Enabled 1 the master reads all 1’s from the MAX9723. Always reset the R/W bit to 0 to avoid this situation. Command Register The MAX9723 has one command register that is used to enable/disable shutdown, enable/disable BassMax, and set the maximum gain and volume. Table 2 describes the function of the bits contained in the command register. Reset B7 to 0 to shut down the MAX9723. The MAX9723 wakes up from shutdown when B7 is set to 1 provided SHDN is high. SHDN must be high and B7 must be set to 1 for the MAX9723 to operate normally (see Table 3). Set B6 to 1 to enable BassMax (see Table 4). The output signal’s low-frequency response will be boosted according to the external components connected between OUT_ and BB_. See the BassMax Gain-Setting Components section in the Applications Information section for details on choosing the external components. ______________________________________________________________________________________ 13 MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C Table 5. MAX9723A and MAX9723B Maximum Gain Control COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9723 S SLAVE ADDRESS 0 ACK COMMAND BYTE Figure 6. Write Data Format Example The MAX9723A and MAX9723B have a maximum gain setting of -5dB or 0dB, while the MAX9723C and MAX9723D have a maximum gain setting of +1dB or +6dB. B5 in the command register programs the maximum gain (see Tables 5 and 6). Adjust the MAX9723’s amplifier gain with the volume control bits [4:0]. The gain is adjustable to one of 32 steps ranging from full mute to the maximum gain programmed by B5. Tables 7–10 list all the possible gain settings for the MAX9723. Figures 7–10 show the volume control transfer functions for the MAX9723. Power-On Reset The contents of the MAX9723’s command register at power-on are shown in Table 11. Applications Information Power Dissipation and Heat Sinking Linear power amplifiers can dissipate a significant amount of power under normal operating conditions. The maximum power dissipation for each package is given in the Absolute Maximum Ratings section under Continuous Power Dissipation or can be calculated by the following equation: PD(MAX) = TJ(MAX) − TA θJA where TJ(MAX) is +150°C, TA is the ambient temperature, and θJA is the reciprocal of the derating factor in °C/W as specified in the Absolute Maximum Ratings section. For example, θJA for the thin QFN package is +59°C/W. The MAX9723 has two power dissipation sources, the charge pump and the two output amplifiers. If the power dissipation exceeds the rated package dissipa14 B5 -5 0 0 1 ACK P ACKNOWLEDGE FROM MAX9723 R/W MAXIMUM GAIN (dB) Table 6. MAX9723C and MAX9723D Maximum Range Control MAXIMUM GAIN (dB) B5 +1 0 +6 1 tion, reduce VDD, increase load impedance, decrease the ambient temperature, or add heatsinking. Large output, supply, and ground traces decrease θJA, allowing more heat to be transferred from the package to surrounding air. Output Dynamic Range Dynamic range is the difference between the noise floor of the system and the output level at 1% THD+N. It is essential that a system’s dynamic range be known before setting the maximum output gain. Output clipping will occur if the output signal is greater than the dynamic range of the system. The DirectDrive architecture of the MAX9723 has increased dynamic range compared to other single-supply amplifiers. Use the THD+N vs. Output Power in the Typical Operating Characteristics to identify the system’s dynamic range. Find the output power that causes 1% THD+N for a given load. This point will indicate what output power causes the output to begin to clip. Use the following equation to determine the peak output voltage that causes 1% THD+N for a given load. VOUT _(P−P) = 2 2(POUT _ 1% × RL ) where POUT_1% is the output power that causes 1% THD+N, RL is the load resistance, and VOUT_(P-P) is the peak output voltage. After V OUT_(P-P) is identified, determine the peak input voltage that can be amplified without clipping: VOUT _(P−P) VIN _(P−P) = AV 10 20 where VIN_(P-P) is the largest peak voltage that can be amplified without clipping, and AV is the voltage gain of ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C B4 B3 B2 B1 B0 (LSB) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 8. MAX9723A and MAX9723B Gain Settings (B5 = 0, Max Gain = -5dB) GAIN (dB) B4 B3 B2 B1 B0 (LSB) GAIN (dB) 1 0 1 1 1 1 1 -5 0 -0.5 1 1 1 1 0 -6 0 1 -1 1 1 1 0 1 -7 1 0 0 -1.5 1 1 1 0 0 -9 1 0 1 1 -2 1 1 0 1 1 -11 1 1 0 1 0 -2.5 1 1 0 1 0 -13 1 1 0 0 1 -3 1 1 0 0 1 -15 1 1 0 0 0 -4 1 1 0 0 0 -17 1 0 1 1 1 -5 1 0 1 1 1 -19 1 0 1 1 0 -6 1 0 1 1 0 -21 1 0 1 0 1 -7 1 0 1 0 1 -23 1 0 1 0 0 -9 1 0 1 0 0 -25 1 0 0 1 1 -11 1 0 0 1 1 -27 1 0 0 1 0 -13 1 0 0 1 0 -29 1 0 0 0 1 -15 1 0 0 0 1 -31 1 0 0 0 0 -17 1 0 0 0 0 -33 0 1 1 1 1 -19 0 1 1 1 1 -35 0 1 1 1 0 -21 0 1 1 1 0 -37 0 1 1 0 1 -23 0 1 1 0 1 -39 0 1 1 0 0 -25 0 1 1 0 0 -41 0 1 0 1 1 -27 0 1 0 1 1 -43 0 1 0 1 0 -29 0 1 0 1 0 -45 0 1 0 0 1 -31 0 1 0 0 1 -47 0 1 0 0 0 -33 0 1 0 0 0 -51 0 0 1 1 1 -35 0 0 1 1 1 -55 0 0 1 1 0 -37 0 0 1 1 0 -59 0 0 1 0 1 -39 0 0 1 0 1 -63 0 0 1 0 0 -41 0 0 1 0 0 -67 0 0 0 1 1 -43 0 0 0 1 1 -71 0 0 0 1 0 -45 0 0 0 1 0 -75 0 0 0 0 1 -47 0 0 0 0 1 -79 0 0 0 0 0 MUTE 0 0 0 0 0 MUTE the amplifier in dB determined by the maximum gain setting (Bit 5) or the combination of the maximum gain setting plus bass boost (see the BassMax Gain-Setting Components section). Component Selection Input-Coupling Capacitor The AC-coupling capacitor (CIN) and internal gain-setting resistor form a highpass filter that removes any DC bias from an input signal (see the Functional Diagram/ Typical Operating Circuit). CIN allows the MAX9723 to bias the signal to an optimum DC level. The -3dB point ______________________________________________________________________________________ 15 MAX9723 Table 7. MAX9723A and MAX9723B Gain Settings (Bit 5 = 1, Max Gain = 0dB) MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C Table 9. MAX9723C and MAX9723D Gain Settings (B5 = 1, Max Gain = +6dB) B4 B3 B2 B1 B0 (LSB) GAIN (dB) B4 B3 B2 B1 B0 (LSB) GAIN (dB) 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 0 5.5 1 1 1 1 0 0 1 1 1 0 1 5 1 1 1 0 1 -1 1 1 1 0 0 4.5 1 1 1 0 0 -3 1 1 0 1 1 4 1 1 0 1 1 -5 1 1 0 1 0 3.5 1 1 0 1 0 -7 1 0 0 1 -9 1 1 0 0 1 3 1 1 1 0 0 0 2 1 1 0 0 0 -11 1 0 1 1 1 1 1 0 1 1 1 -13 0 1 1 0 -15 1 0 1 1 0 0 1 1 0 1 0 1 -1 1 0 1 0 1 -17 1 0 1 0 0 -3 1 0 1 0 0 -19 0 0 1 1 -21 1 0 0 1 1 -5 1 1 0 0 1 0 -7 1 0 0 1 0 -23 -9 1 0 0 0 1 -25 0 0 0 0 -27 1 0 0 0 1 1 0 0 0 0 -11 1 0 1 1 1 1 -13 0 1 1 1 1 -29 1 1 1 0 -31 0 1 1 1 0 -15 0 0 1 1 0 1 -17 0 1 1 0 1 -33 0 1 1 0 0 -19 0 1 1 0 0 -35 1 0 1 1 -37 0 1 0 1 1 -21 0 0 1 0 1 0 -23 0 1 0 1 0 -39 0 1 0 0 1 -25 0 1 0 0 1 -41 1 0 0 0 -45 0 1 0 0 0 -27 0 0 0 1 1 1 -29 0 0 1 1 1 -49 0 0 1 1 0 -31 0 0 1 1 0 -53 0 1 0 1 -57 0 0 1 0 1 -33 0 0 0 1 0 0 -35 0 0 1 0 0 -61 0 0 0 1 1 -37 0 0 0 1 1 -65 -39 0 0 0 1 0 -69 0 0 0 1 0 0 0 0 0 1 -41 0 0 0 0 1 -73 0 0 0 0 0 MUTE 0 0 0 0 0 MUTE of the highpass filter, assuming zero-source impedance, is given by: f−3dB = 16 Table 10. MAX9723C and MAX9723D Gain Settings (B5 = 0, Max Gain = +1dB) 1 2π × RIN × CIN Table 11. Initial Power-Up Command Register Status MODE B7 B6 B5 B4 B3 B2 B1 B0 Power-On Reset 1 1 1 1 1 1 1 1 ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723 MAX9723A AND MAX9723B TRANSFER FUNCTION (BIT 5 = 1) MAX9723A AND MAX9723B TRANSFER FUNCTION (BIT 5 = 0) 0 10 -10 0 -20 -30 GAIN (dB) GAIN (dB) -10 -20 -40 -50 -60 -30 -70 -40 -80 -90 -50 0 6 12 18 24 0 30 6 12 CODE 18 24 30 CODE Figure 7. MAX9723A/MAX9723B Transfer Function with Bit 5 = 1 Figure 8. MAX9723A/MAX9723B Transfer Function with Bit 5 = 0 MAX9723C AND MAX9723D TRANSFER FUNCTION (BIT 5 = 1) MAX9723C AND MAX9723D TRANSFER FUNCTION (BIT 5 = 0) 10 10 0 0 -10 -10 GAIN (dB) GAIN (dB) -20 -30 -40 -50 -20 -30 -60 -40 -70 -80 -50 0 6 12 18 24 30 CODE 0 6 12 18 24 30 CODE Figure 9. MAX9723C/MAX9723D Transfer Function with Bit 5 = 1 Figure 10. MAX9723C/MAX9723D Transfer Function with Bit 5 = 0 where RIN is a minimum of 10kΩ. Choose CIN such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier’s low-frequency response. Use capacitors with low-voltage coefficient dielectrics. Film or C0G dielectric capacitors are good choices for AC-coupling capacitors. Capacitors with high-voltage coefficients, such as ceramics, can result in increased distortion at low frequencies. Charge-Pump Flying Capacitor The charge-pump flying capacitor connected between C1N and C1P affects the charge pump’s load regulation and output impedance. Choosing a flying capacitor that is too small degrades the MAX9723’s ability to provide sufficient current drive and leads to a loss of output voltage. Increasing the value of the flying capacitor improves load regulation and reduces the chargepump output impedance. See the Output Power vs. ______________________________________________________________________________________ 17 MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C GAIN PROFILE WITH AND WITHOUT BassMax 10 fPOLE 8 6 AV (dB) fZERO WITH BassMax 4 2 0 -2 MAX9723A CMD REGISTER CODE = 0xFF R1 = 47kΩ R2 = 22kΩ C3 = 0.1µF WITHOUT BassMax -4 -6 -8 -10 1 10 100 1k 10k FREQUENCY (Hz) Figure 11. BassMax, Gain Profile Example Charge-Pump Capacitance and Load Impedance graph in the Typical Operating Characteristics. Charge-Pump Hold Capacitor The hold capacitor’s value and ESR directly affect the ripple at PVSS. Ripple is reduced by increasing the value of the hold capacitor. Choosing a capacitor with lower ESR reduces ripple and output impedance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Charge-Pump Capacitance and Load Impedance graph in the Typical Operating Characteristics. BassMax Gain-Setting Components The bass-boost low-frequency response, when BassMax is enabled, is set by the ratio of R1 to R2 by the following equation (see Figure 2): A V _ BOOST = 20 × log R1 + R2 R1 − R2 where AV_BOOST is the voltage gain boost in dB at low frequencies. AV_BOOST is added to the gain realized by the volume setting. The absolute gain at low frequencies is equal to: A V _ TOTAL = A V _ VOL + A V _ BOOST where AV_VOL is the gain due to the volume setting, and AV_TOTAL is the absolute gain at low frequencies. 18 To maintain circuit stability, the ratio: R2/(R1 + R2) must not exceed 1/2. A ratio equaling 1/3 is recommended. The switch that shorts BB_ to SGND, when BassMax is disabled, can have an on-resistance as high as 300Ω. Choose a value for R1 that is greater than 40kΩ to ensure that positive feedback is negligible when BassMax is disabled. Table 12 contains a list of R2 values, with R1 = 47kΩ, and the corresponding lowfrequency gain. The low-frequency boost attained by the BassMax circuit is added to the gain realized by the volume setting. Select the BassMax gain so that the output signal will remain within the dynamic range of the MAX9723. Output signal clipping will occur at low frequencies if the BassMax gain boost is excessively large (see the Output Dynamic Range section). Capacitor C3 forms a pole and a zero according to the following equations: R1− R2 2π × C3 × R1× R2 R1+ R2 fZERO = 2π × C3 × R1× R2 fPOLE = fPOLE is the frequency at which the gain boost begins to roll off. fZERO is the frequency at which the bassboost gain no longer affects the transfer function and the volume-control gain dominates. Table 13 contains a list of capacitor values and the corresponding poles and zeros for a given DC gain. See Figure 11 for an example of a gain profile using BassMax. Custom Maximum Gain Setting Using BassMax The circuit in Figure 12 uses the BassMax function to increase the maximum gain of the MAX9723. The gain boost created with the circuit in Figure 12 is added to the maximum gain selected by Bit 5 in the command register. Set the maximum gain with RA and RB using the following equation: RA + RB AV _ TOTAL = AV _ VOL + 20 × log RA − RB where AV_VOL is the gain due to the volume setting, and AV_TOTAL is the absolute passband gain in dB. Capacitor CA blocks any DC offset from being gained, but allows higher frequencies to pass. CA creates a pole that indicates the low-frequency point of the pass band. Choose CA so that the lowest frequencies of ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723 FREQUENCY RESPONSE OF FIGURE 12 10 R MAX9723 9 8 R OUT_ CA AV (dB) 7 AUDIO INPUT 6 5 MAX9723A CMD REGISTER CODE = 0xFF RA = 47kΩ RB = 22kΩ CA = 0.33µF 4 RA 3 2 BassMax ENABLE 1 BB_ RB 0 0.1 1 10 100 1k 10k FREQUENCY (Hz) Figure 12. Using BassMax to Increase MAX9723’s Maximum Gain Figure 13. Increasing the Maximum Gain Using BassMax Table 12. BassMax Gain Examples (R1 = 47kΩ) interest are not attenuated. For a typical application, set fPOLE equal to or below 20Hz. R2 (kΩ) AV GAIN (dB) 39 20.6 33 15.1 27 11.3 22 8.8 15 5.7 10 3.7 fPOLE (Hz) 1 2 π fPOLE × (RA − RB) Figure 13 shows the frequency response of the circuit in Figure 12. With RA = 47kΩ, RB = 22kΩ, and CA = 0.33µF, the passband gain is set to 8.8dB. Layout and Grounding Table 13. BassMax Pole and Zero Examples for a Gain Boost of 8.8dB (R1 = 47kΩ, R2 = 22kΩ) C3 (nF) CA = fZERO (Hz) 100 38 106 82 47 130 68 56 156 56 68 190 47 81 230 22 174 490 10 384 1060 Proper layout and grounding are essential for optimum performance. Connect PGND and SGND together at a single point on the PC board. Connect PVSS to SVSS and bypass with a 1µF capacitor to PGND. Bypass VDD to PGND with a 1µF capacitor. Place the power-supply bypass capacitor and the charge-pump capacitors as close to the MAX9723 as possible. Route PGND and all traces that carry switching transients away from SGND and the audio signal path. Route digital signal traces away from the audio signal path. Make traces perpendicular to each other when routing digital signals over or under audio signals. The thin QFN package features an exposed paddle that improves thermal efficiency. Ensure that the exposed paddle is electrically isolated from PGND, SGND, and V DD. Connect the exposed paddle to SV SS when the board layout dictates that the exposed paddle cannot be left floating. ______________________________________________________________________________________ 19 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723 Functional Diagram/Typical Operating Circuit 1.8V TO 3.6V ANALOG INPUT R5 10kΩ C5 1µF VDD SCL R6 10kΩ CIN 0.47µF INR SDA R VDD VDD I2C INTERFACE R SHDN OUTR R3 47kΩ SVSS SVSS RBB MAX9723 R4 22kΩ VDD VDD VDD LBB C1P C1 1µF C1N C4 0.1µF R2 22kΩ C3 0.1µF CHARGE PUMP SVSS R1 47kΩ R SVSS SGND PGND PVSS SVSS C2 1µF INL CIN 0.47µF OUTL R BASS BOOST CIRCUIT TUNED FOR +8.8dB AT 106Hz. ANALOG INPUT UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout , and recommended reflow temperature profile, as well as the latest information on reliability testing results, go to Maxim’s website at www.maxim-ic.com/ucsp and look up the Application Note: UCSP–A Wafer-Level Chip-Scale Package. 20 Chip Information TRANSISTOR COUNT: 7165 PROCESS: BiCMOS ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C R5 10kΩ 1.8V TO 3.6V R6 10kΩ C5 1µF VDD SDA I2C MASTER SCL OUTL CIN 0.47µF R3 47kΩ INL LBB CIN 0.47µF CODEC C4 0.1µF OUTR C1P C1 1µF R4 22kΩ MAX9723 INR R1 47kΩ C1N RBB PVSS C2 1µF SVSS PGND SGND R2 22kΩ C3 0.1µF A B 3 4 C1N PVSS SDA SGND PGND SCL SHDN INL BBR 13 OUTR 14 OUTL 15 BBL 16 SGND 2 INL TOP VIEW 1 INR TOP VIEW (BUMP SIDE DOWN) SVSS Pin Configurations 12 11 10 9 MAX9723_ 8 SHDN 7 SDA 6 PVSS 5 SCL BBR INR D VDD OUTL OUTR SVSS 1 2 3 4 C1N BBL C1P C1P VDD C PGND MAX9723_ THIN QFN UCSP ______________________________________________________________________________________ 21 MAX9723 System Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX9723 Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 22 E 2 2 ______________________________________________________________________________________ Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C 16L,UCSP.EPS PACKAGE OUTLINE, 4x4 UCSP 21-0101 H 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX9723 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)