AD ADA4807-4ARUZ 3.1 nv/â hz, 1 ma, 180 mhz, rail-to-rail input/output amplifier Datasheet

3.1 nV/√Hz, 1 mA, 180 MHz,
Rail-to-Rail Input/Output Amplifiers
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
VOUT 1
6
+VS
–VS 2
5
DISABLE
+IN 3
4
–IN
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
High resolution analog-to-digital converter (ADC) drivers
Portable and battery-powered instruments and systems
High component density data acquisition systems
Audio signal conditioning
Active filters
12611-058
Figure 1. 6-Lead SC70 and 6-Lead SOT-23 Pin Configuration (ADA4807-1)
VOUT1
–IN1
+IN1
–VS
DISABLE1
10
9
8
7
6
1
2
3
4
5
+VS
VOUT2
–IN2
+IN2
DISABLE2
12611-059
Figure 2. 8-Lead MSOP Pin Configuration (ADA4807-2)
Figure 3. 10-Lead LFCSP Pin Configuration (ADA4807-2)
14 VOUT4
VOUT1 1
APPLICATIONS
12611-001
PIN CONNECTION DIAGRAMS
Low input noise
3.1 nV/√Hz at f = 100 kHz with 29 Hz 1/f corner
0.7 pA/√Hz at f = 100 kHz with 2 kHz 1/f corner
High speed performance with dc precision
180 MHz, −3 dB bandwidth (G = +1, VOUT = 20 mV p-p)
225 V/μs slew rate for 5 V step (rise)
47 ns settling time to 0.1% for 4 V step
±125 μV and 3.7 μV/°C maximum input offset voltage and drift
100 nA and 250 pA/°C maximum input offset current and drift
Low distortion (HD2/HD3), VS = ±5 V, VOUT = 2 V p-p
−141 dBc/−144 dBc at 1 kHz
−112 dBc/−115 dBc at 100 kHz
−95 dBc/−79 dBc at 1 MHz
Low power operation
1.0 mA quiescent supply current per amplifier at ±5 V
Dynamic power scaling
Fully specified at +3 V, +5 V, and ±5 V supplies
Rail-to-rail inputs and outputs
–IN1 2
13 –IN4
12 +IN4
+IN1 3
+VS 4
ADA4807-4
11 –VS
+IN2 5
10 +IN3
–IN2 6
9
–IN3
VOUT2 7
8
VOUT3
12611-104
FEATURES
Figure 4. 14-Lead TSSOP Pin Configuration (ADA4807-4)
GENERAL DESCRIPTION
The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4
(quad) are low noise, rail-to-rail input and output, voltage
feedback amplifiers. These amplifiers combine low power, low
noise, high speed, and dc precision to provide an attractive
solution for a wide range of applications from high resolution
data acquisition instrumentation to high performance batterypowered and high component density systems where power
consumption is of key importance.
With only 1.0 mA of supply current per amplifier, the ADA4807-1/
ADA4807-2/ADA4807-4 feature the lowest input voltage noise
among high speed, rail-to-rail input/output amplifiers in the
industry and offer a wide bandwidth, high slew rate, fast settling
time, and excellent distortion performance. Additionally, these
amplifiers offer very low input offset voltage and drift performance,
making them ideal for driving multiplexed and high throughput
precision 16-/18-bit successive approximation registers (SARs)
and 24-bit - ADCs.
Rev. B
These amplifiers are fully specified at +3 V, +5 V, and ±5 V supplies
and can operate over the industrial −40°C to +125°C
temperature range.
The ADA4807-1 is available in 6-lead SOT-23 and space-saving
6-lead SC70 packages. The ADA4807-2 is available in an 8-lead
MSOP and a compact, 3 mm × 3 mm, 10-lead LFCSP. The
ADA4807-4 is available in a 14-lead TSSOP package.
Table 1. Other Rail-to-Rail Amplifiers
Device
AD8031/AD8032
AD8027/AD8028
AD8029/AD8030/
AD8040
Bandwidth
(MHz)
80
190
125
Slew
Rate
(V/μs)
35
90
62
Voltage
Noise
(nV/√Hz)
15
4.3
16.5
Max.
VOS
(mV)
±1.5
0.8
5
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ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Slew, Transient, Settling Time, and Crosstalk............................. 18
Applications ....................................................................................... 1
Distortion and Noise.................................................................. 20
Pin Connection Diagrams ............................................................... 1
Output Characteristics............................................................... 22
General Description ......................................................................... 1
Overdrive Recovery and Turn On/Turn Off Times .............. 23
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 24
Specifications..................................................................................... 3
Disable Circuitry ........................................................................ 25
±5 V Supply ................................................................................... 3
Input Protection ......................................................................... 25
5 V Supply...................................................................................... 5
Noise Considerations ................................................................. 25
3 V Supply...................................................................................... 7
Applications Information .............................................................. 26
Absolute Maximum Ratings............................................................ 9
Capacitive Load Drive ............................................................... 26
Maximum Power Dissipation ..................................................... 9
Low Noise FET Operational Amplifier ................................... 26
Thermal Resistance ...................................................................... 9
Power Mode ADC Driver ......................................................... 27
ESD Caution .................................................................................. 9
ADC Driving............................................................................... 28
Pin Configurations and Function Descriptions ......................... 10
ADC Driving with Dynamic Power Scaling ........................... 29
Typical Performance Characteristics ........................................... 13
Layout, Grounding, and Bypassing .......................................... 30
Frequency Response................................................................... 13
Outline Dimensions ....................................................................... 31
Frequency and Supply Current ................................................. 15
Ordering Guide .......................................................................... 33
DC and Input Common-Mode Performance ......................... 16
REVISION HISTORY
9/15—Rev. A to Rev. B
Added ADA4807-4 ............................................................. Universal
Changes to Features Section, General Description Section, and
Table 1 .......................................................................................................... 1
Added Figure 4, Renumbered Sequentially .................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 7
Deleted Figure 6, Renumbered Sequentially............................... 10
Changes to Figure 6 ........................................................................ 10
Added Figure 9 and Table 9, Renumbered Sequentially ........... 12
Changes to Figure 20 ...................................................................... 14
Added Figure 21.............................................................................. 14
Added Figure 31 and Figure 32..................................................... 16
Added Figure 35.............................................................................. 17
Changes to Figure 39 ...................................................................... 18
Added Figure 42.............................................................................. 19
Deleted Figure 50, Figure 51, Figure 53, and Figure 54 ............. 19
Added Figure 46.............................................................................. 20
Added Figure 49 and Figure 51..................................................... 21
Added Figure 59 and Figure 61..................................................... 23
Changes to DISABLE Circuitry Section ...................................... 25
Added Low Noise FET Operational Amplifier Section............. 26
Added Figure 70, Figure 71, Figure 72, and Power Mode ADC
Driver Section ................................................................................. 27
Added ADC Driving Section and Figure 73 through Figure 77..... 28
Added ADC Driving with Dynamic Power Scaling Section,
Figure 78, Figure 79, and Figure 80 .............................................. 29
Added Figure 58 ............................................................................. 33
Changes to Ordering Guide .......................................................... 33
4/15—Rev. 0 to Rev. A
Added ADA4807-2 ............................................................. Universal
Changes to Features Section, General Description
Section, and Pin Connection Diagrams Heading .........................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................7
Changes to Table 6 and Figure 4 ......................................................9
Added Figure 7, Figure 8, and Table 8; Renumbered Sequentially ....11
Reorganized Layout, Typical Performance Characteristics
Section.............................................................................................. 12
Added Figure 36 ............................................................................. 16
Changes to Figure 37 Caption, Figure 38 Caption, Figure 39
Caption, and Figure 40 Caption ................................................... 17
Changes to Figure 44 and Figure 47............................................. 18
Change to Theory of Operation Section ..................................... 20
Changes to DISABLE Circuitry Section, Table 9, and Noise
Considerations Section .................................................................. 21
Added Figure 65 and Figure 66 .................................................... 23
Changes to Ordering Guide .......................................................... 25
12/14—Revision 0: Initial Version
Rev. B | Page 2 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
SPECIFICATIONS
±5 V SUPPLY
TA = 25°C, VS = ±5 V, RLOAD = 1 kΩ to midsupply, RF = 0 Ω, G = +1, −VS ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
Third Harmonic (HD3)
Peak-to-Peak Noise
Input Voltage Noise
Input Voltage Noise 1/f Corner
Input Current Noise
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
−VS ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
Test Conditions/Comments
Min
Typ
Max
Unit
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 5 V step, 20% to 80%, rise/fall
G = +1, VOUT = 4 V step
180
28
225/250
47
MHz
MHz
V/μs
ns
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2,
ADA4807-4
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
f = 1 kHz
f = 10 Hz
−141
−112
−95
−84
dBc
dBc
dBc
dBc
−144
−115
−79
160
3.1
3.3
5.8
29
0.7
10
2
dBc
dBc
dBc
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
f = 100 kHz
f = 10 Hz
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−VS ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−VS ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−750
−850
120
±20
±20
±140
±140
0.7
−1.2
530
2.5
8
25
30
130
+125
+175
+750
+850
3.7
−1.6
1000
3.6
100
150
250
45
35
1
1
VICM = −3 V to +2 V
Rev. B | Page 3 of 33
−VS − 0.2
96
+VS + 0.2
110
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
pA/°C
dB
MΩ
kΩ
pF
pF
V
dB
ADA4807-1/ADA4807-2/ADA4807-4
Parameter
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
DISABLE Input Current
Low
High
DISABLE On Time
DISABLE Off Time
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
Low
Linear Output Current3
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio (PSRR)
Positive
Negative
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
Disabled
Enabled
<1.3
>1.7
V
V
Disabled
Enabled
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
−470
−3
1.3
1.8
nA
nA
μs
270
340
ns
RLOAD = 1 kΩ
+VS − 0.08
−VS + 0.1
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN =+VS, RLOAD= 0 Ω to
10 Ω
Sinking, G= +1, VIN = −VS, RLOAD = 0 Ω to 10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
+VS − 0.04
−VS + 0.07
50
60
80
V
V
mA
mA
mA
80
17
mA
% overshoot
2.7
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
+VS = 3 V to 5 V, −VS = −5 V
+VS = 5 V, −VS = −3 V to −5 V
1.0
2.4
98
98
107
120
11
1.1
4.0
V
mA
μA
dB
dB
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.
1
2
Rev. B | Page 4 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
5 V SUPPLY
TA = 25°C, VS = 5 V, RLOAD = 1 kΩ to midsupply, RF = 0 Ω, G = +1, 0 V ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
Third Harmonic (HD3)
Peak-to-Peak Noise
Input Voltage Noise
Input Voltage Noise 1/f Corner
Input Current Noise
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
CMRR
Test Conditions/Comments
Min
Typ
Max
Unit
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 2 V step, 20% to 80%, rise/fall
G = +1, VOUT = 2 V step
170
28
145/160
40
MHz
MHz
V/μs
ns
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2,
ADA4807-4
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
f = 1 kHz
f = 10 Hz
−141
−111
−93
−83
dBc
dBc
dBc
dBc
−153
−115
−78
160
3.1
3.3
5.8
29
0.7
10
2
dBc
dBc
dBc
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
f = 100 kHz
f = 10 Hz
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−720
−850
113
±20
±20
±110
±110
0.7
−1.2
500
2.6
8
25
30
130
+125
+175
+720
+850
3.7
−2.0
1000
3.8
100
150
250
45
35
1
1
−VS − 0.2
96
VICM = 1 V to 3 V
Rev. B | Page 5 of 33
+VS + 0.2
110
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
pA/°C
dB
MΩ
kΩ
pF
pF
V
dB
ADA4807-1/ADA4807-2/ADA4807-4
Parameter
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
DISABLE Input Current
Low
High
DISABLE On Time
DISABLE Off Time
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
Low
Linear Output Current3
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
PSRR
Positive
Negative
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
Disabled
Enabled
<1.3
>1.8
V
V
Disabled
Enabled
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
−360
−1.3
450
700
nA
nA
ns
270
450
ns
RLOAD = 1 kΩ
+VS − 0.05
−VS + 0.05
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN = +VS, RLOAD = 0 Ω
to 10 Ω
Sinking, G = +1, VIN = −VS, RLOAD = 0 Ω to
10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
+VS − 0.03
−VS + 0.04
50
60
80
V
V
mA
mA
mA
80
mA
24
% overshoot
2.7
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
+VS = 1.5 V to 3.5 V, −VS = −2.5 V
+VS = 2.5 V, −VS = −1.5 V to −3.5 V
950
1.3
98
98
115
130
11
1000
2.0
V
μA
μA
dB
dB
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.
1
2
Rev. B | Page 6 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
3 V SUPPLY
TA = 25°C, VS = 3 V, RLOAD = 1 kΩ to midsupply, RF = 0 Ω, G = +1, 0 V ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
Third Harmonic (HD3)
Peak-to-Peak Noise
Input Voltage Noise
Input Voltage Noise 1/f Corner
Input Current Noise
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
CMRR
Test Conditions/Comments
Min
Typ
Max
Unit
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 2 V step, 20% to 80%, rise/fall
G = +1, VOUT = 2 V step
165
28
118/237
40
MHz
MHz
V/μs
ns
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
f = 10 kHz
f = 10 Hz
−98
−85
−65
−94
−91
−68
160
3.1
3.3
5.8
29
0.7
10
2
dBc
dBc
dBc
dBc
dBc
dBc
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
f = 100 kHz
f = 10 Hz
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−720
−850
104
±20
±20
±125
±125
0.7
−1.2
500
2.7
8
25
40
113
+125
+175
+720
+850
3.8
−2.0
1000
3.8
130
150
230
45
35
1
1
−VS − 0.2
92
VICM = 0.3 V to 1.3 V
Rev. B | Page 7 of 33
+VS + 0.2
110
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
pA/°C
dB
MΩ
kΩ
pF
pF
V
dB
ADA4807-1/ADA4807-2/ADA4807-4
Parameter
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
DISABLE Input Current
Low
High
DISABLE On Time
DISABLE Off Time
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
Low
Linear Output Current3
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
PSRR
Positive
Negative
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
Disabled
Enabled
<1.1
>1.5
V
V
Disabled
Enabled
−325
−500
nA
nA
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
500
700
ns
270
460
ns
RLOAD = 1 kΩ
+VS − 0.04
−VS + 0.04
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN = +VS, RLOAD = 0 Ω to
10 Ω
Sinking, G = +1, VIN = −VS, RLOAD = 0 Ω to
10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
+VS − 0.02
−VS + 0.03
50
60
65
V
V
mA
mA
mA
70
mA
30
% overshoot
2.7
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
+VS = 1.5 V to 3.5 V, −VS = −1.5 V
+VS = 1.5 V, −VS = −1.5 V to −3.5 V
915
1.0
97
97
113
130
11
1000
2.0
V
μA
μA
dB
dB
The disable pin is DISABLE on the ADA4807-1 and DISABLE1 or DISABLE2 for the ADA4807-2 LFCSP package, hereafter referred to as DISABLE for the ADA4807-1/ADA4807-2.
See the Disable Circuitry section.
3
See Figure 53 and Figure 56.
1
2
Rev. B | Page 8 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Parameter
Supply Voltage
Internal Power Dissipation
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range (All Packages)
Lead Temperature (Soldering 10 sec)
Rating
11 V
See Figure 5
±VS ± 0.2 V
±1.4 V
See power
derating curves in
Figure 5
−65°C to +125°C
300°C
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
6-Lead SC70, 4-Layer Board
6-Lead SOT-23, 4-Layer Board
8-Lead MSOP
10-Lead LFCSP
14-Lead TSSOP
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
MAXIMUM POWER DISSIPATION (W)
4.0
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
ADA4807-1/ADA4807-2/ADA4807-4 is limited by the associated
rise in junction temperature. The maximum safe junction
temperature for plastic encapsulated devices is determined by
the glass transition temperature of the plastic, approximately
150°C. Exceeding this limit temporarily can cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
θJA
209
223
123
51
130
3.5
3.0
2.5
LFCSP
2.0
1.5
1.0
SOT-23
0.5
0
–40
MSOP
TSSOP
SC70
–25
–10
5
20
35
50
65
80
AMBIENT TEMPERATURE (°C)
95
110
125
12611-003
Table 5.
Figure 5. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION
Although the ADA4807-1/ADA4807-2/ADA4807-4 are
internally short-circuit protected, this may not be sufficient to
guarantee that the maximum junction temperature (150°C) is
not exceeded under all conditions. To ensure proper operation,
it is necessary to observe the power derating curves shown in
Figure 5.
Rev. B | Page 9 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
VOUT 1
6
+VS
–VS 2
5
DISABLE
+IN 3
4
–IN
12611-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. ADA4807-1 Pin Configuration
Table 7. ADA4807-1 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VOUT
−VS
+IN
−IN
DISABLE
+VS
Description
Output
Negative Supply
Noninverting Input
Inverting Input
Active Low Power-Down
Positive Supply
Rev. B | Page 10 of 33
1
2
3
4
5
10
9
8
7
6
+VS
VOUT2
–IN2
+IN2
DISABLE2
NOTES
1. THE EXPOSED PAD CAN BE CONNECTED TO
GROUND OR POWER PLANES, OR IT CAN
BE LEFT FLOATING.
12611-060
VOUT1
–IN1
+IN1
–VS
DISABLE1
ADA4807-1/ADA4807-2/ADA4807-4
Figure 7. ADA4807-2 10-Lead LFCSP Pin Configuration
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
12611-061
Data Sheet
Figure 8. ADA4807-2 8-Lead MSOP Pin Configuration
Table 8. ADA4807-2 Pin Function Descriptions
Pin No.
10-Lead LFCSP
8-Lead MSOP
1
1
2
2
3
3
4
4
5
Not applicable
6
Not applicable
7
5
8
6
9
7
10
8
Not applicable
Mnemonic
VOUT1
−IN1
+IN1
−VS
DISABLE1
DISABLE2
+IN2
−IN2
VOUT2
+VS
EPAD
Description
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Active Low Power-Down 1.
Active Low Power-Down 2.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
Exposed Pad. For the 10-Lead LFCSP, the exposed pad can be connected to ground
or power planes, or it can be left floating.
Rev. B | Page 11 of 33
Data Sheet
VOUT1 1
14
VOUT4
–IN1 2
13
–IN4
12
+IN4
11
–VS
+IN1 3
+VS 4
ADA4807-4
+IN2 5
10
+IN3
–IN2 6
9
–IN3
VOUT2 7
8
VOUT3
12611-110
ADA4807-1/ADA4807-2/ADA4807-4
Figure 9. ADA4807-4 Pin Configuration
Table 9. ADA4807-4 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
VOUT1
−IN1
+IN1
+VS
+IN2
−IN2
VOUT2
VOUT3
−IN3
+IN3
−VS
+IN4
−IN4
VOUT4
Description
Output 1
Inverting Input 1
Noninverting Input 1
Positive Supply
Noninverting Input 2
Inverting Input 2
Output 2
Output 3
Inverting Input 3
Noninverting Input 3
Negative Supply
Noninverting Input 4
Inverting Input 4
Output 4
Rev. B | Page 12 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
TYPICAL PERFORMANCE CHARACTERISTICS
27
24
21
18
15
12
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
0.1
6
VS RANGE = ±2.5V TO ±5V
G = +1
3 R
LOAD = 1kΩ
VS = ±2.5V
RLOAD = 1kΩ
VOUT = 20mV p-p
G = +10
CLOSED-LOOP GAIN (dB)
G = +2
G = +1
G = –1
–9
2V p-p
–12
–15
100
1000
–24
0.1
1
6
3
0
0
±5.0V
–3
–6
–9
–12
±1.5V
–15
VOUT = 2V p-p
G = +1
RLOAD = 1kΩ
±1.5V
–3
–6
–9
–12
–15
–18
±5.0V
–21
–24
–18
1000
FREQUENCY (MHz)
–30
0.1
12611-007
100
Figure 14. Large Signal Frequency Response for Various Supplies
6
–40°C
+25°C
+85°C
+125°C
3
0
CLOSED-LOOP GAIN (dB)
–3
–6
–9
–12
–15
–21
–24
0.1
1
–3
–6
–9
–12
–40°C
–15
FREQUENCY (MHz)
100
1000
Figure 12. Small Signal Frequency Response for Various Temperatures
+25°C
–21
–27
10
+125°C
–18
–24
VS RANGE = ±1.5V TO ±5V
G = +1
VOUT = 20mV p-p
RLOAD = 1kΩ
VS RANGE = ±2.5V TO ±5V
G = +1
VOUT = 2V p-p
RLOAD = 1kΩ
–30
0.1
12611-008
CLOSED-LOOP GAIN (dB)
0
–18
1000
1
10
FREQUENCY (MHz)
100
1000
12611-011
3
100
10
1
FREQUENCY (MHz)
Figure 11. Small Signal Frequency Response for Various Supplies
6
±2.5V
–27
±2.5V
10
1
1000
Figure 13. Frequency Response for Various Output Amplitudes, G = +1
VOUT = 20mV p-p
G = +1
RLOAD = 1kΩ
–21
0.1
100
10
FREQUENCY (MHz)
12611-009
10
12611-010
1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
–6
–21
Figure 10. Small Signal Frequency Response for Various Gains,
RF = 499 Ω
3
20mV p-p
–3
–18
FREQUENCY (MHz)
6
200mV p-p
0
G = +5
12611-006
CLOSED-LOOP GAIN (dB)
FREQUENCY RESPONSE
Figure 15. Large Signal Frequency Response for Various Temperatures
Rev. B | Page 13 of 33
ADA4807-1/ADA4807-2/ADA4807-4
1kΩ
CLOSED-LOOP GAIN (dB)
0
–3
–6
–9
100Ω
–12
–15
–18
–3
–6
–12
–18
–21
–27
1
10
100
1000
FREQUENCY (MHz)
–30
0.1
12611-012
–24
0.1
1000
Figure 19. Large Signal Frequency Response for Various Resistive Loads
0.6
12
G = +1
0.5 RLOAD = 1kΩ
VS = ±2.5V
G = +1
VOUT = 20mV p-p
RLOAD = 1kΩ
9
6
0.4
3
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
100
10
1
FREQUENCY (MHz)
Figure 16. Small Signal Frequency Response for Various Resistive Loads
0
–3
0pF
–6
–9
5pF
–12
–15
10pF
–18
15pF
1
100
10
0.2
0.1
0
–0.1
–0.2
–0.3
1000
FREQUENCY (MHz)
Figure 17. Small Signal Frequency Response for Various Capacitive Loads
–0.6
0.1
1
3
VCM = 0V
Vs = ±2.5V, ±5V
VOUT = 200mV p-p
G=2
RF = 499Ω
RLOAD = 1kΩ
Vs = ±2.5V, ±5V
VOUT = 20mV p-p
0
NORMALIZED GAIN (dB)
0
–3
–6
VCM = +VS – 0.5V
–9
–12
–15
–3
–6
–9
–12
–15
Vs = ±2.5V, ±5V
VOUT = 2V p-p
–18
–18
–21
100
FREQUENCY (MHz)
Figure 18. Small Signal Frequency Response for
Various Input Common-Mode Voltages (VCM)
1000
–24
12611-013
10
100
Figure 20. 0.1 dB Flatness Frequency Response for Various Output Amplitudes
6
VS = ±2.5V
G = +1
VOUT = 20mV p-p
RLOAD = 1kΩ
1
10
FREQUENCY (MHz)
6
–21
0.1
VS RANGE = ±2.5V TO ±5V
VOUT = 2V p-p
–0.5
12611-050
–24
0.1
VS RANGE = ±1.5V TO ±5V
VOUT = 20mV p-p
0.3
–0.4
–21
CLOSED-LOOP GAIN (dB)
100Ω
–15
–24
–21
3
1kΩ
–9
12611-015
CLOSED-LOOP GAIN (dB)
VS RANGE = ±2.5V TO ±5V
3 VOUT = 2V p-p
G = +1
0
12611-221
3
6
VS = ±2.5V
VOUT = 20mV p-p
G = +1
Vs = ±5V
VOUT = 4V p-p
0.1
1
10
FREQUENCY (MHz)
100
1000
12611-121
6
Data Sheet
Figure 21. Frequency Response for Various Output Amplitudes, G = +2
Rev. B | Page 14 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
FREQUENCY AND SUPPLY CURRENT
20
–40
VS = ±2.5V
G = +1
ON
DISABLE = +VS
0
–60
–20
–70
–40
CMRR (dB)
–60
OFF
DISABLE = –VS
–80
–80
–90
–100
–100
–110
–120
0.1
1
10
100
1000
FREQUENCY (MHz)
–130
0.001
12611-017
–140
0.01
0.01
Figure 22. Off Isolation vs. Frequency
100
140
–40
80
120
–50
10
100
60
100
40
80
20
60
0
40
–20
20
10
100
VS = ±5V
ΔVS = –16dBm
–PSRR
–60
PSRR (dB)
VS = ±2.5V
PHASE (Degrees)
–30
–70
+PSRR
–80
–90
–100
0.01
0.1
1
10
100
–110
0
1000
–120
0.001
12611-018
–40
0.001
FREQUENCY (MHz)
0.1
0.01
1
FREQUENCY (MHz)
Figure 23. Open-Loop Gain and Phase vs. Frequency
Figure 26. PSRR vs. Frequency
1.6
2.5
1.4
2.0
DISABLE SUPPLY CURRENT (μA)
DISABLE = –VS
VS = ±5.0V
1.2
1.0
0.8
VS = ±1.5V
VS = ±2.5V
0.6
0.4
0.2
+IS
1.5
1.0
0.5
0
–0.5
–1.0
–IS
0
–40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
–2.0
0
1
2
3
4
5
POWER SUPPLY, ±VS (V)
Figure 24. Quiescent Supply Current vs. Temperature
Figure 27. DISABLE Supply Current vs. Power Supply, ±VS
Rev. B | Page 15 of 33
6
12611-022
–1.5
12611-019
QUIESCENT SUPPLY CURRENT (mA)
OPEN-LOOP GAIN (dB)
1
Figure 25. CMRR vs. Frequency
160
120
0.1
FREQUENCY (MHz)
12611-020
–120
12611-226
OFF ISOLATION (dB)
VS = ±2.5V
ΔVCM = 0dBm
–50
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
DC AND INPUT COMMON-MODE PERFORMANCE
350
NUMBERING UNITS
300
NPN
VS = ±5V
VCM = +VS – 0.5V
450 UNITS
x = –32.7µV
σ = 109.4µV
60
PNP
VS = ±5V
VCM = 0V
450 UNITS
x = –1.5µV
σ = 17.9µV
50
NUMBER OF AMPLIFIERS
400
250
200
150
100
VS = ±2.5V
–40°C TO +125°C
COUNT = 361 AMPLIFIERS
x = 0.7µV/°C
σ = 0.5µV/°C
40
30
20
10
–400
–200
0
200
400
INPUT REFERRED OFFSET VOLTAGE (µV)
600
0
12611-122
0
–600
–2.8
90
PNP
VS = ±5V
VCM = 0V
450 UNITS
x = –1.58nA
σ = 6.62nA
80
200
150
100
50
0.2
0.8
1.4
2.0
2.6
3.2
3.8
70
VS = ±2.5V
–40°C TO +125°C
COUNT = 283 AMPLIFIERS
x = 30pA/°C
σ = 35pA/°C
60
50
40
30
20
100
150
0
–200
–80
–20
40
100
160
220
280
INPUT OFFSET CURRENT DRIFT (pA/°C)
Figure 32. Input Offset Current Drift Distribution, VCM = 0 V
40
VS = ±5.0V
10 UNITS
30
INPUT OFFSET CURRENT (nA)
0.5
0
–0.5
–1.0
–1.5
VS = ±5.0V
10 UNITS
20
10
0
–10
–20
–3.9
–2.6
–1.3
0
1.3
2.6
3.9
5.2
INPUT COMMON-MODE VOLTAGE (V)
Figure 30. Input Bias Current vs. Input Common-Mode Voltage
–40
–5.2
–3.9
–2.6
–1.3
0
1.3
2.6
3.9
5.2
INPUT COMMON-MODE VOLTAGE (V)
Figure 33. Input Offset Current vs. Input Common-Mode Voltage
Rev. B | Page 16 of 33
12611-126
–30
12611-124
–2.0
–5.2
–140
12611-032
–50
0
50
INPUT OFFSET CURRENT (nA)
12611-123
–100
Figure 29. Input Offset Current Distribution
INPUT BIAS CURRENT (µA)
–0.4
10
0
–150
1.0
–1.0
Figure 31. Input Referred Offset Voltage Drift Distribution, VCM = 0 V
NUMBER OF AMPLIFIERS
NUMBERING UNITS
250
NPN
VS = ±5V
VCM = +VS – 0.5V
450 UNITS
x = –1.18nA
σ = 22.59nA
–1.6
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 28. Input Referred Offset Voltage Distribution for the ADA4807-1 and
ADA4807-2
300
–2.2
12611-031
50
100
0
–100
–200
–3.9
–2.6
–1.3
0
1.3
2.6
INPUT COMMON-MODE VOLTAGE (V)
3.9
5.2
Figure 34. Input Referred Offset Voltage vs. Input Common-Mode Voltage
Rev. B | Page 17 of 33
9
OIL BATH TEMPERATURE
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
15
–1
14
–2
13
–3 VS = ±2.5V
8 UNITS, SOLDERED TO PCB
–4
0
100
200
300
12
11
400
500
600
TIME (Hours)
Figure 35. Long-Term Input Offset Voltage (VOS) Drift
TEMPERATURE (°C)
CHANGING IN INPUT OFFSET VOLTAGE (µV)
200
–300
–5.2
25
10
VS = ±5V
10 UNITS
12611-125
INPUT REFERRED OFFSET VOLTAGE (µV)
300
ADA4807-1/ADA4807-2/ADA4807-4
12611-234
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
SLEW, TRANSIENT, SETTLING TIME, AND CROSSTALK
280
G = +1
RLOAD = 1kΩ
260
1.5
VS = ±5V
VOUT = 5V p-p
G = +1
RLOAD = 1kΩ
FALLING EDGE
1.0
OUTPUT VOLTAGE (V)
SLEW RATE (V/µs)
240
RISING EDGE
220
200
180
FALLING EDGE
VS = ±2.5V
VOUT = 2V p-p
160
RISING EDGE
±2.5V
0.5
0
±1.5V
–0.5
±5V
140
–1.0
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–1.5
12611-023
100
–40
0
100
200
300
400
500
600
700
800
900
TIME (ns)
Figure 36. Slew Rate vs. Temperature
12611-025
120
Figure 38. Large Signal Transient Response for Various Supplies
0.5
15
OUTPUT VOLTAGE (% of Final Value)
0.4
5
0
–5
–15
G = +1
RLOAD = 1kΩ
VS RANGE = ±1.5V TO ±5V
0
0.1
0.2
0.3
0.4
0.5
0.3
VS = ±2.5V
OUTPUT STEP = 2V p-p
0.2
0.1
0
–0.1
VS = ±5V
OUTPUT STEP = 5V p-p
–0.2
–0.3
–0.4
0.6
0.7
TIME (µs)
–0.5
0
20
40
60
TIME (ns)
Figure 39. Settling Time to 0.1%
Figure 37. Small Signal Transient Response for Various Supplies
Rev. B | Page 18 of 33
80
90
12611-238
–10
12611-024
OUTPUT VOLTAGE (mV)
10
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
15
0
VS = ±2.5V
G = +1
–20
–40
5
CROSSTALK (dB)
0pF
5pF
10pF
15pF
0
–5
VOUT1
–80
–100
–10
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TIME (µs)
0.8
–140
100
12611-027
–15
0
–20
VS = ±2.5V
VOUT = 2V p-p
DISABLE = 2.5V
–40
–60
–80
–100
DRIVING AMP 1
–120
DRIVING AMP 2
–160
0.0001
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
1000
12611-036
–140
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 40. Small Signal Transient Response for Various Capacitive Loads
CROSSTALK (dB)
–60
Figure 41. ADA4807-2 Crosstalk vs. Frequency
Rev. B | Page 19 of 33
Figure 42. ADA4807-4 All Hostile Crosstalk
1G
12611-241
OUTPUT VOLTAGE (mV)
10
VS = ±2.5V
VOUT2, VOUT3, VOUT4 = 1V p-p
G = +1
RLOAD = 1kΩ
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
DISTORTION AND NOISE
HARMONIC DISTORTION (dBc)
VS = ±1.5V, HD2
VS = ±1.5V, HD3
–80
–100
VS = ±5V, HD2
–120
VS = ±5V, HD3
–140
–160
–180
VS = ±2.5V, HD2
1
VS = ±2.5V, HD3
10
100
1000
10000
FREQUENCY (kHz)
Figure 43. ADA4807-1 Harmonic Distortion vs. Frequency for Various Supplies
0
HARMONIC DISTORTION (dBc)
–80
G = +2, HD2
–100
G = +1, HD2
–120
G = +5, HD3
–140
G = +2, HD3
–160
–180
G = +1, HD3
1
10
–60
RLOAD = 100Ω
HD2
–80
RLOAD = 1kΩ
HD2
–100
RLOAD = 1kΩ
HD3
–120
RLOAD = 100Ω
HD3
–140
–160
100
1000
10000
FREQUENCY (kHz)
12611-028
HARMONIC DISTORTION (dBc)
G = +5, HD2
10
G = +1
VOUT = 2V p-p
VS = ±2.5V
–40
–60
1
Figure 46. ADA4807-2/ADA4807-4 Harmonic Distortion vs. Frequency for
Various Supplies
–20
–40
0.1
FREQUENCY (MHz)
VS = ±2.5V
VOUT = 2V p-p
RLOAD = 1kΩ
–20
G = +1
RLOAD = 1kΩ
VOUT = 2V p-p
–180
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 44. ADA4807-1 Harmonic Distortion vs. Frequency for Various Gains
–60
0
VS = ±2.5V
G = +1
RLOAD = 1kΩ
–70
–20
f = 1MHz
–80
–90
–100
f = 100kHz
–110
–120
f = 1kHz
–130
–30
VS = 10V
VS = 5V
VS = 3V
–40
–50
–60
HD2
–70
HD2
HD2
HD3
–80
HD3
–90
–100
–110
HD3
–120
–140
–150
0.5
G=+1
VOUT = 2V p-p
RLOAD = 1kΩ
f = 100kHz
–10
–130
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOUT (V p-p)
Figure 45. Total Harmonic Distortion vs. Output Voltage (VOUT)
12611-245
TOTAL HARMONIC DISTORTION (dB)
–50
Figure 47. ADA4807-1 Harmonic Distortion vs. Frequency for Various
Resistive Loads
HARMONIC DISTORTION (dBc)
–40
12611-030
–60
12611-127
HARMONIC DISTORTION (dBc)
–40
0
VS = ±1.5V
–10
VS = ±2.5V
–20
VS = ±5V
HD2
–30
HD3
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0.001
0.01
12611-145
G = +1
RLOAD = 1kΩ
VOUT = 2V p-p
–140
0
1
2
3
4
5
6
7
8
9
10
INPUT COMMON-MODE VOLTAGE (V)
Figure 48. Harmonic Distortion vs. Input Common-Mode Voltage
Rev. B | Page 20 of 33
12611-037
–20
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
4
3
2
THD = –80dB
THD = –90dB
THD = –100dB
ADA4807-1,
ADA4807-2
ADA4807-4
0
10
1
1000
100
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION (%)
4
THD = –80dB
THD = –90dB
THD = –100dB
ADA4807-1,
ADA4807-2
ADA4807-4
1
0.01
16Ω
0.0001
32Ω
0.1
1
OUTPUT VOLTAGE (V rms)
12611-132
600Ω
0.01
100
Figure 51. Output Voltage vs. Frequency for VS = ±5 V
0.1
0.001
10
FREQUENCY (kHz)
VS = ±2.5V
G = +1
f = 1kHz
0.00001
0.001
6
0
Figure 49. Output Voltage vs. Frequency for VS = ±2.5 V
1
8
2
12611-248
1
VS = ±5V
G = +2
RF = 499Ω
RLOAD = 1kΩ
10
OUTPUT VOLTAGE (V p-p)
5
OUTPUT VOLTAGE (V p-p)
12
VS = ±2.5V
G = +2
RF = 499Ω
RLOAD = 1kΩ
Figure 50. Total Harmonic Distortion vs. Output Voltage for Various
Resistive Loads
Rev. B | Page 21 of 33
1000
12611-250
6
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
OUTPUT CHARACTERISTICS
1
10
100
1k
10k
100k
1M
0.1
100M
10M
FREQUENCY (Hz)
1
+125°C
1.0
0.8
0.6
0.4
–40°C
0.2
0
0
10
20
30
40
50
60
70
80
90
100
LOAD CURRENT (mA)
DISABLED OUTPUT IMPEDANCE (kΩ)
10
1
0.1
10
100
FREQUENCY (MHz)
1000
12611-141
ENABLED OUTPUT IMPEDANCE (Ω)
1.8
10k
100k
1M
CURRENT NOISE (pA/√Hz)
0.1
100M
10M
VS = ±2.5V
G = +1
1.6
+125°C
1.4
+25°C
1.2
+85°C
1.0
0.8
–40°C
0.6
0.4
0.2
0
1000
100
1
1k
0
10
20
30
40
50
60
70
80
90
100
Figure 56. Negative Rail Output Saturation Voltage (−VS + VOUT) vs.
Load Current for Various Temperatures
VS = ±2.5V
DISABLE = +VS
0.01
0.1
100
LOAD CURRENT (mA)
Figure 53. Positive Rail Output Saturation Voltage (+VS – VOUT) vs.
Load Current for Various Temperatures
1000
10
FREQUENCY (Hz)
NEGATIVE RAIL OUTPUT SATURATION VOLTAGE (V)
(–VS + VOUT)
+25°C
1.2
12611-040
POSITIVE RAIL OUTPUT SATURATION VOLTAGE (V)
(+VS – VOUT)
1.4
+85°C
CURRENT NOISE
Figure 55. Input Voltage Noise and Current Noise vs. Frequency,
VCM = +VS − 0.5 V
VS = ±2.5V
G = +1
1.6
1
1
0.1
Figure 52. Input Voltage Noise and Current Noise vs. Frequency,
VCM = 0 V
1.8
10
VOLTAGE NOISE
12611-134
1
CURRENT NOISE
10
100
12611-043
1
VS RANGE = ±1.5V TO ±5V
NPN ACTIVE
VS = ±2.5V
DISABLE = –VS
100
10
1
0.1
0.01
0.001
0.1
1
10
100
FREQUENCY (MHz)
Figure 57. Disabled Output Impedance vs. Frequency
Figure 54. Enabled Output Impedance vs. Frequency
Rev. B | Page 22 of 33
1000
12611-144
VOLTAGE NOISE
INPUT VOLTAGE NOISE (nV/√Hz)
10
CURRENT NOISE (pA/√Hz)
10
0.1
100
100
VS RANGE = ±1.5V TO ±5V
PNP ACTIVE
12611-136
INPUT VOLTAGE NOISE (nV/√Hz)
100
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
OVERDRIVE RECOVERY AND TURN ON/TURN OFF TIMES
1.5
VS = ±2.5V
G = +1
RLOAD = 1kΩ
VOUT
0
–1
–2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TIME (µs)
0.5
1
0
0
–0.5
–1
–1.0
–2
–1.5
12611-041
–3
0
0.2
400
350
TURN OFF TIME (ns)
VS = ±5.0V
1000
800
600
VS = ±2.5V
0.8
1.0
1.2
1.4
1.6
1.8
–3
2.0
G = +1
RLOAD = 1kΩ
DISABLE = +VS TO –VS
VS = ±1.5V
300
VS = ±5.0V
VS = ±2.5V
250
200
400
150
VS = ±1.5V
200
0
–40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
100
–40
12611-033
TURN ON TIME (ns)
1400
1200
0.6
Figure 60. Output Overdrive Recovery
G = +1
RLOAD = 1kΩ
DISABLE = –VS TO +VS
1600
0.4
TIME (µs)
Figure 58. Input Overdrive Recovery
1800
2
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 59. Turn On Time vs. Temperature and Supply
Figure 61. Turn Off Time vs. Temperature and Supply
Rev. B | Page 23 of 33
125
12611-034
VOLTAGE (V)
1
3
VS = ±2.5V
G = +2
RLOAD = 1kΩ
VOUT
1.0
INPUT VOLTAGE (V)
2
VIN
OUTPUT VOLTAGE (V)
VIN
12611-044
3
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
THEORY OF OPERATION
The rail-to-rail input stage is useful in many different applications.
Although the precision is reduced from input to input, many
applications can tolerate this loss when the alternative is no
functionality at all. The positive rail input range is indispensable
for servo loops with a high-side input range
The ADA4807-1/ADA4807-2/ADA4807-4 have a rail-to-rail
input stage with an input range that goes 200 mV beyond either
rail. A PNP transistor input pair is active for a majority of the
input range, while an NPN transistor input pair is active for the
common-mode voltages within 1.3 V of the positive rail. The
ADA4807-1/ADA4807-2/ADA4807-4 are fabricated using the
Analog Devices, Inc., third generation, extra fast complementary
bipolar (XFCB) process resulting in exceptionally good distortion,
noise, slew rate, and settling characteristics for 1 mA devices.
Given traditional rail-to-rail input architecture performance, the
input 1/f noise is surprisingly low, and the current noise is only
0.7 pA/√Hz for a 3 nV/√Hz voltage noise. Typical high slew rate
devices suffer from increased current noise because of input pair
degeneration and higher input stage current. The ADA4807-1/
ADA4807-2/ADA4807-4 exceed current benchmark parameters
given the performance of the XFCB process.
The ADA4807-1/ADA4807-2/ADA4807-4 input operates 200 mV
beyond either rail. Internal protection circuitry prevents the output
from phase inverting when the input range is exceeded. When
the input exceeds a diode beyond either rail, internal electrostatic
discharge (ESD) protection diodes source or sink current through
the input.
I1
I2
Q51
Q42
Q47
DIFFERENTIAL
DRIVE
FROM
INPUT STAGE
Q38
Q68
Q20
C9
+
The multistage design of the ADA4807-1/ADA4807-2/
ADA4807-4 has excellent precision specifications, such as input
drift, offset, open-loop gain, CMRR, and PSRR. Typical harmonic
distortion numbers fall in the range of −130 dBc for a 10 kHz
fundamental (see the Distortion and Noise section). This level of
performance makes the ADA4807-1/ADA4807-2/ADA4807-4 the
best choices when driving 18-bit precision converters.
Q37
R29
Q27
Q21
Q48
VOUT
C5
+
Q43
Q49
I4
Q50
The ADA4807-1/ADA4807-2 are optimized for a low shutdown
current (4 μA maximum), in the order of a few microamperes. In
power sensitive applications, this can eliminate the use of a power
FET and enable time interleaved power saving operation schemes.
12611-052
I5
Q44
Figure 62. Differential Drive from Input Stage
+VS
R1
I2
Q9
R2
1.3V
Q3
Q2
Q8
Q5
VIP
Q13
OUTPUT STAGE,
COMMON-MODE
FEEDBACK
R3
–VS
VBIAS1
Q17
Q14
I1
5µA
Q7
Q18
Q4
Figure 63. Simplified Schematic
Rev. B | Page 24 of 33
Q11
VBIAS2
R4
12611-051
VIN
R5
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
DISABLE CIRCUITRY
When the DISABLE pin is an option, a pull-up resistor is required
if the logic leakage currents exceed 300 nA. For a 10 V supply,
pulling the DISABLE pin to below 6.3 V turns the ADA4807-1/
ADA4807-2 off, which reduces the supply current to 2.4 µA.
Conversely, pulling the DISABLE pin voltage to above 6.6 V
enables the ADA4807-1/ADA4807-2 with a quiescent current of
1 mA. When the ADA4807-1/ADA4807-2 device is disabled, its
output enters a high impedance state. Figure 64 and Table 10
show the DISABLE functionality over the complete supply range.
heating. If large differential voltages must be sustained across the
input terminals, it is recommended that the current through the
input clamps be limited to less than 10 mA. Series input resistors
sized appropriately for the expected differential overvoltage
provide the needed protection.
+VS
BIAS
ESD
ESD
+INx
–INx
ESD
ESD
4.0
–VS
3.6
3.4
NOTES
1. THE ±INx PINS ARE ±IN ON THE ADA4807-1,
±IN1 AND ±IN2 ON THE ADA4807-2,
AND ±IN1 TO ±IN4 ON THE ADA4807-4.
3.0
2.8
Figure 65. Input Stage and Protection Diodes
2.6
2.4
NOISE CONSIDERATIONS
2.2
Figure 66 illustrates the primary noise contributors for the typical
gain configurations. The total output noise (VN_OUT) is the root
sum square of all the noise contributions.
2.0
VTH
VON = VTH +150mV
VOFF = VTH –150mV
1.6
3
4
6
5
7
8
POWER SUPPLY, VS (V)
9
10
VN _ RG = 4kT × RG
Figure 64. DISABLE Trigger Voltage
+3 V
1.35 V
1.05 V
+5 V
1.6 V
1.3 V
+10 V
6.6 V
6.3 V
±5 V
1.6 V
1.3 V
VN _ R F = 4kT × RF
ven
RG
+ vout_en –
ien
Table 10. Threshold Voltages for Disabled and Enabled Modes
Mode
Enabled
Disabled
RF
+7 V/−2 V
3.6 V
3.3 V
The output impedance decreases as the frequency increases. When
disabled, a forward isolation of 120 dB is achieved at 100 kHz (see
Figure 22). ESD clamps protect the DISABLE pin, as shown in
Figure 65. Voltages beyond the power supplies cause these diodes
to conduct. To avoid excessive current in the ESD diodes, ensure
that the voltage to the DISABLE pin is not 0.7 V greater than the
positive supply or that it is not 0.7 V less than the negative supply.
If an overvoltage condition is expected, limit the input current to
less than 10 mA with a series resistor.
INPUT PROTECTION
The ADA4807-1/ADA4807-2/ADA4807-4 are fully protected
from ESD events, withstanding human body model ESD events
of ±3 kV and charged device model events of ±1.25 kV with no
measured performance degradation. The precision input is
protected with an ESD network between the power supplies and
diode clamps across the input device pair, as shown in Figure 65.
For differential voltages above approximately 1.2 V at room
temperature and 0.8 V at 125°C, the diode clamps begin to
conduct. Too much current can cause damage due to excessive
VN _ RS = 4kT × RS
RS
12611-055
1.8
1.4
12611-054
TO THE REST OF THE AMPLIFIER
3.2
12611-152
TRIGGER VOLTAGE BELOW +VS (V)
3.8
iep
Figure 66. Noise Sources in Typical Gain Configurations
Source resistance noise, amplifier input voltage noise, and the
voltage noise from the amplifier input current noise (IN+ × RS)
are all subject to the noise gain term (1 + RF/RG).
Calculate the output noise spectral density using the following
equation:
 R
VN _ OUT = 4kTRF + 1 + F
 RG
2
2

R 
 4kTRs + I N + 2 RS 2 + VN 2 +  F  4kTRG + I N − 2 RF 2

R 

 G
[
]
where:
k is Boltzmann’s constant.
T is the absolute temperature in degrees Kelvin.
RF and RG are the feedback network resistances, as shown in
Figure 66.
RS is the source resistance, as shown in Figure 66.
IN+ and IN− represent the amplifier input current noise spectral
density in pA/√Hz.
VN is the amplifier input voltage noise spectral density in nV/√Hz.
Rev. B | Page 25 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
APPLICATIONS INFORMATION
CAPACITIVE LOAD DRIVE
LOW NOISE FET OPERATIONAL AMPLIFIER
Figure 67 shows the schematic for driving large capacitive loads, and
Figure 68 shows the frequency response for a gain of +2. Note that
the bandwidth decreases with larger capacitive loads (see Figure 68).
Low noise amplifiers for photodiode, piezoelectric, and other
instrumentation applications typically call for circuit parameters
such as extremely high input impedance, low 1/f noise, or subpicoamp bias currents that can be met only with a discrete
amplifier design.
Figure 69 shows the required series resistor (RSERIES) when
limiting the peaking to 3 dB for a range of load capacitors
(CLOAD) at a gain of +2. From Figure 69, no series resistors are
necessary to maintain stability for larger capacitors.
RF
VIN
VOUT
RSERIES
VLOAD
CLOAD
RLOAD
RT
49.9Ω
12611-056
RG
Figure 67. Schematic for Driving Large Capacitive Loads
The unbalanced output impedance of the FETs is negated by
the use of an inverting amplifier cascode. The ADA4807-1/
ADA4807-2/ADA4807-4 are ideally suited for the cascode due
to their rail-to-rail input structure, which results in excellent
overload behavior of the overall discrete amplifier. Using this
cascode structure, the CMRR is greater than 100 dB.
3
15pF, 100Ω
–3
470pF, 20Ω
47pF, 82.5Ω
1nF, 10.5Ω
10nF, 1.69Ω
–6
100nF, 0.5Ω
–9
–12
–15
VS = ±5V
RLOAD = 1kΩ
G = +2
VOUT = 70mV p-p
–18
0.1
1
10
100
1000
FREQUENCY (MHz)
12611-155
NORMALIZED CLOSED-LOOP GAIN (dB)
6
0
The discrete amplifier shown in Figure 70 uses a high-speed op
amp preceded by a differential amplifier stage. This discrete configuration is implemented with dual matched JFETs, which provide
high input impedance and some initial gain, reducing the noise
and precision specifications of the second stage. The low current
consumption of the ADA4807-1/ADA4807-2/ADA4807-4, in
addition to their precision and low noise characteristics, results
in a composite design with 7 mA of total supply current,
1.5 nV/√Hz noise at 1 kHz, and 4 nV/√Hz noise at 10 Hz.
Figure 68. Frequency Response for Driving Large Capacitive Loads,
RF = RG = 249 Ω
A high output impedance current source is also needed to
maintain the CMRR of the discrete amplifier. An ADR510
maintains a precise current over the supply voltage, and the low
collector capacitance of the PMP4201 results in a balanced and
predictable slew rate behavior. This is shown in Figure 71 with a
0.4 V p-p input and a 4 V p-p output with a gain of 10. Figure 72
shows output referred total harmonic distortion plus noise
(THD + N) for a gain of 10.
100
90
80
RSERIES (Ω)
70
60
50
40
30
20
0
0.001
0.01
0.1
1
10
100
CLOAD (nF)
12611-057
10
Figure 69. Required Series Resistor (RSERIES) vs. Capacitive Load (CLOAD)
at 3 dB Peaking
Rev. B | Page 26 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
R0
100Ω
Rb
100Ω
VOS
TRIM
C0
20pF
R12
100Ω
R1
10Ω
R13
100Ω
VOS
TRIM
C7
27pF
–
+5V
VOUT
+
–5V
+5V
ADA4807-1/
ADA4807-2/
ADA4807-4
V–
+
R4
5kΩ
–
1/2 LSK489
C9
2pF
ADA4807-1/
ADA4807-2/
ADA4807-4
–5V
V+
1/2 LSK489
+5V
R2
100Ω
R3
1kΩ
R6
5kΩ
1/2 PMP4201
qn1
qn0
1/2 PMP4201
R7
200Ω
12611-068
ADR510
–5V
Figure 70. Low Noise FET Operational Amplifier Schematic
POWER MODE ADC DRIVER
One of the merits of a SAR ADC, such as the AD7980, is that its
power scales with the sampling rate. This power scaling makes
SAR ADCs very power efficient, especially when running at a
low sampling frequency. However, the ADC driver used with
the SAR ADC traditionally consumes constant power regardless
of the sampling frequency.
1
2
CH2 1V Ω
M100ns
A CH1
0V
12611-069
CH1 200mV
Figure 73 illustrates a method by which the quiescent power of
the ADC driver can be reduced by 95% while still maintaining
the input signal to the ADC. Both the ADA4807-1/ADA4807-2/
ADA4807-4 and the AD8603 are rail-to-rail input and output
(RRIO) amplifiers and can operate on a single 5 V analog supply.
Connecting the AD8603 in parallel with a sharing resistor allows
the ADA4807-1/ADA4807-2/ADA4807-4 to be powered down,
reducing the total supply current for the driver from 1 mA to
50 μA. The sampling frequency of the AD7980 can then be
reduced to match the power consumption of the AD8603. With
the ADA4807-1/ADA4807-2/ADA4807-4 powered on, the SNR
and THD are 84.1 dB and −100.3 dB for a 3 V p-p, 1 kHz input
and a 4.096 V reference. The SNR and THD degrade to 81.4 dB
and −77.3 dB for the same input signal in the low power mode
when only the AD8603 is on.
Figure 71. Pulse Response, G = 10, 4 V p-p Output
–60
–65
–70
DISTORTION (%)
–75
–80
–85
–90
–95
–100
–110
100
1k
10k
20k
FREQUENCY (Hz)
Figure 72. 8 V p-p Output, THD + N for G = 10, RLOAD = 600 Ω
12611-071
–105
One issue with this method is that the reference and reference
buffer power do not scale with the ADC or the driver. This
makes this configuration most useful in multichannel systems
where the reference can be reused across many inputs.
Alternately, the reference buffer can be scaled in the same
fashion as the input driver; however, the reference itself must
remain on in any of the modes.
Rev. B | Page 27 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
5V
5V
ADA4807-1/
ADA4807-2/
ADA4807-4
ADR4540
–
+
C2
0.1µF
C3
10µF
C4
0.1µF
LP MODE
5V
ADA4807-1/
ADA4807-2/
ADA4807-4
VIN
–
R10
22Ω
+
R11
49.9Ω
REF
IN+
AD7980
C1
2.7µF
IN–
GND
5V
–
12611-070
AD8603
+
Figure 73. Dual Power Mode ADC Driver
ADC DRIVING
The ADA4807-1/ADA4807-2/ADA4807-4 can be used in ADC
driving applications. Figure 74 is a simplified schematic of the
ADA4807-1/ADA4807-2/ADA4807-4 driving an 18-bit differential
ADC, the AD7982, in a fully differential signal chain. This configuration results in an effective number of bits (ENOB) of 15.7; results
are shown in Figure 75.
Figure 76 shows the ADA4807-1/ADA4807-2/ADA4807-4
configured to convert a single-ended to differential signal and
drive an 18-bit ADC. This configuration results in an ENOB of
15.3. The FFT is shown in Figure 77.
20Ω
VIN
2.7nF
ADA4807-1/
ADA4807-2/
ADA4807-4
ADA4807-1/
ADA4807-2/
ADA4807-4
20Ω
20Ω
REF
2
2.7nF
ADA4807-1/
ADA4807-2/
ADA4807-4
IN+
ADC
IN–
20Ω
VIN–
Figure 76. Schematic for Driving the AD7982 Differential Converter from a
Single-Ended Input Signal, +VS = +7 V, −VS = −1 V
2.7nF
0
12611-275
ADA4807-1/
ADA4807-2/
ADA4807-4
fs = 200kSPS
fIN = 1kHz
SNR = 96.6dB
THD = –111.5dB
SFDR = –112.3dB
SINAD = 96.5dB
–40
SNR = 94.5dB
THD = –110.3dB
SFDR = –111.1dB
SINAD = 94.4dB
–40
AMPLITUDE (dB)
0
–20
fs = 200kSPS
fIN = 1kHz
–20
Figure 74. Schematic for Driving the AD7982, +VS = +7 V, −VS = −1 V
–60
–60
–80
–100
–120
–80
–140
–100
–160
–120
–180
–140
0
2
4
6
8
10
12
FREQUENCY (kHz)
14
16
18
20
Figure 77. FFT for Driving a Single-Ended Input Signal into a Differential
Converter
–160
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
12611-075
AMPLITUDE (dB)
12611-276
2.7nF
–180
ADC
IN–
1kΩ
12611-077
VIN+
IN+
1kΩ
Figure 75. FFT for Driving a Differential Converter, −0.5 dBFS
Rev. B | Page 28 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
ADC DRIVING WITH DYNAMIC POWER SCALING
CONV
1
DISABLE
2
CH1 2V
CH2 2V
M1µs
A CH1
0
fs = 200kSPS
fIN = 1kHz
SNR = 94.7dB
THD = –107.11dB
SFDR = –108.8dB
SINAD = 94.4dB
CONV
AMPLITUDE (dB)
–40
DISABLE
2.56V
Figure 80. Dynamic Power Scaling Timing Diagram for Driving a SingleEnded Input Signal Chain into a Differential ADC (AD7982)
–20
1
12611-078
In power sensitive applications, the ADA4807-1/ADA4807-2
can be switched on prior to the ADC turning on. Figure 78
shows the timing diagram for dynamically power scaling the
ADA4807-1/ADA4807-2 with the AD7982 configuration shown in
Figure 79. The falling edge of the DISABLE signal must align
with the rising edge of the CONV signal of the ADC to obtain a
clean data acquisition. Figure 79 gives the FFT for driving a fully
differential signal chain with a 1.2 µs on time as shown in Figure 78.
With this method, the ADA4807-1/ADA4807-2 quiescent current
(per amplifier) is reduced from 2 mA to 0.25 mA. Figure 81 gives
the FFT for dynamically power scaling a single-ended input
signal chain into a differential ADC with a 4 µs on time as
shown in Figure 80. This configuration results in a quiescent
current reduction of 20%.
–60
–80
–100
–120
–140
2
CH2 2V
M1µs
A CH1
2.56V
–180
Figure 78. Dynamic Power Scaling Timing Diagram for Driving a Fully
Differential Signal Chain into a Differential ADC (AD7982)
0
fs = 200kSPS
fIN = 1kHz
–20
AMPLITUDE (dB)
–80
–100
–120
–140
2
4
6
8
10
12
FREQUENCY (kHz)
14
16
18
20
12611-079
–160
0
4
6
8
10
12
14
16
18
20
Figure 81. FFT for Driving a Single-Ended to Differential Converter Using
Dynamic Power Scaling, −0.5 dBFS, On Time of 4 µs, for the Schematic Shown in
Figure 76
–60
–180
2
FREQUENCY (kHz)
SNR = 96.7dB
THD = –110.9dB
SFDR = –111.8dB
SINAD = 96.6dB
–40
0
12611-080
CH1 2V
12611-278
–160
Figure 79. FFT for Driving a Differential Converter using Dynamic Power Scaling,
−0.5 dBFS, On Time of 1.2 µs, for the Schematic Shown in Figure 74
Rev. B | Page 29 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
LAYOUT, GROUNDING, AND BYPASSING
The ADA4807-1/ADA4807-2/ADA4807-4 are high speed
devices. Realizing their superior performance requires attention
to the details of high speed printed circuit board (PCB) design.
The first requirement is to use a multilayer PCB with solid ground
and power planes that cover as much of the board area as possible.
Bypass each power supply pin directly to a nearby ground plane,
as close to the device as possible. Use 0.1 µF high frequency
ceramic chip capacitors.
Provide low frequency bulk bypassing using 10 µF tantalum
capacitors from each supply to ground.
Stray transmission line capacitance in combination with
package parasitics can potentially form a resonant circuit at
high frequencies, resulting in excessive gain peaking or possible
oscillation. Signal routing must be short and direct to avoid such
parasitic effects. Provide symmetrical layout for complementary
signals to maximize balanced performance.
Use radio frequency transmission lines to connect the driver
and receiver to the amplifier.
Minimize stray capacitance at the input and output pins by
clearing the underlying ground and low impedance planes
near these pins.
If the driver and receiver are more than one-eighth of the
wavelength from the amplifier, minimize the signal trace
widths. This nontransmission line configuration requires
clearing of the underlying and adjacent ground and low
impedance planes near the signal lines.
Rev. B | Page 30 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
OUTLINE DIMENSIONS
2.20
2.00
1.80
6
5
4
1
2
3
2.40
2.10
1.80
0.65 BSC
1.30 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.10 MAX
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
0.46
0.36
0.26
0.22
0.08
072809-A
1.35
1.25
1.15
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 82. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
PIN 1
INDICATOR
3.00
2.80
2.60
0.95 BSC
1.90
BSC
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 83. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. B | Page 31 of 33
0.55
0.45
0.35
12-16-2008-A
1.30
1.15
0.90
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
3.20
3.00
2.80
3.20
3.00
2.80
8
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
0.80
0.55
0.40
0.23
0.09
6°
0°
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 84. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 85. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 32 of 33
02-05-2013-C
PIN 1 INDEX
AREA
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
0.30
0.19
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
Figure 86. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4807-1AKSZ-R2
ADA4807-1AKSZ-R7
ADA4807-1ARJZ-R2
ADA4807-1ARJZ-R7
ADA4807-2ACPZ-R2
ADA4807-2ACPZ-R7
ADA4807-2ARMZ
ADA4807-2ARMZ-R7
ADA4807-4ARUZ
ADA4807-4ARUZ-R7
ADA4807-1AKSZ-EBZ
ADA4807-1ARJZ-EBZ
ADA4807-2ACPZ-EBZ
ADA4807-2ARMZ-EBZ
ADA4807-4AURZ-EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board for 6-Lead SC70
Evaluation Board for 6-Lead SOT-23
Evaluation Board for 10-Lead LFCSP_WD
Evaluation Board for 8-Lead MSOP
Evaluation Board for 14-Lead TSSOP
Z = RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12611-0-9/15(B)
Rev. B | Page 33 of 33
Package
Option
KS-6
KS-6
RJ-6
RJ-6
CP-10-9
CP-10-9
RM-8
RM-8
RU-14
RU-14
Branding
H3J
H3J
H3J
H3J
H3S
H3S
H3S
H3S