ACTIVE-SEMI ACT8870 Advanced pmu for microcontrollers and solid state drive application Datasheet

ACT8870QJ-T
REV 0 23-DEC-2016
Advanced PMU for Microcontrollers and Solid State Drive Applications
BENEFITS and FEATURES

Wide input voltage range
o Vin = 2.8V to 5.5V

Complete integrated power solution
o One 4A DC/DC Step-Down (Buck)
Regulator
o Three 2.5A DC/DC Step-Down
(Buck) Regulators
o One 800mA LDO
o Two 200mA LDOs

Space Savings
o Fully integrated
o High Fsw =2.25MHz or 1.125MHz
o Integrated sequencing

Easy system level design
o Configurable sequencing
o Seamless sequencing with external
supplies

Buck 1 Bypass Mode for 3.3V system level
compliance

Highly configurable
o uP interface for status reporting
and controllability
o Programmable Reset and Power
Good GPIO’s
o Flexible Sequencing Options

GENERAL DESCRIPTION
The ACT8870 PMIC is an integrated ActivePMU power
management unit. It is designed to power a wide range
of processors, including Atmel’s SAMA5D2, FPGA’s,
peripherals, microcontrollers, and solid-state drive applications. It is highly flexible and can be reconfigured
via I2C for multiple applications without the need for
PCB changes. The low external component count and
high configurability significantly speeds time to market.
Examples of configurable options include output voltage,
startup time, slew rate, system level sequencing,
switching frequency, sleep modes, operating modes etc.
ACT8870 is programmed at the factory with default configuration. These settings can be optimized for a specific
design through the I2C interface. The ACT8870 comes
in several default configuration. Contact the factory for
specific default configurations.
The core of the device includes four DC/DC step down
converters using integrated power FETs, three lowdropout regulators (LDOs), and an optional load switch.
Each DC/DC regulator switches at 2.25MHz, requiring
only three small components for operation. The LDOs
only require small ceramic capacitors. All are highly
configurable via the I2C interface.
The ACT8870 PMIC is available in a 5 x 5 mm 40 pin
QFN package or a 3.2x4.2 mm 0.5mm 48 ball wafer
chip-scale package.
I2C Interface – 1MHz
APPLICATIONS
•
•
•
•
Microcontroller Applications
Solid-State Drives
FPGA
Video Processor
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Typical Application Diagram
ACT8870
MCU
BUCK1 (4.0A)
BUCK2 (2.5A)
BUCK3 (2.5A)
DC/DC
REGULATOR
BUCK4 (2.5A)
PG
LDO1 (800mA)
ENABLE
LDO2 (200mA)
LDO3 (200mA)
SCL
SDA
nRESET
IRQ
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FUNCTIONAL BLOCK DIAGRAM
VIN
Supply
ACT8870
VIN
MODE
Supply
VIN
GPIO
VIO_IN
IO Supply
FB_B1
Vref
VIO_IN
PWREN
VIO_IN
VIO_IN
SCK
VIO_IN
SDA
VIO_IN
IRQ
VIO_IN
nRESET_AUX1
VIO_IN
VIN_B1
nRESET_AUX2
VIO_IN
VIO_IN
1µF
SW_B1
FB_B1
Digital
Core
VIN_B2
FB_B2
Vref
Buck2
Controller
1µF
SW_B2
FB_B2
Supply
22µF
PGND_B2
PG
VIN_B3
EXT_PG
Power _Good
Supply
POK
EXT_EN
ENABLE
2x22µF
PGND_B 1
nRESET
VIO_IN
Buck1 and
Bypass
Controller
VIO_IN
Supply
VIO_IN
FB_B3
VIN_LDO23
Vref
Buck3
Controller
1µF
SW_B3
FB_B3
22µF
PGND_B3
Vref
OUT_LDO3
1µF
VIN_B4
Vref
FB_B4
OUT_LDO2
Vref
1µF
Supply
Supply
VIN_LDO1
Buck4
Controller
1µF
SW_B4
FB_B4
PGND_B4
Vref
OUT_LDO1
1µF
AGND
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3
22µF
ACT8870QJ-T
REV 0 23-DEC-2016
ORDERING INFORMATION
PART NUMBER
ACT8870QJ101-T
VOUT1
VOUT2
VOUT3
VOUT4
VLDO1
VLDO2
VLDO3
Device ID
0x7DFh
Package
Off
1.5V
1.25V
3.3V
3.3V
1.8V
2.5V
0x2Fh
5x5 40 pin
ACT 8870 QJxxx-T
Product Number
Package Code
Pin Count
Option Code
Tape and Reel
Note 1: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity required.
Note 2: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor
products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
Note 3: Package Code designator “Q” represents QFN
Note 4: Pin Count designator “J” represents 40 pins
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IRQ
1
PGND1
2
PGND1
3
POK
4
PGND2
SW_B2
5
VIN_B2
FB_B2
OUT_LDO1
VIN_LODO1
SW_B1
VIN_B1
VIN_B1
VIN
FB_B1
PG
GPIO
VIN_B4
SW_B4
37
36
35
34
31
33
32
SW_B1
39
38
TOP VIEW
40
PIN CONFIGURATION - QFN
30
MODE
29
FB_B4
28
PGND4
27
PGND3
26
SW_B3
25
VIN_B3
7
24
8
9
23
22
FB_B3
OUT_LDO3
10
21
ACT8870
VIN_LDO23
20
OUT_LDO2
EXT_PG
VIO_IN
18
19
13
14
15
SCL
nRESET
EXT_EN
12
nRESET_AUX1
SDA
AGND
PWREN
11
nRESET_AUX2
6
16
17
EXPOSED
PAD
QFN
Figure 1: Pin Configuration – Top View – QFN55-40
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PIN DESCRIPTIONS - QFN
PIN
NAME
1
IRQ
2,3
PGND1
4
POK
5
PGND2
DESCRIPTION
Interrupt IRQ Open Drain Output indicates a fault occurred.
Dedicated Power Ground for BUCK1 Regulator.
Power OK Open Drain Output, indicates Overvoltage or Undervoltage on VIN input supply.
Dedicated Power Ground for Buck 2 Regulator.
6
SW_B2
Switch Pin for BUCK2 Regulator.
7
VIN_B2
Dedicated VIN power input for BUCK2 Regulator.
8
FB_B2
9
OUT_LDO1
Output for LDO1 Regulator (Leave unconnected if LDO1 is not used and disabled).
Feedback for BUCK2 Regulator. Connect to the BUCK2 output.
10
VIN_LDO1
Dedicated VIN power input for LDO1 Regulator.
11
nRESET_AUX2
Auxiliary nRESET configurable, Open Drain Output (configurable as an input).
12
nRESET_AUX1
Auxiliary nRESET configurable. Open Drain Output (configurable as an input).
13
SCL
14
nRESET
15
SDA
16
AGND
I2C Clock Input.
nRESET Open Drain Output. This pin is configurable.
I2C Data Input and Output.
Analog Ground.
17
PWREN
Power Enable Digital Input. This pin is configurable.
18
EXT_EN
External Regulator Enable Push-Pull Digital Output.
19
EXT_PG
External Power Good Digital Input. This pin is configurable.
20
VIO_IN
21
OUT_LDO2
22
VIN_LDO23
Dedicated VIN power input for LDO2 and LDO3 Regulator.
23
OUT_LDO3
Output for LDO3 Regulator (Leave unconnected if LDO3 is not used and disabled).
Digital Input Reference Voltage Input. Connect a 0.1uF ceramic capacitor between VIN_IN and AGND
Output for LDO2 Regulator (Leave unconnected if LDO2 is not used and disabled).
24
FB_B3
Feedback for BUCK3 Regulator. Connect to the BUCK3 output.
25
VIN_B3
Dedicated VIN power input for BUCK3 Regulator.
26
SW_B3
Switch Pin for BUCK3 Regulator.
27
PGND3
Dedicated Power Ground for BUCK3 Regulator.
28
PGND4
Dedicated Power Ground for BUCK4 Regulator.
29
FB_B4
Feedback for BUCK4 Regulator. Connect to the BUCK4 output.
30
MODE
Configuration input pin. This pin is read at power up to configure BUCK1.
31
SW_B4
Switch Pin for BUCK4 Regulator.
32
VIN_B4
Dedicated VIN power input for BUCK4 Regulator.
33
GPIO
34
PG
35
FB_B1
36
VIN
37,38
VIN_B1
39,40
SW_B1
Exposed Pad
Configurable General purpose input/open drain output.
Power Good Output. This pin is configurable. Open Drain Output.
Feedback for BUCK1 Regulator. Connect to the BUCK1 output.
Analog Input supply monitored by POK thresholds.
Dedicated VIN power input for BUCK1 Regulator.
Switch pin for BUCK1 Regulator.
Tie to Ground Plane for best performance
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
All I/O and Power pins except PGND_B1, PGND_B2, PGND_B3, PGND_B4, GND
-0.3 to 6
V
Grounds: Any PGND referenced to GND
-0.3 to +0.3
V
SW_Bx to PGNDx
-0.3 to VIN_Bx + 1
V
FB_Bx to PGNDx
-0.3 to VIN_Bx +0.3
V
OUT_LDOx to PGNDx
-0.3 to VINx + 0.3
V
EXT_EN, nRESET_AUX1, nRESET_AUX2
-0.3 to VIO_IN + 0.3
V
Junction to Ambient Thermal Resistance, QFN (Note2)
26
°C/W
Junction to Ambient Thermal Resistance, WCSP (Note2)
31
°C/W
Operating Junction Temperature
-40 to 125
°C
Storage Temperature
-55 to 150
°C
Note1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.
Note2: Measured on Active-Semi Evaluation Kit
RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN, VIN_B1, VIN_B2, VIN_B3, VIN_B4, VIN_LDO1,
VIN_LDO23
2.8
5.5
V
VIO_IN
1.62
5.5
V
1.6
3.2
A
105
°C
Average lifetime operating current. QFN. (Note 1)
SW_B2,SW_B3,SW_B4
SW_B1
Operating Junction Temperature
-40
Note1: This temperature range is used for lifetime reliability testing.
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DIGITAL I/O ELECTRICAL CHARACTERISTICS
(VVIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
UNIT
PWREN, EXT_PG Input Low
VVIO_IN = 1.8V
PWREN, EXT_PG Input High
VVIO_IN = 1.8V
PWREN, EXT_PG Input Low
VVIO_IN = 3.3V
PWREN, EXT_PG Input High
VVIO_IN = 3.3V
POK, IRQ, nRESET, nRESET_AUX1,
nRESET_AUX2, GPIO, PG Leakage Current
Output = 5V
1
µA
POK, IRQ, nRESET, nRESET_AUX1,
nRESET_AUX2, GPIO, PG Output Low
IOL = 5mA
0.35
V
EXT_EN Output Low
IOL = 1mA
0.35
V
EXT_EN Output High
IOH = 1mA
MODE, GPIO Input Low
VAVIN = 3.3V
MODE, GPIO Input High
VAVIN = 3.3V
MODE, GPIO Input Low
VAVIN = 5.0V
MODE, GPIO Input High
VAVIN = 5.0V
1.25
V
1.0
2.3
V
1.0
2.3
3.5
µs
1.2
8
V
V
10
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V
V
1.5
VVIO_IN UVLO Threshold Falling
V
V
VVIO_IN0.35
PWREN, EXT_PG, MODE Deglitch Time
V
V
ACT8870QJ-T
REV 0 23-DEC-2016
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.8
5.5
V
VIN_LDO1 referenced to GND
2.4
5.5
V
VIN_LDO23 referenced to GND
2.8
5.5
V
Supply Inputs Voltage Range: VIN_B1 referenced
to PGND_B1
VIN_B2 referenced to PGND_B2
VIN_B3 referenced to PGND_B3
VIN_B4 referenced to PGND_B4
UVLO Threshold Falling (Note 1)
UVLO Hysteresis (Note 1)
VIN_LVL=0
2.6
2.7
2.8
V
VIN_LVL=1 UV_LVL=0
2.6
2.7
2.8
V
VIN_LVL=1 UV_LVL=1
3.7
3.8
3.9
V
VIN_LVL=0
50
100
150
mV
VIN_LVL=1 UV_LVL=0
50
100
150
mV
VIN_LVL=1 UV_LVL=1
200
300
400
mV
VIN_LVL = 0
3.6
3.7
3.8
V
VIN_LVL = 1
5.55
5.75
5.95
V
VIN_LVL = 0
50
100
150
mV
VIN_LVL = 1
100
150
200
mV
OV Threshold Rising (Note 1)
OV Hysteresis (Note 1)
All Regulators Disabled
60
µA
All Regulators Enabled but no load
300
µA
Operating Supply Current
Thermal Shutdown Temperature TSD_SHUTDWN
Temperature rising
150
Thermal Shutdown Hysteresis
180
20
Startup Delay after initial VIN
start of first regulator output assuming start
delay=100µsec minimum (Note 2)
SLEEP Mode exit delay after de-asserting PWREN
pin
Configuration dependent (Note 2)
Thermal Interrupt Threshold TSD_ALERT
165
Temperature rising. Typically 30 degrees lower
than TSD_SHUTDWN
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30
°C
°C
435
485
µs
38
50
µs
°C
135
ACT8870QJ-T
REV 0 23-DEC-2016
Thermal Interrupt Hysteresis
°C
15
POK UV Interrupt Threshold Falling (VIN_LVL=0)
(Note 3) (Note 4)
POK_UV_SET=00 (88% of 3.3V)
POK_UV_SET=01 (86% of 3.3V)
POK_UV_SET=10 (84% of 3.3V)
POK_UV_SET=11 (Disable)
2.80
2.74
2.67
N/A
2.90
2.84
2.77
N/A
3.00
2.94
2.87
N/A
V
POK UV Interrupt Threshold Falling (VIN_LVL=1)
(Note 3) (Note 4)
POK_UV_SET=00 (88% of 3.3V)
POK_UV_SET=01 (85% of 3.3V)
POK_UV_SET=10 (85% of 5.0V)
POK_UV_SET=11 (Disable)
2.80
2.70
4.08
N/A
2.90
2.80
4.25
N/A
3.00
2.90
4.42
N/A
V
POK OV Interrupt Threshold Rising (VIN_LVL=0)
(Note 3) (Note 4)
POK_OV_SET=00 (107% of 3.3V)
POK_OV_SET=01 (109% of 3.3V)
POK_OV_SET=10 (110% of 3.3V)
POK_OV_SET=11 (Disable)
3.43
3.50
3.53
N/A
3.53
3.60
3.63
N/A
3.63
3.70
3.73
N/A
V
POK OV Interrupt Threshold Rising (VIN_LVL=1,
POK_LVL = 0) (Note 3) (Note 4)
POK_OV_SET=00 (133% of 3.3V)
POK_OV_SET=01 (136% of 3.3V)
POK_OV_SET=10 (136% of 3.3V)
POK_OV_SET=11 (Disable)
4.23
4.33
4.33
N/A
4.40
4.50
4.50
N/A
4.57
4.67
4.67
N/A
V
POK OV Interrupt Threshold Rising
(VIN_LVL=1, POK_LVL = 1) (Note 3) (Note 4)
POK_OV_SET=00 (110% of 5.0V)
POK_OV_SET=01 (112% of 5.0V)
POK_OV_SET=10 (114% of 5.0V)
POK_OV_SET=11 (Disable)
5.33
5.43
5.53
N/A
5.50
5.60
5.70
N/A
5.67
5.77
5.87
N/A
V
POK Deglitch Time OV or UV
5
Note 1: All Under-voltage Lockout, Overvoltage measurements are referenced to the AVIN Input and GND Pins.
Note 2: This delay can be affected by programming sequence and startup delays.
Note 3: All POK Under-voltage and Overvoltage measurements are referenced to the VIN Input and GND Pins.
Note 4: There is no hysteresis on OV and UV threshold for the POK interrupt.
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10
µs
ACT8870QJ-T
REV 0 23-DEC-2016
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1)
(VIN_B1 = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Input Operating Voltage Range
MIN
TYP
MAX
UNIT
2.8
5.5
V
0.8
4.0
V
Output Voltage Range
Configurable in 12.5mV steps
Standby Supply Current, Low Power Mode Enabled
VOUT_B1 = 103%, Regulator Enabled, No
Load
Shutdown Current
Regulator Disabled
Output Voltage Accuracy – Default Voltage PWM Mode
VOUT_B1 = 3.3V, IOUT = 2A
-1%
Output Voltage Accuracy – Default Voltage PFM Mode
VOUT_B1 = 3.3V, IOUT = 1mA
-1%
Line Regulation
VOUT_B1 = 2.8V VIN_B1 = 3.3V to 5.5V,
PWM Regulation
0.02
%/V
Load Regulation
VOUT_B1 = 3.3V PWM Regulation
0.04
%/A
Power Good Threshold
VOUT_B1 Rising
Power Good Hysteresis
VOUT_B1 Falling
Overvoltage Fault Threshold
VOUT_B1 Rising
Overvoltage Fault Hysteresis
VOUT_B1 Falling
Switching Frequency
VOUT_B1 ≥ 20% of VNOM
45
92
µA
1
µA
VNOM
1%
V
VNOM
1%
V
93
94
3
107.5
110
%VNOM
%VNOM
112.5
3
%VNOM
%VNOM
1.075
1.125
1.180
MHz
300
500
2000
µs
Configurable
Soft-Start Period Tset
10% to 90% VNOM
High Side FET Peak Current Limit (Cycle-by-Cycle) ILIMSET
High Side FET Peak Current Limit (Cycle-byCycle)e Tolerance
High Side FET Peak Current Limit, IRQ Trigger
Level
High Side FET Peak Current Limit, Shutdown
Level
B1_ILIMSET=11
B1_ILIMSET=10
B1_ILIMSET=01
B1_ILIMSET=00
3.0
3.8
4.6
5.3
A
At default ILIMSET
-10
ILIMSET
+10
%
At other set points
-15
ILIMSET
+15
%
Below ILIMSET = 00, 01, 10
-30.0
-22.5
-15.0
%
Below ILIMSET = 11
-32.5
-22.5
-12.5
%
Above ILIMSET = 00, 01, 10
+15.0
+22.5
+30
%
Above ILIMSET = 11
+12.5
+22.5
+32.5
%
0.04
Ω
PMOS On-Resistance
ISW = -1A, VIN = 5.0V
0.025
NMOS On-Resistance
ISW = 1A, VIN = 5.0V
0.025
SW Leakage Current
VIN_B1 = 5.5V, VSW = 0 or 5.5V
Dynamic Voltage Scaling Rate
B1_SLEW=00 (not allowed)
B1_SLEW=01
B1_SLEW=10
B1_SLEW=11
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11
Ω
1
N/A
14.0
3.50
0.88
µA
mV/us
ACT8870QJ-T
REV 0 23-DEC-2016
Switching Rise / Fall Times
B1_DRVADJ=00 VIN_B1 = 5V
B1_DRVADJ=01
B1_DRVADJ=10
B1_DRVADJ=11
Discharge Resistance
Enabled when regulator disabled
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12
6.3/9.0
4.5/7.4
3.1/5.9
3.0/5.0
2.75
4.4
ns
8.75
Ω
ACT8870QJ-T
REV 0 23-DEC-2016
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1) –
BYPASS MODE
(VIN_B1 = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
2.7
3.3
3.7
V
0.025
0.04
Ω
3
4
A
Bypass Mode
Input Voltage for By-Pass Mode
PMOS On-Resistance
ISW = -1A, VIN = 3.3V
Max=125°C at TJunction
Internal PMOS Current Detection
Triggers Interrupt on IRQ Pin
2
Internal PMOS Current Detection
Deglitch Time
Internal PMOS Current Shutdown
10
Shuts down after deglitch time and stays off for Off Time
4.8
6.0
µs
7.2
A
Internal PMOS Current Shutdown
Deglitch Time
10
µs
Internal PMOS Current Shutdown Off
time
100
ms
Internal PMOS Softstart
Only used with 3.3V Input
5.94
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13
6.6
7.26
mV/us
ACT8870QJ-T
REV 0 23-DEC-2016
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK2-4)
(VIN_Bx = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Input Operating Voltage Range
Output Voltage Range
Configurable in 12.5mV steps
Maximum Output Current
MIN
TYP
MAX
UNIT
2.8
5.5
V
0.8
4
V
2
A
Standby Supply Current, Low Power
Mode Enabled
VOUT_Bx = 103%, Regulator Enabled, No load
35
Shutdown Current
VIN_Bx = 5.5V, Regulator Disabled
0.1
1
µA
µA
B2 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B2 =1.5V, IOUT = 1A
PWM Mode
-1%
VNOM
1%
V
B3 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B3 =1.25V, IOUT = 1A
PWM Mode
-1%
VNOM
1%
V
B4 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B4 =3.3V, IOUT = 1A
PWM Mode
-1%
VNOM
1%
V
B2 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B2 =1.5V, IOUT = 1A
PFM Mode
-1%
VNOM
1%
V
B3 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B3 =1.25V, IOUT = 1A
PFM Mode
-1%
VNOM
1%
V
B4 Voltage Accuracy – Default Voltage –
CMI101 VOUT_B4 =3.3V, IOUT = 1A
PFM Mode
-1%
VNOM
1%
V
Line Regulation
VOUT_Bx =1.8V VIN_Bx = 2.8V to 5.5V PWM Regulation
0.02
%/V
Load Regulation
VOUT_Bx = 1.8V PWM Regulation
0.04
%/A
Power Good Threshold
VOUT_B2 Rising
92
93
94
VOUT_B3 Rising
94
95
96
VOUT_B4 Rising
94
95
96
Power Good Hysteresis
VOUT_Bx Falling
Overvoltage Fault Threshold
VOUT_Bx Rising
Overvoltage Fault Hysteresis
VOUT_Bx Falling
Switching Frequency
VOUT_Bx ≥ 20% of VNOM
2.15
2.25
2.36
MHz
Soft-Start Period Tset
Configurable
10% to 90% VNOM
300
500
2000
µs
High Side FET Current Limit (Cycle-byCycle) ILIMSET
Bx_ILIMSET=11
Bx_ILIMSET=10
Bx_ILIMSET=01
Bx_ILIMSET=00
High Side FET Current Limit (Cycle-byCycle) Tolerance
High Side FET Peak Current Limit, IRQ
Trigger Level
High Side FET Peak Current Limit,
3
%VNOM
107.5
110
%VNOM
112.5
3
%VNOM
%VNOM
2.0
2.5
3.0
3.5
A
At default ILIMSET
-10
ILIMSET
+10
%
At other setpoints
-15
ILIMSET
+15
%
Below ILIMSET = 00, 01, 10
-27.5
-22.5
-17.5
%
Below ILIMSET = 11
-30.0
-22.5
-15.0
%
Above ILIMSET = 00, 01, 10
+15.0
+22.5
+30
%
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ACT8870QJ-T
REV 0 23-DEC-2016
Shutdown Level
Above ILIMSET = 11
PMOS On-Resistance
ISW = -500mA
0.08
Ω
NMOS On-Resistance
ISW = 500mA
0.05
Ω
SW Leakage Current
VVIN_BX = 5.5V, VSW = 0 or 5.5V
Dynamic Voltage Scaling Rate
Bx_SLEW=00
Bx_SLEW=01
Bx_SLEW=10
Bx_SLEW=11
Not
Allowed
14.0
3.50
0.88
mV/us
Switching Rise / Fall Times
Bx_DRVADJ=00 VIN_Bx = 5V
Bx_DRVADJ=01
Bx_DRVADJ=10
Bx_DRVADJ=11
6.3/9.0
4.5/7.4
3.1/5.9
3.0/5.0
ns
Discharge Resistance
Enabled when regulator disabled
+12.5
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+22.5
+32.5
1
6.25
9.40
20
%
µA
Ω
ACT8870QJ-T
REV 0 23-DEC-2016
LDO1 ELECTRICAL CHARACTERISTICS
(VIN_LDO1 = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
MIN
TYP
MAX
UNIT
2.4
5.5
V
4.0
V
Output Voltage Range–VSET
Configurable in 25mV steps
0.8
Output Current
VIN_LDO1 = 2.8V to 5.5V, LDO1_ILIM=11
0.75
A
Output Current
VIN_LDO1 = 2.4V to 2.8V, LDO1_ILIM=1x
0.4
A
Output Voltage Accuracy
VIN_LDO1 - VLDO1_OUT > 0.4V
-1
Line Regulation
VIN_LDO1 - VLDO1_OUT > 0.4V
VIN_LDO1 = 2.8V to 5.5V
ILDO1_OUT = 1mA
0.005
%/V
Load Regulation
ILDO1_OUT = 1mA to 750mA, LDO1_ILIM=11
0.15
%/A
Power Supply Rejection Ratio
Supply Current per Output
1
f = 1kHz, ILDO1_OUT = 20mA, VLDO1_OUT = 2.5V
54
f = 10kHz, ILDO1_OUT = 20mA, VLDO1_OUT = 2.5V
53
f = 2.25MHz, ILDO1_OUT = 20mA, VLDO1_OUT = 2.5V
44
Regulator Enabled No Load
25
42
Regulator Disabled
0
1
VLDO1_OUT = 1.8V Setting (10% to 90%)
LDO1 SS_RAMP=00
LDO1 SS_RAMP=01
LDO1 SS_RAMP=10
LDO1 SS_RAMP=11
Soft-Start Period
VSET
Not allowed
385
465
600
VLDO1_OUT = 3.3V Setting (10% to 90%)
LDO1 SS_RAMP=00
LDO1 SS_RAMP=01
LDO1 SS_RAMP=10
LDO1 SS_RAMP=11
Not allowed
450
525
660
VLDO1_OUT Rising
Power Good Hysteresis
VLDO1_OUT Falling
Overvoltage Fault Threshold
VLDO1_OUT Rising
Overvoltage Fault Hysteresis
VLDO1_OUT Falling
dB
92
93
µs
94
3
105
110
10
25
%VNOM
%VNOM
114
3
Discharge Resistance
µA
240
330
450
575
VLDO1_OUT = 2.5V Setting (10% to 90%)
LDO1 SS_RAMP=00
LDO1 SS_RAMP=01
LDO1 SS_RAMP=10
LDO1 SS_RAMP=11
Power Good Threshold
%
%VNOM
%VNOM
75
Ω
Dropout Voltage
ILDO1_OUT = 200mA
200
mV
Dropout Voltage
ILDO1_OUT = 400mA, LDO1_ILIM=1x
300
mV
Dropout Voltage
ILDO1_OUT = 750mA VIN_LDO1 > 2.8
LDO_ILIM=11
400
mV
Output Current Limit
LDO1_ILIM=00
LDO1_ILIM=01
LDO1_ILIM=10
LDO1_ILIM=11 (800mA min)
Startup Delay
Additional startup delay required before soft start ramp
LDO1_SS_RAMP=00
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16
-15%
350
500
630
1000
+15%
mA
31
44
65
µs
ACT8870QJ-T
REV 0 23-DEC-2016
LDO2 AND LDO3 ELECTRICAL CHARACTERISTICS
(VIN_LDO23 = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
MIN
MAX
UNIT
2.4
5.5
V
4.0
V
1
%
Output Voltage Range – VSET
Configurable in 25mV steps
0.8
Output Voltage Accuracy
VIN_LDO23 - VLDOx_OUT > 0.4V
-1
Line Regulation
VIN_LDO23 - VLDOx_OUT > 0.4V
VIN_LDO23 = 2.8V to 5.5V
ILDOx_OUT = 1mA
Load Regulation
Power Supply Rejection Ratio
TYP
VSET
0.007
%/V
ILDOx_OUT = 1mA to 100mA, LDOx_ILIM=1X
-1
%/A
f = 1kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V
56
f = 10kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V
45
f = 2.25MHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V
55
Supply Current per Output
Regulator Disabled
Supply Current per Output
Regulator Enabled, No load
15
VLDOx_OUT = 1.8V Setting (10% to 90%)
LDO23 SS_RAMP=00
LDO23 SS_RAMP=01
LDO23 SS_RAMP=10
LDO23 SS_RAMP=11
110
110
165
215
VLDOx_OUT = 2.5V Setting (10% to 90%)
LDO23 SS_RAMP=00
LDO23 SS_RAMP=01
LDO23 SS_RAMP=10
LDO23 SS_RAMP=11
145
145
175
215
VLDOx_OUT = 3.3V Setting (10% to 90%)
LDO23 SS_RAMP=00
LDO23 SS_RAMP=01
LDO23 SS_RAMP=10
LDO23 SS_RAMP=11
200
200
210
235
Soft-Start Period
Power Good Threshold
VLDOx_OUT Rising
Power Good Hysteresis
VLDOx_OUT Falling
Overvoltage Fault Threshold
VLDOx_OUT Rising
Overvoltage Fault Hysteresis
VLDOx_OUT Falling
0.02
91
93
dB
1
µA
µs
95
3
105
110
20
%VNOM
%VNOM
114
3
Discharge Resistance
µA
%VNOM
%VNOM
50
125
Ω
Dropout Voltage
ILDOx_OUT = 30mA
50
90
mV
Dropout Voltage
ILDOx_OUT = 50mA, LDOx_ILIM=01
90
150
mV
Dropout Voltage
ILDOx_OUT = 100mA, LDOx_ILIM=1x
180
310
mV
Dropout Voltage
ILDOx_OUT = 150mA VIN_LDO23 > 2.8
LDOx_ILIM=11
285
500
mV
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ACT8870QJ-T
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Output Current Limit
LDOx_ILIM=00
LDOx_ILIM=01
LDOx_ILIM=10
LDOx_ILIM=11
60
100
150
200
80
145
225
290
Startup Delay
Additional startup delay required before soft start ramp
LDOx_SS_RAMP=01
20
36
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18
mA
55
µs
ACT8870QJ-T
REV 0 23-DEC-2016
OVERALL SYSTEM TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Regulator Programmable Startup Delay
Timings between turn on events
ONDLY=000
ONDLY=001
ONDLY=010
ONDLY=011
ONDLY=100
ONDLY=101
ONDLY=110
ONDLY=111
32.6
101
196
291
386
481
576
671
34.5
106.5
206.5
306.5
406.5
506.5
606.5
706.5
51.5
127.5
132.5
337.5
442.5
547.5
652.5
757.5
µs
nRESET, nRESET_AUX2
Programmable Delay Range
Step Size = 114µs
199
996
µs
nRESET, nRESET_AUX2 Min Delay
Timing
Setting nRST_DLY=000
160
199
240
µs
nRESET, nRESET_AUX2 Max Delay
Timing
Setting nRST_DLY=111
920
996
1080
µs
nRESET_AUX1 Delay Timings
Programmable Delay Range
Step Size = 228µs
398
1991
µs
nRESET_AUX1 Min Delay Timing
Setting nRST_AUX1_DLY=000
360
398
435
µs
nRESET_AUX1 Max Delay Timing
Setting nRST_AUX1_DLY=111
1876
1991
2114
µs
AUX TIMER Delay Timing
Setting AUX_DLY=00
Setting AUX_DLY=01
Setting AUX_DLY=10
Setting AUX_DLY=11
3.7
7.7
15.7
31.7
4
8
16
32
4.3
8.3
16.3
32.3
ms
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ACT8870QJ-T
REV 0 23-DEC-2016
2
I C INTERFACE ELECTRICAL CHARACTERISTICS
(VIO_IN = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SCL, SDA Input Low
VIO_IN = 1.8V
SCL, SDA Input High
VIO_IN = 1.8V
SCL, SDA Input Low
VIO_IN = 3.3V
SCL, SDA Input High
VIO_IN = 3.3V
SDA Leakage Current
SDA=5V
1
µA
SDA Output Low
IOL = 5mA
0.35
V
1000
kHz
0.4
1.25
UNIT
V
V
1.0
2.3
V
V
SCL Clock Frequency, fSCL
0
SCL Low Period, tLOW
0.5
µs
SCL High Period, tHIGH
0.26
µs
SDA Data Setup Time, tSU
50
ns
0
ns
SDA Data Hold Time, tHD
(Note1)
Start Setup Time, tST
For Start Condition
260
ns
Stop Setup Time, tSP
For Stop Condition
260
ns
Capacitance on SCL or SDA Pin
SDA Fall Time SDA, Tof
Device requirement
Pulse Width of spikes must be suppressed
on SCL and SDA
0
10
pF
120
ns
50
ns
Note1: Comply to I2C timings for 1MHz operation - “Fast Mode Plus”.
Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering RESET, IDLE, OVUVFLT, and
THERMAL states to clear any transactions that may have been occurring when entering the above states.
Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.
Note4: Device Address is 7’h5A
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Stop
condition
Figure 2: I2C Data Transfer
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SYSTEM CONTROL INFORMATION
General
I2C Registers
The ACT8870 is a single-chip integrated power management solution designed to power many processors
such as the Atmel SAMA5D3. It integrates four highly
efficient buck regulators, three LDOs, and an integrated
load bypass switch. Its high integration and high switching frequency result in an extremely small footprint and
lost power solution. It contains a master controller that
manages startup sequencing, timing, voltages, slew
rates, sleep states, and fault conditions. I2C configurability allows system level changes without the need for
costly PCB changes. The built-in load bypass switch enables full sequencing configurability in 3.3V systems.
The ACT8870 contains an array of internal registers
contain the IC’s basic instructions for setting up the IC
configuration, output voltages, sequencing, fault
thresholds, fault masks, etc. These registers are what
give the IC its operating flexibility. The two types of
registers are described below.
Basic Volatile – These are R/W (Read and Write) and
RO (Read only). After the IC is powered, the user can
modify the R/W register values to change IC
functionality. Changes in functionality include things like
masking certain faults. The RO registers communicate
IC status such as fault conditions. Any changes to these
registers are lost when power is recycled. The default
values are fixed and cannot be changed by the factory
or the end user.
The ACT8870 master controller monitors all outputs and
reports faults via I2C and hardwired status signals.
Faults can masked and fault levels and responses are
configurable via I2C.
Many of the ACT8870 pins and functions are configurable. The IC’s default functionality is defined by the default CMI (Code Matrix Index), but much of this functionality can be changed via I2C. The first part of the
datasheet describes basic IC functionality and default
pin functions. The end of the datasheet provides the
configuration and functionality specific to each CMI version. Contact [email protected] for additional information about other configurations.
Basic Non-Volatile – These are R/W and RO. After the
IC is powered, the user can modify the R/W register
values to change IC functionality. Changes in
functionality include things like output voltage settings,
startup delay time, and current limit thresholds. Any
changes to these registers are lost when power is
recycled. The default values can be modified at the
factory to optimize IC functionality for specific
applications. Please consult [email protected] for
custom options and minimum order quantities.
I2C Serial Interface
To ensure compatibility with a wide range of systems,
the ACT8870 uses standard I2C commands. The
ACT8870 operates as a slave device, and is addressed
using a 7-bit slave address of 0x5Ah followed by an
eighth bit, which indicates whether the transaction is a
read-operation or a write-operation 1011010x. “x” is a 0
for write operation and 1 for a read operation. Use address 0xB4h for write operations and 0xB5h for read operations.
When modifying only certain bits within a register, take
care to not inadvertently change other bits.
Inadvertently changing register contents can lead to
unexpected device behavior.
There is no timeout function in the I2C packet processing state machine, however, any time the I2C state
machine receives a start bit command, it immediately
resets the packet processing, even if it is in the middle
of a valid packet.
RESET State
State Machine
The ACT8870 contains an internal state machine with
five internal states.
In the RESET, or “cold” state, the ACT8870 is waiting
for the input voltage on VIN to be within a valid range
defined by I2C bits POK_OV_SET and POK_UV_SET.
All regulators are off in RESET. nRESET, nRESET_AUX1, and nRESET_AUX2 are asserted low. All
volatile registers are reset to defaults and Non-Volatile
registers are reset to programmed defaults. The IC transitions from RESET to ACTIVE when the input voltage
enters the valid range. The IC transitions from any other
state to RESET if the input voltage drops below the
UVLO threshold voltage.
The ACT8870 holds the I2C state machine in reset during the RESET, Idle, OVUVFLT, and THERMAL states
to avoid a corruption of registers when the voltage regulators are out of spec.
I2C commands are communicated using the SCL and
SDA pins. SCL is the I2C serial clock input. SDA is the
data input and output. SDA is open drain and must have
a pullup resistor. Signals on these pins must meet timing
requirements in the Electrical Characteristics Table.
ACTIVE State
The ACTIVE state is the normal operating state when
the input voltage is within the allowable range, all outputs are turned on, and no faults are present. When entering the ACTIVE state from the RESET state, all regulators are powered on following their programmed
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ACT8870QJ-T
REV 0 23-DEC-2016
power up sequence. The regulators are not sequenced
when entering ACTIVE from SLEEP.
SLEEP State
The SLEEP state is a low power mode for the operating
system. Each output can be programmed to be on or off
in the SLEEP state. The outputs do not follow any sequencing when turning on or off as they enter or exit the
SLEEP state. They do turn on with their programmed
softstart time. Buck1/2/3/4 can be programmed to regulate to their VSET0 voltage, VSET1 voltage, or be
turned off in the SLEEP state. LDO1/2/3 can be programmed to regulate to their VSET0 voltage or can be
programmed to be turned off. Note that LDO1/2/3 do
not have a VSET1 voltage.
The IC can enter SLEEP via a hardware input pin or an
I2C command. The hardware input is typically the
PWREN pin, but this can be reconfigured to other pins.
To enable SLEEP via I2C, program the following:
Figure 3. State Machine
Set register 0x08h bit1 (PWR_DN_MODE) = 1
Sequencing
Set register 0x00h bit0 (PWRDN_EN) = 1
The ACT8870 provides the end user with extremely
versatile sequencing capability that can be optimized for
many different applications. Each of the seven outputs
has four basic sequencing parameters: input trigger,
turn-on delay, softstart time, and output voltage. Each of
these parameters is controlled via the ICs internal
registers. As an example, the ACT8870QJ101-T
sequencing and output voltages are optimized for the
Atmel SAMA5D3D3 processor. The specifics for this IC
as well as others are detailed at the end of the datasheet.
Contact [email protected] for custom sequencing
configurations. Refer to the Active-Semi Application
Note describing the Register Map for full details on I2C
functionality and programming ranges.
To enter SLEEP,
(SLP_ENTR) = 1.
program
register
0x01h
bit1
I2C is disabled in SLEEP mode, to the only way to exit
SLEEP mode is to toggle the PWREN pin.
THERMAL State
In the THERMAL state the chip has exceeded the thermal shutdown temperature. To protect the device, all
the regulators are shut down and all three nRESETx
pins are asserted low. This state can be disabled by setting register 0x0Ah bit4 (TSD_nMASK) = 0. Note that
thermal shutdown fault flag, TSD_SHUTDWN, still provides the thermal status even TSD_nMASK = 0.
Input trigger. The input trigger for a regulator is the
event that turns that regulator on. Each output can have
a separate input trigger. The input trigger can be the
internal power ok (POK) signal from one of the other
regulators, the internal VIN POK signal, or an external
signal applied to an input pin such as EXT_PG or GPIO.
This flexibility allows a wide range of sequencing
possibilities, including have some of the outputs be
sequenced with another external power supply or a
control signal from the host. As an example, if the LDO1
input trigger is Buck1, LDO1 will not turn on until Buck1
is in regulation. Input triggers are defined at the factory
and can only be changed with a custom CMI
configuration. The nRESETx, POK, PG, and EXT_EN
outputs can be connected to a power supply’s internal
POK signal and used to trigger external supplies in the
overall sequencing scheme.
OVUVFLT State
In the OVUVFLT state one of the regulators has exceed
an OV level at any time or UV level after the soft start
ramp has completed. All regulators shutdown and all
three nRESETx outputs are asserted low when the IC
enters OVUVFLT state. The OVUVFLT state is timed to
retry after 100ms and enter the ACTIVE state. If the OV
or UV condition still exists in the ACTIVE state the IC
returns back to the OVUVFLT state. The cycle continues until the OV or UV fault is removed or the input
power is removed. This state can be disabled by setting
the OV_nMASK or UV_nMASK non-volatile bits low.
The IC does not directly enter OVUVFLT in an overcurrent condition, but does enter this state due to the resulting UV condition.
Turn-on Delay. The turn-on delay is the time between
an input trigger going active and the output starting to
turn on. Each output’s turn-on delay is configured via its
I2C bit ONDLY. Turn-on delays can be changed after the
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IC is powered on, but they are volatile and reset to the
factory defaults when power is recycled.
Thermal Warning
Thermal Shutdown
Softstart Time. The softstart time is the time it takes an
output to ramp from 0V to its programmed voltage. Each
output’s softstart time is configured via its I2C bit
SS_RAMP. Softstart times can be changed after the IC
is powered on, but they are volatile and reset to the
factory defaults when power is recycled.
There are three types of I2C register bits associated with
each fault condition: fault flag bits, fault bits, and mask
bits. The fault flag bits display the real-time fault status.
Their status is valid regardless of whether or not that
fault is masked. The mask bits either block or allow the
fault to affect the fault bit. Each potential fault condition
can be masked via I2C if desired. Any unmasked fault
condition results in the fault bit going high, which asserts
the IRQ pin. IRQ is typically active low. The IRQ pin
only de-asserts after the fault condition is no longer
present and the corresponding fault bit is read via I2C.
Note that masked faults can still be read in the fault flag
bit. Refer to Active-Semi Application Note describing the
Register Map for full details on I2C functionality and
programming ranges.
Output Voltage. The output voltage is each regulator’s
desired voltage. Each buck’s output voltage is
programmed via its I2C bits Bx_VSET0 and Bx_VSET1.
The output regulates to Bx_VSET0 in ACTIVE mode.
They can be programmed to regulate to Bx_VSET1 in
DVS mode or SLEEP mode. Each output’s voltage can
be changed after the IC is powered on, but the new
setting is volatile and is reset to the factory defaults
when power is recycled. Output voltages can be
changed on the fly. If a large output voltage change is
required, it is best to make multiple smaller changes.
This prevents the IC from detecting an instantaneous
over or under voltage condition because the fault
threshold are immediately changed, but the output
takes time to respond.
Output Under/Over Voltage
The ACT8870 monitors the output voltages for under
voltage and over voltage conditions. If one output enters
an UV/OV fault condition, the IC shuts down all outputs
for 100ms and restarts with the programmed power up
sequence. If an output is in current limit, it is possible
that its voltage can drop below the UV threshold which
also shuts down all outputs. If that behavior is not
desired, mask the appropriate fault bit. Each output still
provides its real-time UV/OV fault status via its fault flag,
even if the fault is masked. Masking an OV/UV fault just
prevents the fault from being reported via the IRQ pin.
A UV/OV fault condition pulls the nRESETx pins low.
Note that nRESETx pins are configurable via CMI
settings.
Dynamic Voltage Scaling
On-the-fly dynamic voltage scaling (DVS) for the four
buck converters is available via the I2C interface. This
allows systems to save power by quickly adjusting the
microprocessor performance level when the workload
changes. Note that DVS is not a different operating
state. The IC operates in the ACTIVE state, but just
regulates the outputs to a different voltage. For fault free
operation, the user must ensure output load conditions
plus the current required to charge the output
capacitance during a DVS rising voltage condition does
not exceed the current limit setting of the regulator. As
with any power supply, changing an output voltage too
fast can require a current higher than the current limit
setting. The user must ensure that the voltage step,
slew rate, and load current conditions do not result in an
instantaneous loading that results in a current limit
condition.
Output Current Limit
The ACT8870 incorporates a three level overcurrent
protection scheme for the buck converters and a single
level scheme for the LDOs. For the buck converters, the
overcurrent current threshold refers to the peak switch
current. The first protection level is when a buck
converter’s peak switch current reaches 80% of the
Cycle-by-Cycle current limit threshold for greater than
16 switching cycles. Under this condition, the IC reports
the fault via the appropriate fault flag bit. If the fault is
unmasked, it asserts the IRQ pin. This may or may not
turn off that output or other outputs depending on the
specific CMI. The next level is when the current
increases to the Cycle-by-Cycle threshold. The buck
converter limits the peak switch current in each
switching cycle. This reduces the effective duty cycle
and causes the output voltage to drop, potentially
creating an undervoltage condition. When the
overcurrent condition results in an UV condition, and UV
is not masked, the IC turns off all supplies off for 100ms
and restarts. The third level is when the peak switch
current reaches 120% of the Cycle-by-Cycle current
Enter DVS by programming register 0x00h bit1
(DVS_EN) = 1 and then pulling the EXT_EN pin high.
Note that some CMI configurations may not require
DVS_EN = 1 and may use different input pins.
Fault Protection
The ACT8870 contains several levels of fault protection,
including the following:
Output Overvoltage
Output Undervoltage
Output Current Limit
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I 2C
limit threshold. This immediately shuts down the
regulator and waits 14ms before restarting.
bit DVS_EN = 0. When
power good input by setting
configured as a power good input, EXT_PG can be
used as an input to the nRESETx pins. EXT_PG polarity
is controlled by the EXT_PG_POL bit. EXT_PG is active
high when EXT_PG_POL = 0 and active low when
EXT_PG_POL = 1.
For LDOs, the overcurrent thresholds are set by each
LDO’s Output Current Limit setting. When the output
current reaches the Current Limit threshold, the LDO
limits the output current. This reduces the output
voltage, creating an undervoltage condition, causing all
supplies to turn off for 100ms before restarting.
Configure EXT_PG as a dynamic voltage scaling (DVS)
control input by setting I2C bit DVS_EN = 1. When
EXT_PG is de-asserted, all buck regulators regulate to
their VSET0 voltage. When EXT_PG is asserted, the
buck regulators regulate to their VSET1 voltage. Note
that EXT_PG input is only valid for DVS toggling when
the IC is in the ACTIVE state of operation. I2C bit
EXT_PG_POL has no effect in DVS Mode.
The overcurrent fault limits for each output are
adjustable via I2C. Overcurrent fault reporting can be
masked via I2C, but the overcurrent limits are always
active and will shut down the IC when exceeded.
Thermal Warning and Thermal Shutdown
EXT_PG is referenced to the VIO_IN pin, and is 5.5V
tolerant meaning that EXT_PG can go to 5.5V even if
VIO_IN is less than 5.5V. The EXT_PG input has a 10us
bidirectional filter to prevent noise from triggering
unwanted operation.
The ACT8870 monitors its internal die temperature and
reports a warning via IRQ when the temperature rises
above the Thermal Interrupt Threshold of typically 135
deg C. It reports a fault when the temperature rises
above the Thermal Shutdown Temperature of typically
165 deg C. A temperature fault shuts down all outputs
unless the fault is masked. Both the fault and the
warning can be masked via I2C. The temperature
warning and fault flags still provide real-time status even
if the faults are masked. Masking just prevents the faults
from being reported via the IRQ pin.
VIO_IN
VIO_IN is the input bias supply for the IC. Apply an input
voltage between 1.62V and 5.5V. Bypass to AGND with
a high quality, 1uF ceramic capacitor.
MODE
Pin Descriptions
Setting MODE = 0 configures Buck1 as a standard
integrated buck regulator. Setting MODE = 1 configures
Buck1 as an integrated bypass switch. In bypass mode,
the Buck1 P-ch power FET is used to sequence the
3.3V supply to the downstream load. This provides full
sequencing flexibility for 3.3V systems by allowing the
3.3V input to be used as the input supply for the other
regulators but still be sequenced in any order for the
downstream loads. Bypass mode is only valid for a 3.3V
input voltage. The MODE pin must be tied directly to
VIN or AGND. MODE is only sampled when VIN
reaches its UVLO threshold during power. Changing
MODE after power up has no effect on functionality. I2C
bit MODE_STAT shows the status of the MODE pin
when it was read at startup.
The ACT8870 input and output pins are configurable via
CMI configurations. The following descriptions are refer
to the most common pin functions. Refer to the CMI
Options section in the back of the datasheet for specific
pin functionality for each CMI.
PWREN
The PWREN pin controls the IC’s SLEEP state. When
I2C bit PWREN_MODE = 0, the PWREN pin moves the
IC between the SLEEP and ACTIVE states.
PWREN must be enabled via the PWRDN_EN I2C bit
after power up. PWREN is ignored if the PWRDN_EN
bit is low. The PWREN polarity is controlled by the
PWREN_POL I2C bit. PWREN is active low when
PWREN_POL is high, and active high when
PWREN_POL is low. The host processor can read the
PWREN status via I2C in the PWREN_STAT I2C bit.
GPIO
The GPIO pin can be configured as a digital input or an
open drain output. It has multiple uses, including a
sequencing input, sequencing output, status output, or
control input to toggle a supply’s output voltage. Set I2C
bit GPIO_OUT = 0 to configure GPIO as an input. When
using GPIO as an output, GPIO_OUT = 0 configures it
as an open drain output, and GPIO_OUT = 1 configures
it as a logic low output. When used as either an input
or an output, I2C bit GPIO_STAT always provides the
real-time status of the GPIO pin. GPIO_STAT = 0 when
GPIO pin is a logic 0. GPIO_STAT = 1 when GPIO pin
is a logic 1.
PWREN is referenced to the VIO_IN pin, and is 5.5V
tolerant meaning that PWREN can go to 5.5V even if
VIO_IN is less than 5.5V. PWREN has a 10us
bidirectional filter to prevent noise from triggering
unwanted operation.
EXT_PG
The EXT_PG pin is a dual purpose input. It functions as
either a power good input from an external supply or a
dynamic scaling control input. Configure EXT_PG as a
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IRQ
nRESET
The IRQ pin is an output that issues an interrupt to the
host CPU/Controller when an ACT8870 fault or warning
condition occurs.
nRESET issues the main reset to the CPU/controller.
nRESET is immediately asserted low when either the
VIN voltage is above or below the UV or OV thresholds
or any valid output supply voltage is below its Power
Good threshold. After startup, nRESET de-asserts after
a programmable delay time when VIN and all outputs
are above their respective UVLO thresholds. The
nRESET delay time is controlled by the I2C bits
nRST_DLY[2:0], which programs the delay between
200us and 1ms in 114us steps. nRESET is configurable,
so refer to the CMI Options section in the back of the
datasheet for its specific functionality for each CMI.
nRESET is an open drain output and is 5.5V tolerant
meaning that nRESET can be pulled up to 5.5V even if
VIO_IN is less than 5.5V.
IRQ is triggered by:
1. Die temperature exceeding Thermal Interrupt
Threshold of 135C.
2. Any buck regulator reaching peak current limit,
ILIMSET, for 16 cycles after softstart.
3. Any LDO regulator reaching current limit,
LDOx_ILIM, for more than 16us after softstart.
4. BUCK1 PMOS switch exceeding Current Detection
threshold 75% of ILIMSET when system is
configured in bypass mode.
EXT_EN
EXT_EN is used to control an external regulator or to
provide a control signal to other system components.
Depending on the MODE pin status, EXT_EN is either
an exact output of the ACT8870’s internal BUCK1
enable signal or an exact output of the bypass switch
enable signal. The I2C bit EXT_EN_POL controls the
EXT_EN polarity. EXT_EN is active high when
EXT_EN_POL is low and EXT_EN is active low when
EXT_EN_POL is high. EXT_EN is a push-pull CMOS
output using VIO_IN supply. Note that the EXT_EN
output is enabled and valid in all modes of operation.
EXT_EN is configurable, so refer to the CMI Options
section in the back of the datasheet for its specific
functionality for each CMI.
IRQ is masked by the I2C register 0x00h bit2
(IRQ_nMASK) by default to mask all IRQ conditions. To
enable IRQ functionality, set IRQ_nMASK = 1. IRQ is an
active-low open drain 5.5V compatible output.
POK
POK indicates that the voltage on the VIN pin is inside
the POK UV and OV Interrupt Thresholds. If the VIN
voltage is above or below these values, POK pulls low
to interrupt the host CPU/Controller. POK is masked by
the I2C bit POK_nMASK by default. To enable POK
functionality, set I2C bit POK_nMASK = 1. I2C bits
POK_OV and POK_UV provide real-time UV and OV
status, even when POK is masked. The POK UV and
OV threshold are configurable via the I2C bits
POK_UV_SET and POK_OV_SET.
PG signals the status of a regulator’s Power Good / UV
comparator. When the regulator is below the Power
Good threshold, the PG pin is pulled low. When above
the threshold, the PG pin is open drain. The PG
functionality is enabled by default, but can be disabled
by I2C. Disable PG for each regulator using the
regulator’s UV_FLTMSK bit. PG is configurable, so
refer to the back of the datasheet for its specific
functionality for each CMI. PG is an open drain output
and is 5V tolerant meaning that PG can be pulled up to
5.5V even if VIO_IN is less than 5.5V.
POK is an open drain output and is 5.5V tolerant
meaning that POK can be pulled up to 5.5V even if
VIO_IN is less than 5.5V.
nRESET_AUX1 and nRESET_AUX2
nRESET_AUX1 and nRESET_AUX2 pins can be used
to signal that the IC is in the SLEEP state or that the
input voltage is above or below the UV or OV threshold.
They can also be tied to one or a combination of the
power supply’s internal POK signal. These outputs are
immediately asserted low, but follow a programmed
delay when de-asserted. The nRESET_AUX1 delay
time is controlled by the I2C bits RST_AUX1_DLY[2:0],
which programs the delay between 400us and 2mS in
227us steps. The nRESET_AUX2 delay time is
controlled by the I2C bits RST_AUX2_DLY[2:0], which
programs the delay between 200us and 1ms in 114us
steps. These pins are open drain output and 5.5V
tolerant meaning that they can be pulled up to 5.5V
even if VIO_IN is less than 5.5V.
Step-down dc/dc Converters
General Description
The ACT8870 contains four fully integrated step-down
converters. Buck1 is a 4A output, while Buck2, Buck3,
and Buck4 are 2.5A outputs. All buck converters are
fixed frequency, current-mode controlled, synchronous
PWM converters that achieve peak efficiencies of up to
96.5%. The buck converters switch at 2.25MHz and are
internally compensated, requiring only three small
external components (Cin, Cout, and L) for operation.
They ship with default output voltages that can be
modified via the I2C interface for systems that require
advanced power management functions.
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Each buck converter has a dedicated input pin and
power ground pin. Each buck converter should have a
dedicated input capacitor that is optimally placed to
minimize the power routing loops for each buck
converter. Note that even though each buck converter
has separate inputs, all buck converter inputs must be
connected to the same voltage potential.
setting DISLPM = 1 disables LPM. Operating in LPM
saves power, while operating in forced PWM mode
gives better transient response. Each buck converter
output can be programmed between 2.8V and 5.5V with
the I2C register Bx_VSEL0[7:0].
Enable / Disable Control
When power is applied to the IC, all converters automatically turn on according to a pre-programmed sequence.
Once in normal operation (ACTIVE state), each converter can be independently disabled via I2C. Each CMI
version requires a different set of command to disable a
converter, so contact the factory for specific instructions
if needed. Each converter contains an optional integrated discharge resistor that actively discharges the
output capacitor when the regulator is disabled. The discharge function is enabled via the I2C bit Bx_DisPulldown.
Buck 1 is configurable as a bypass switch for systems
with a 3.3V bus voltage. The bypass switch provides full
sequencing capability by allowing the 3.3V bus to be
used as the input to the other supplies and still be
properly sequenced to the downstream load.
Tie MODE to AGND to configure Buck1 for a switching
power supply. Tie MODE to VIN to configure Buck1 as
a bypass switch. MODE is only sampled when VIN
reaches its UVLO threshold. Changing the MODE pin
after startup has no effect. When Buck1 is configured as
a power supply, EXT_EN is a direct output of the
ACT8870 Buck1 enable signal. When Buck1 is
configured as a bypass switch, EXT_EN is a direct
output of the bypass switch enable signal.
Soft-Start
The ACT8870 buck regulators are highly configurable
and can be quickly and easily reconfigured via I2C. This
allows them to support changes in hardware
requirements without the need for PCB changes.
Examples of I2C functionality are given below:
Each buck regulator contains a softstart circuit that limits the rate of change of the output voltage, minimizing
input inrush current and ensuring that the outputs power
up monotonically. This circuitry is effective any time the
regulator is enabled, as well as after responding to a
short circuit or other fault condition. Each regulator’s
softstart time is adjustable between 525us and 1650us
via its I2C bits SS_RAMP.
Real-time power good, OV, and current limit status
100% Duty Cycle Operation
On/Off control
The buck regulators are capable of operating at up to
100% duty cycle. During 100% duty cycle operation, the
high-side power MOSFETs are held on continuously,
providing a direct connection from the input to the output
(through the inductor), ensuring the lowest possible
dropout voltage in battery powered applications.
Softstart ramp
Dynamic Voltage Scaling
Slew rate control
Each buck converter supports Dynamic Voltage Scaling
(DVS). DVS allows the user to optimize the processor’s
energy to complete tasks by lowering the processor’s
operating frequency and input voltage when lower performance is acceptable. In normal operation, each output regulates to the voltage programmed in the I2C register Bx_VSET0. During DVS, each output regulates to
Bx_VSET1. The output transitions from Bx_VSET0 to
Bx_VSET1 at a rate determined by the output capacitance and the load current. The outputs transition between VSET1 and VSET0 by the rate determined by the
I2C bits SLEW.
Ability to mask individual faults
Dynamically change output voltage
Switching delay and phase control
Low power mode
Overcurrent thresholds
Refer to the Active-Semi Application Note describing the
Register Map for full details on I2C functionality and
programming ranges.
Operating Mode
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage
condition does not exceed the current limit setting of the
regulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the
The buck converters operate in fixed-frequency PWM
mode at medium to heavy loads. They transition to a
proprietary power-saving low power mode (LPM) at light
loads in order to save power. Each buck converter’s
LPM can be independently enabled or disabled via its
DISLPM I2C bit. Setting DISLPM = 0 enables LPM while
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voltage step, slew rate, and load current conditions do
not result in an instantaneous loading that results in a
current limit condition.
∗
Where Vout is the output voltage, Vin is the input voltage,
and FSW is the switching frequency.
Enter DVS by programming register 0x00h bit1
(DVS_EN) = 1 and then pulling the EXT_EN pin high.
Note that some CMI configurations may not require
DVS_EN = 1 and may use different input pins.
BUCK1 Bypass Switch
The ACT8870 provides a bypass mode for 3.3V
systems. This allows the 3.3V input voltage to power the
ACT8870 regulators and also be sequenced to the
downstream loads. In bypass mode, the Buck1 P-ch
FET acts as a switch and the N-ch FET is disabled. The
bypass switch turns on the 3.3V rail with the
programmed delay and softstart time.
Bx_VSET0 must be higher than Bx_VSET1.
PWR_GOOD, OV, and ILIM are automatically masked
during DVS transitions to avoid asserting nRESET.
Optimizing Noise
Each buck converter contains several features available
via I2C to further optimize functionality. The top P-ch
FET’s turn-on timing can be shifted 100ns from the master clock edge via the PHASE_DELAY I2C bit. It can also
be aligned to the rising or falling clock edge via the
PHASE I2C bit. The internal FET rise and fall times can
be optimized to minimize switching noise at the cost of
lower efficiency via the DRVADJ I2C bit.
In bypass mode, the ACT8870 I2C registers are
reconfigured to the following.
1. B1_PWR_GOOD register bit reconfigured to the
output of the Soft Start ramp. When soft start is
complete, this bit goes high to allow the sequencing
of
the
other
regulators
to
continue.
B1_PWR_GOOD no longer reports the Buck1
output voltage status. It stays high as long as the
bypass switch is enabled.
Overcurrent and Short Circuit Protection
Each buck converter provides overcurrent and short circuit protection. Overcurrent protection is achieved with
cycle-by-cycle current limiting. The peak current threshold is set by the Bx_ILIM I2C bits. If the peak current
reaches the programmed threshold for 16 consecutive
switching cycles, the IC asserts IRQ low. A short circuit
condition that results in the peak switch current being
122% of Bx_ILIMSET immediately shuts down all supplies, asserts IRQ low and restarts the system in 100ms.
If a buck converter reaches overcurrent or short circuit
protection, the status is reported in the ILIM_REG[x] I2C
registers. The contents of these registers are latched
until read via I2C. Overcurrent and short circuit conditions can be masked via the I2C bit Bx_ILIM_FLTMSK.
2. B1_ILIM bit is the output of the PMOS Current
Detection circuit. In an overcurrent condition,
B1_ILIM triggers an IRQ output and gets latched in
the ILIM_REG[0] if configured by the IRQ_nMASK.
The B1_ILIM can also be masked with the
B1_ILIM_FLTMSK register.
3. B1_UV register bit reconfigured to the output of the
PMOS Current Shutdown circuit. This is set to 6A
typical. If the bypass switch current exceeds 6A,
limits the current which triggers an under voltage
fault condition and moves the IC into the OVUVFLT
state. This immediately shuts down all regulators
including the bypass switch. The system restarts in
100mS, following the programmed startup
sequencing. This fault can be masked with I2C bit
UV_nMASK. This fault is latched in the UV_REG
I2C bit. Shutdown due to overcurrent can also be
masked via the I2C bit B1_PG_FLTMSK.
Compensation
The buck converters utilize current-mode control and a
proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating
range. No compensation design is required; simply follow a few simple guide lines described below when
choosing external components.
4. B1_OV is disabled. There is no overvoltage
detection circuitry on the output of the bypass
switch.
Minimum On-Time
Input Capacitor Selection
The ACT8870 minimum on-time is 120ns. If the calculated on-time is less than 120ns with 2.25MHz operation, then the user must configure the output to switch
at 1.125MHz. Setting I2C bits Bx_HalfFreq = 0 sets Fsw
= 2.25MHz. Setting Bx_HalfFreq = 1 sets Fsw =
1.125MHz. The following equation calculates the ontime.
Each regulator requires a high quality, low-ESR,
ceramic input capacitor. Note that even though each
buck converter has separate input pins, all input pins
must be connected to the same voltage potential. 10uF
capacitors are typically suitable, but this value can be
increased without limit. Smaller capacitor values can be
used with lighter output loads. Choose the input
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capacitor value to keep the input voltage ripple less than
50mV.
Vripple
Where ΔIL is the inductor ripple current, FSW is the
switching frequency, and COUT is the output capacitance
after taking DC bias into account.
∗ 1
∗
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
∗
Be sure to consider the capacitor’s DC bias effects and
maximum ripple current rating when using capacitors
smaller than 0805.
A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The output capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics are not recommended due to
their wide variation in capacitance over temperature and
voltage ranges.
A capacitor’s actual capacitance is strongly affected by
its DC bias characteristics. The input capacitor is
typically an X5R, X7R, or similar dielectric. Use of Y5U,
Z5U, or similar dielectrics is not recommended. Input
capacitor placement is critical for proper operation.
Each buck’s input capacitor must be placed as close to
the IC as possible. The traces from VIN_Bx to the
capacitor and from the capacitor to PGNDx should as
short and wide as possible.
LDO CONVERTERS
General Description
The ACT8870 contains three fully integrated low
dropout linear regulators (LDO). LDO1 is an 800mA
output, while LDO2 and LDO3 are 200mA outputs. The
LDOs are require only two small external components
(Cin, Cout) for operation. They ship with default output
voltages that can be modified via the I2C interface for
systems that require advanced power management
functions.
Inductor Selection
The Buck converters utilize current-mode control and a
proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. The ACT8870 is optimized for
operation with 1.0-1.5μH inductors. Choose an inductor
with a low DC-resistance, and avoid inductor saturation
by choosing inductors with DC ratings that exceed the
maximum output current by at least 30%. The following
equation calculates the inductor ripple current.
LDO1 has a dedicated input pin. LDO2 and LDO3 share
an input pin. The LDOs can operate from different input
voltages than the buck converters. LDO1 and LDO2/3
can operate from different input voltage from each other.
Enable / Disable Control
∆
1
∗
When power is applied to the IC, all LDOs automatically
turn on according to a pre-programmed sequence.
Once in normal operation (ACTIVE state), each converter can be independently disabled via I2C. Each CMI
version requires a different set of command to disable a
converter, so contact the factory for specific instructions
if needed. Each converter contains an optional integrated discharge resistor that actively discharges the
output capacitor when the regulator is disabled. Each
LDO’s discharge function is enabled via its I2C bit
DIS_PULLDOWN.
∗
Where VOUT is the output voltage, VIN is the input voltage,
FSW is the switching frequency, and L is the inductor
value.
Output Capacitor Selection
The ACT8870 is designed to use small, low ESR,
ceramic output capacitors. Buck1 typically requires a
44uF output capacitor while Buck2, Buck3, and Buck4
require a 22uF output capacitor each. In order to ensure
stability, the actual Buck1 capacitance should be
greater than 33uF while Buck2, Buck3, and Buck4
should be greater than 15uF. The output capacitance
can be increased to reduce output voltage ripple and
improve load transients if needed. Design for an output
ripple voltage less than 1% of the output voltage. The
following equation calculates the output voltage ripple
as a function of output capacitance.
VRIPPLE
Soft-Start
Each LDO contains a softstart circuit that limits the rate
of change of the output voltage, minimizing input inrush
current and ensuring that the outputs power up in a
monotonically. This circuitry is effective any time the
LDO is enabled, as well as after responding to a short
circuit or other fault condition. Each LDO’s softstart time
is adjustable via its I2C bits SS_RAMP between 525us
and 1000us.
∆
8∗
Overcurrent and Short Circuit Protection
∗
Each LDO provides overcurrent and short circuit protection. The overcurrent threshold is set by the LDOx_ILIM
I2C bits. In both an overload and a short circuit condition,
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the LDO limits the output current which causes the output voltage to drop. This can result in an undervoltage
fault in addition to the current limit fault. If an LDO
reaches current limit protection, the status is reported in
the ILIM_REG[x] I2C registers. The contents of these
registers are latched until read via I2C. When the current limiting results in a drop in output voltage that triggers an undervoltage condition, the IC shuts down all
power supplies, asserts IRQ low, and enters the
UVLOFLT state. The IC restarts in 100ms and starts up
with default sequencing. Overcurrent and short circuit
conditions can be masked via the I2C bit
LDOx_ILIM_FLTMSK.
sensitive analog signals near these high frequency,
high dV/dt traces.
3. Place the LDO input capacitors close to their input
pins. Connect their ground pins into the ground
plane that connects the IC’s exposed pad.
4. The input capacitor and output capacitor grounds
should be connected as close together as possible,
with short, direct, and wide traces.
5. Connect the PGNDx ground pins and the AGND
ground pin directly to the exposed pad under the IC.
The AGND ground plane should be routed
separately from the other ground planes and only
connect to the main ground plane under the IC at
the AGND pin.
Input Capacitor Selection
Each LDO requires a high quality, low-ESR, ceramic
input capacitor. A 1uF is typically suitable, but this value
can be increased without limit. The input capacitor is
should be a X5R, X7R, or similar dielectric.
6. Connect the VIO_IN input capacitor to the AGND
ground pin.
Output Capacitor Selection
7. Connect the VIN input capacitor to the AGND
ground pin.
Each LDO requires a high quality, low-ESR, ceramic
output capacitor. A 1uF is typically suitable, but this
value can be increased without limit. The input capacitor
is should be a X5R, X7R, or similar dielectric.
8. Remember that all open drain outputs need pullup
resistors.
PC board layout guidance
9. Connect the exposed pad directly the top layer
ground plane. Connect the top layer ground plane
to both internal ground planes and the PCB
backside ground plane with thermal vias. Provide
ground plane routing on multiple layers that allows
the IC’s heat to flow into the PCB and then spread
radially from the IC. Avoid cutting the ground planes
and adding vias that restrict the radial flow of heat.of
operating conditions, and are relatively insensitive
to layout considerations.
Proper parts placement and PCB layout are critical to
the operation of switching power supplies. Follow the
following layout guidelines when designing the
ACT8870 PCB. Refer to the Active-Semi ACT8870
Evaluation Kits for layout examples
1. Place the buck input capacitors as close as possible
to the IC. Connect the capacitors directly to the
corresponding VIN_Bx input pin and PGNDx power
ground pin. Avoid the use of vias if possible.
2. Minimize the switch node trace length between
each SW_Bx pin and the inductor. Avoid routing
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Typical Operating Characteristics
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Recommended External Components
The following components have been used with the ACT8870.
REFERENCE
DESCRIPTION
MANUFACTURER
Input Capacitor, Buck1
22uF, 6.3V, X5R
Samsung, CL10A226MQ8NRNC
Input Capacitor, Buck2/3/4
10uF, 10V, X5R
Samsung, CL10A106KP8NNNC
Input Capacitor, LDO1/2/3
1uF, 25V, X7R
Yageo, CC0603KRX7R8BB105
Output Capacitor, Buck1
2x22uF, 6.3V, X5R
Samsung, CL10A226MQ8NRNC
Output Capacitor, Buck2/3/4
22uF, 6.3V, X5R
Samsung, CL10A226MQ8NRNC
Output Capacitor, LDO1/2/3
1uF, 25V, X7R
Yageo, CC0603KRX7R8BB105
Inductor, Buck1
1uH, 10.8mohm
Coilcraft, XFL4020-102
Inductor, Buck2/3/4
1uH, 15mohm
Wurth, 74438356010
VIO_IN
100nF, 6.3V, X5R
Standard
VIN
1uF, 6,3V, X5R
Standard
CMI OPTIONS
This section provides the basic default configuration settings for each available ACT8870 CMI option. Refer to each
option’s application note for the comprehensive list of default settings
CMI 101
CMI 101 is optimized for Atmel SAMA5D2. Buck1 is not used in this application. Buck4 and LDO1 power the SAMA5D2
Group 2 power supply inputs. Buck2 and Buck3 power the Group 1 power supply inputs. LDO3 powers VDDFUSE
which is not part of Group 1 or Group 2. LDO2 provides 1.8V power for other parts of the system.
Sequencing
Rail
Active
Mode
Voltage
(V)
Sleep
Mode
Voltage
(V)
DVS
Voltage
(V)
DVS slew
rate (mV/us)
Nominal
Current (A)
Current
Limit
Setting(A)
Sequencing
Input
Trigger
Buck 1
OFF
N/A
OFF
N/A
N/A
N/A
N/A
Buck 2
1.5
N/A
1.35
3.12
0.1
2
Buck 3
1.25
N/A
1.25
3.12
0.1
Buck 4
3.3
N/A
3.3
3.12
LDO1
3.3
N/A
3.3
LDO2
1.8
N/A
LDO3
2.5
N/A
StartUp
Delay (us)
Soft-Start
(us)
LDO3_PG
200
500
2
BUCK2_PG
700
700
0.1
2
VIN_UVLO
300
700
NA
0.4
0.5
VIN_UVLO
100
613
1.8
NA
0.05
0.2
BUCK4 PG
300
150
2.5
NA
0.05
0.2
LDO2_PG
300
150
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ACT8870QJ-T
REV 0 23-DEC-2016
SLEEP Mode
SLEEP Mode is not available in CMI 101. Connect PWREN to AGND
DVS Mode
DVS mode does not require changing I2C bit DVS_EN. The IC can enter DVS mode regardless of the DVS_EN setting.
Drive EXT_PG to a logic L for normal operation. Drive EXT_PG to a logic H for DVS mode. Note that Buck3/4 cannot
enter DVS mode with this CMI code. Their VSET1 setting is not used.
POK Thresholds
POK_UV = 2.8V
POK_OV = 5.5V
PG
The PG pin is asserted high when Buck4 is in regulation.
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ACT8870QJ-T
REV 0 23-DEC-2016
nRESET
nRESET is asserted low when any output is out of regulation. The reset timing is 996us
nRESET_AUX1
nRESET_AUX1 is asserted low when Buck2 is out of regulation. The reset timing is 1764us
nRESET_AUX2
nRESET_AUX2 is asserted low when Buck4 is out of regulation. The reset timing is 996us
Default Mask Settings
nRESET
nRESET_AUX1
nRESET_AUX2
Masked
Masked
Masked
CMI 101 Default Mask Settings
VIN_OV
IRQ
POK
(POK_OV)
Unmasked
Masked
Masked
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Thermal
Shutdown
Unmasked
UV
OV
Unmasked
Unmasked
ACT8870QJ-T
REV 0 23-DEC-2016
PACKAGE OUTLINE AND DIMENSIONS QFN55-40
PIN# 1 DOT
BY MARKING
P I N# 1 I D
C0 .200
40L FCSLP
(5x5mm)
Top View
Bottom View
Side View
SYMBOL
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
A
0.800
0.900
0.031
0.035
A1
-
0.050
-
0.002
A3
0.203 REF
0.008 REF
D
4.950
5.050
0.195
0.199
E
4.950
5.050
0.195
0.199
D2
1.250
1.350
0.049
0.053
E2
1.050
1.150
0.041
0.045
b
0.150
0.250
0.006
0.010
e
L
0.400 BSC
0.350
0.450
0.016 BSC
0.014
0.018
Innovative PowerTM
ActiveSwitcherTM is a trademark of Active-Semi.
37
ACT8870QJ-T
REV 0 23-DEC-2016
REVISION HISTORY
REVISION
0
DATE
23DEC2016
DESCRIPTION
1. Initial Release.
Innovative PowerTM
ActiveSwitcherTM is a trademark of Active-Semi.
38