Samsung K4D551638D 256mbit gddr sdram Datasheet

256M GDDR SDRAM
K4D551638D-TC
256Mbit GDDR SDRAM
4M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.8
October 2003
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Revision History
Revision 1.8 (October 6, 2003)
• Added Lead free package part number in the data sheet.
Revision 1.7 (August 5, 2003)
• Added K4D551638D-TC45 in the spec
Revision 1.6 (July 21, 2003)
• Removed K4D551638D-TC30 from the spec
• Added K4D551638D-TC2A in the spec
Revision 1.5 (July 14, 2003)
• Added K4D551638D-TC30 in the spec
Revision 1.4 (June 16, 2003)
• Changed tRCDRD of K4D551638D-TC33/36 from 4tCK to 5tCK
• Changed tRCDWR of K4D551638D-TC33/36 from 2tCK to 3tCK
Revision 1.3 (April 11, 2003)
• Added K4D551638D-TC60 in the spec.
• Changed AC/DC parameters’ value of K4D551638D-TC50.
• Refresh cycle period of K4D551638D-TC50/60 is 8K/64ms.
Revision 1.1 (March 21, 2003)
• Changed VDD and VDDQ spec from 2.5V+5% to 2.6V+0.1V for all the frequency
Revision 1.0 (February 27, 2003)
• Changed the CAS Latency (CL) of K4D551638D-TC40 from 3 to 4
• Defined DC spec.
Revision 0.0 (January 16, 2003) - Target Spec
• Defined Target Specification
- 2 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.6V + 0.1V power supply for device operation
• 2 DQS’s ( 1DQS / Byte )
• 2.6V + 0.1V power supply for I/O interface
• Data I/O transactions on both edges of Data strobe
• SSTL_2 compatible inputs/outputs
• DLL aligns DQ and DQS transitions with Clock transition
• 4 banks operation
• Edge aligned data & data strobe output
• MRS cycle with address key programs
• Center aligned data & data strobe input
-. Read latency 3, 4 (clock)
• DM for write masking only
-. Burst length (2, 4 and 8)
• Auto & Self refresh
-. Burst type (sequential & interleave)
• 32ms refresh period (4K cycle) for -TC2A/33/36/40/45
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• 64ms refresh period (8K cycle) for -TC50/60
• 66pin TSOP-II
• Differential clock input
• Maximum clock frequency up to 350MHz
• No Wrtie-Interrupted by Read Function
• Maximum data rate up to 700Mbps/pin
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
K4D551638D-TC2A*
350MHz
700Mbps/pin
K4D551638D-TC33
300MHz
600Mbps/pin
K4D551638D-TC36
275MHz
550Mbps/pin
K4D551638D-TC40
250MHz
500Mbps/pin
K4D551638D-TC45
222MHz
444Mbps/pin
K4D551638D-TC50
200MHz
400Mbps/pin
K4D551638D-TC60*
166MHz
333Mbps/pin
Interface
Package
SSTL_2
66pin TSOP-II
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
3. K4D551638D-LC is the Lead free package part number
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank DDR SDRAM
The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by
16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
PIN CONFIGURATION (Top View)
VDD
1
66
VSS
DQ0
2
65
DQ15
VDDQ
3
64
VSSQ
DQ1
4
63
DQ14
DQ2
5
62
DQ13
VSSQ
6
61
VDDQ
DQ3
7
60
DQ12
DQ4
8
59
DQ11
VDDQ
9
58
VSSQ
DQ5
10
57
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VDDQ
DQ7
13
54
DQ8
NC
14
53
NC
VDDQ
15
52
VSSQ
LDQS
16
51
UDQS
NC
17
50
NC
VDD
18
49
VREF
NC
19
48
VSS
LDM
20
47
UDM
WE
21
46
CK
CAS
22
45
CK
RAS
23
44
CKE
CS
24
43
NC
NC
25
42
A12
BA0
26
41
A11
BA1
27
40
A9
AP/A10
28
39
A8
A0
29
38
A7
A1
30
37
A6
A2
31
36
A5
A3
32
35
A4
VDD
33
34
VSS
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
PIN DESCRIPTION
CK,CK
Differential Clock Input
BA0, BA1
Bank Select Address
CKE
Clock Enable
A0 ~A12
Address Input
CS
Chip Select
DQ0 ~ DQ15
Data Input/Output
RAS
Row Address Strobe
VDD
Power
CAS
Column Address Strobe
VSS
Ground
WE
Write Enable
VDDQ
Power for DQ’s
L(U)DQS
Data Strobe
VSSQ
Ground for DQ’s
L(U)DM
Data Mask
NC
No Connection
RFU
Reserved for Future Use
VREF
Reference voltage
- 4 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A12
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
LDQS,UDQS
LDM,UDM
DQ0 ~ DQ15
NC/RFU
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
BLOCK DIAGRAM (4Mbit x 16I/O x 4 Bank)
16
Intput Buffer
I/O Control
CK, CK
Data Input Register
Serial to parallel
Bank Select
LWE
LDMi
4Mx16
16
Output Buffer
4Mx16
32
2-bit prefetch
Sense AMP
Row Decoder
Refresh Counter
Row Buffer
ADDR
Address Register
CK,CK
4Mx16
x16
DQi
4Mx16
Column Decoder
Col. Buffer
LCBR
LRAS
Latency & Burst Length
Strobe
Gen.
Programming Register
DLL
LCKE
LRAS LCBR
Data Strobe
LWE
LCAS
LWCBR
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
- 6 -
LDM
UDM
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
FUNCTIONAL DESCRIPTION
• Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CK,CK
tRP
2 Clock min.
2 Clock min.
tRFC
tRP
tRFC
2 Clock min.
~
Command
precharge
ALL Banks
EMRS
MRS
DLL Reset
1st Auto
Refresh
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
Any
Command
200 Clock min.
Inputs must be
stable for 200us
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
- 7 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
BA1
BA0
RFU
0
A12
A11
A10
A9
RFU
DLL
A8
A8
A7
DLL
TM
A6
A5
A3
CAS Latency
A2
BT
A1
Address Bus
A0
Burst Length
Mode Register
Burst Type
Test Mode
DLL Reset
A4
A7
mode
A3
Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
0
Burst Length
CAS Latency
BA0
An ~ A0
A6
A5
A4
MRS
0
0
0
Reserved
1
EMRS
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
A1
A0
Sequential
Interleave
0
0
0
Reserve
Reserve
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Reserve
Reserve
Latency
0
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Burst Type
A2
1
Reserved
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Command
NOP
Precharge
All Banks
NOP
NOP
MRS
NOP
Any
Command
NOP
NOP
tMRD=2 tCK
tRP
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
BA1
BA0
RFU
1
BA0
A12
A11
A10
A9
A8
RFU
An ~ A0
0
MRS
1
EMRS
A7
A6
A5
A4
D.I.C
A6
0
A1
A3
RFU
Output Driver Impedence Control
1
Weak
A2
A1
A0
D.I.C
DLL
Address Bus
Extended
Mode Register
A0
DLL Enable
0
Enable
1
Disable
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
- 9 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
2.0
W
Short circuit current
IOS
50
mA
Voltage on any pin relative to Vss
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
Parameter
VDD
2.5
2.6
2.7
V
1,7,8
Output Supply voltage
VDDQ
2.5
2.6
2.7
V
1,7,8
Reference voltage
VREF
0.49*VDDQ
-
0.51*VDDQ
V
2
Vtt
VREF-0.04
VREF
VREF+0.04
V
3
Input logic high voltage
VIH(DC)
VREF+0.15
-
VDDQ+0.30
V
4
Input logic low voltage
VIL(DC)
-0.30
-
VREF-0.15
V
5
Output logic high voltage
VOH
Vtt+0.76
-
-
V
IOH=-15.2mA
Output logic low voltage
VOL
-
-
Vtt-0.76
V
IOL=+15.2mA
Input leakage current
IIL
-5
-
5
uA
6
Output leakage current
IOL
-5
-
5
uA
6
Termination voltage
Note : 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
7. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
8. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
- 10 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-2A
-33
-36
-40
-45
-50
-60
TBD
230
220
210
200
145
125
mA
4
3
mA
Operating Current
(One Bank Active)
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
Precharge Standby Current
in Power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
Precharge Standby Current
in Non Power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
TBD
100
90
80
70
30
25
mA
Active Standby Current
power-down mode
ICC3P
CKE ≤ VIL(max), tCC= tCC(min)
TBD
80
75
70
65
55
35
mA
Active Standby Current in
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
TBD
150
140
130
120
75
55
mA
Operating Current
( Burst Mode)
ICC4
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
Page Burst, All Banks activated.
TBD
450
430
410
390
250
200
mA
Refresh Current
ICC5
tRC ≥ tRFC(min)
TBD
390
380
370
360
200
Self Refresh Current
ICC6
CKE ≤ 0.2V
70
4
180
3
1
mA
2
mA
Note : 1. Measured with outputs open.
2. Refresh period is 32ms for -TC2A/33/36/40/45 (4K/32ms)
Refresh period is 64ms for -TC50/60 (8K/64ms)
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.6V+ 0.1V, VDDQ=2.6V+ 0.1V ,TA=0 to 65°C)
Symbol
Min
Typ
Max
Unit
Input High (Logic 1) Voltage; DQ
Parameter
VIH
VREF+0.35
-
-
V
Note
Input Low (Logic 0) Voltage; DQ
VIL
-
-
VREF-0.35
V
Clock Input Differential Voltage; CK and CK
VID
0.7
-
VDDQ+0.6
V
1
Clock Input Crossing Point Voltage; CK and CK
VIX
0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
3. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
4. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
- 11 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC OPERATING TEST CONDITIONS (VDD=2.6V±0.1V, TA= 0 to 65°C)
Parameter
Value
Unit
Input reference voltage for CK(for single ended)
0.50*VDDQ
V
CK and CK signal maximum peak swing
1.5
V
CK signal minimum slew rate
1.0
V/ns
VREF+0.35/VREF-0.35
V
VREF
V
Vtt
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Fig.1
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V.
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.6V, TA= 25°C, f=1MHz)
Symbol
Min
Max
Unit
Input capacitance( CK, CK )
Parameter
CIN1
1.0
5.0
pF
Input capacitance(A0~A12, BA0~BA1)
CIN2
1.0
4.0
pF
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ0~DQ15)
COUT
1.0
6.5
pF
Input capacitance(DM0 ~ DM3)
CIN4
1.0
6.5
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
CDC1
0.1 + 0.01
uF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
uF
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS
Parameter
CK cycle time
-2A
Min
Max
tCK
10
2.86
tCH
0.45
0.55
tCL
0.45
0.55
tDQSCK
-0.6
0.6
tAC
-0.6
0.6
tDQSQ
0.35
tRPRE
0.9
1.1
tRPST
0.4
0.6
tDQSS
0.85
1.15
tWPRES
0
tWPREH
0.35
tWPST
0.4
0.6
tDQSH
0.4
0.6
tDQSL
0.4
0.6
tIS
0.9
tIH
0.9
tDS
0.35
tDH
0.35
tCLmin
tHP
or
tCHmin
tHPtQH
0.35
Symbol
CL=3
CL=4
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
-33
Min
3.3
0.45
0.45
-0.6
-0.6
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP0.35
Max
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
0.6
0.6
0.6
-
-36
Min
3.6
0.45
0.45
-0.6
-0.6
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP0.4
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
0.6
0.6
0.6
-
-40
Min
4.0
0.45
0.45
-0.6
-0.6
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP0.4
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
0.6
0.6
0.6
-
-45
Min
4.5
0.45
0.45
-0.7
-0.7
0.9
0.4
0.8
0
0.3
0.4
0.45
0.45
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP0.45
Max
Unit
Note
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
0.6
0.55
0.55
-
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
-
ns
1
-
ns
1
Unit
Note
10
1
AC CHARACTERISTICS (I)
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge
@Normal Precharge
Last data in to Row precharge
@Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
Exit self refresh to read command
Symbol
tRC
tRFC
tRAS
tRCDRD
tRCDW
-2A
Min
15
17
10
5
-33
Max
100K
-
Min
15
17
10
5
-36
Max
100K
-
Min
15
17
10
5
-40
Max
100K
-
Min
13
15
9
4
-45
Max
100K
-
Min
12
14
8
4
Max
100K
-
tCK
tCK
tCK
tCK
3
-
3
-
3
-
2
-
2
-
tCK
tRP
tRRD
5
3
-
5
3
-
5
3
-
4
3
-
4
3
-
tCK
tCK
tWR
3
-
3
-
3
-
3
-
3
-
tCK
1
tWR_A
3
-
3
-
3
-
3
-
3
-
tCK
1
tCDLR
tCCD
tMRD
3
1
2
-
3
1
2
-
2
1
2
-
2
1
2
-
2
1
2
-
tCK
tCK
tCK
1
tDAL
8
-
8
-
8
-
7
-
7
-
tCK
tXSR
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
tCK
-
ns
-
us
Power down exit time
tPDEX
Refresh interval time
tREF
-
-
-
-
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 13 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS
Parameter
CK cycle time
Symbol
CL=3
CL=4
-50
-60
Min
12
14
8
4
2
4
2
Max
100K
-
Min
10
12
7
3
2
3
2
Max
100K
-
tWR
3
-
3
-
tCK
1
tWR_A
3
-
3
-
tCK
1
tCDLR
tCCD
tMRD
2
1
2
-
1
1
2
-
tCK
tCK
tCK
1
tDAL
7
-
6
-
tCK
200
1tCK+tIS
7.8
-
200
1tCK+tIS
7.8
-
tCK
ns
us
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
Clock half period
tHP
Data output hold time from DQS
tQH
10
0.55
0.55
0.55
0.65
0.4
1.1
0.6
1.28
0.6
-
Max
Note
-
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Max
Unit
Min
6.0
0.45
0.45
-0.6
-0.7
0.9
0.4
0.75
0
0.25
0.4
0.35
0.35
0.8
0.8
0.45
0.45
tCLmin
or
tCHmin
tHP-0.55
tCK
Min
5.0
0.45
0.45
-0.55
-0.65
0.9
0.4
0.72
0
0.25
0.4
0.35
0.35
0.6
0.6
0.4
0.4
tCLmin
or
tCHmin
tHP- 0.5
0.55
0.55
0.6
0.7
0.45
1.1
0.6
1.25
0.6
-
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
-
ns
1
-
ns
1
Unit
Note
12
1
AC CHARACTERISTICS (I)
Parameter
Symbol
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
RAS to CAS delay for Write
Row precharge time
Row active to Row active
Last data in to Row precharge @Normal Precharge
Last data in to Row precharge @Auto
Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery + Precharge
Exit self refresh to read command
Power down exit time
Refresh interval time
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRRD
tXSR
tPDEX
tREF
-50
-60
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 14 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming
the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
- 15 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
AC CHARACTERISTICS (II)
(Unit : Number of Clock)
K4D551638D-TC2A
Frequency
Cas Latency
350MHz ( 2.86ns )
4
300MHz ( 3.3ns )
4
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
4
222MHz ( 4.5ns )
4
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
15
15
15
13
12
12
10
tRFC
17
17
17
15
14
14
12
tRAS
10
10
10
9
8
8
7
tRCDRD tRCDWR
5
3
5
3
5
3
4
2
4
2
4
2
3
2
tRP
5
5
5
4
4
4
3
tRRD
3
3
3
3
3
3
3
tDAL
8
8
8
7
7
7
6
Unit
K4D551638D-TC33
Frequency
Cas Latency
300MHz ( 3.3ns )
4
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
4
222MHz ( 4.5ns )
4
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
15
15
13
12
12
10
tRFC
17
17
15
14
14
12
tRAS
10
10
9
8
8
7
tRCDRD tRCDWR
5
3
5
3
4
2
4
2
4
2
3
2
tRP
5
5
4
4
4
3
tRRD
3
3
3
3
3
3
tDAL
8
8
7
7
7
6
Unit
K4D551638D-TC36
Frequency
Cas Latency
275MHz ( 3.6ns )
4
250MHz ( 4.0ns )
4
222MHz ( 4.5ns )
4
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
15
13
12
12
10
tRFC
17
15
14
14
12
tRAS
10
9
8
8
7
tRCDRD tRCDWR
5
3
4
2
4
2
4
2
3
2
tRP
5
4
4
4
3
tRRD
3
3
3
3
3
tDAL
8
7
7
7
6
Unit
K4D551638D-TC40
Frequency
Cas Latency
250MHz ( 4.0ns )
4
222MHz ( 4.5ns )
4
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
13
12
12
10
tRFC
15
14
14
12
tRAS
9
8
8
7
tRCDRD tRCDWR
4
2
4
2
4
2
3
2
tRP
4
4
4
3
tRRD
3
3
3
3
tDAL
7
7
7
6
Unit
K4D551638D-TC45
Frequency
Cas Latency
222MHz ( 4.5ns )
4
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
12
12
10
tRFC
14
14
12
tRAS
8
8
7
tRCDRD tRCDWR
4
2
4
2
3
2
tRP
4
4
3
tRRD
3
3
3
tDAL
7
7
6
Unit
K4D551638D-TC50
Frequency
Cas Latency
200MHz ( 5.0ns )
3
166MHz ( 6.0ns )
3
tRC
12
10
tRFC
14
12
tRAS
8
7
tRCDRD tRCDWR
4
2
3
2
tRP
4
3
tRRD
3
3
tDAL
7
6
Unit
K4D551638D-TC60
Frequency
Cas Latency
166MHz ( 6.0ns )
3
tRC
10
tRFC
12
tRAS
7
tRCDRD tRCDWR
3
2
tRP
3
tRRD
3
tDAL
6
Unit
- 16 -
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
Simplified Timing @ BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CK, CK
BA[1:0] BAa
BAa
BAa
Ra
A10/AP Ra
ADDR
(A0~A9, Ra
A11,A12)
Ca
BAa
BAb
Ra
Rb
Ra
Rb
BAa
BAb
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3
DM
COMMAND
ACTIVEA
PRECH
WRITEA
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD
tRAS
tRP
tRC
Normal Write Burst
(@ BL=4)
tRRD
Multi Bank Interleaving Write Burst
(@ BL=4)
- 17 -
Rev 1.8 (Oct. 2003)
256M GDDR SDRAM
K4D551638D-TC
PACKAGE DIMENSIONS (66pin TSOP-II)
0.65TYP
0.65±0.08
0.30±0.08
(10×)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
- 18 -
(10.76)
0.075 MAX ]
(0.50)
0.45~0.75
(4×
)
1.20MAX
1.00±0.10
0.10 MAX
[
(R
0.2
5)
(0.71)
0.05 MIN
0.210±0.05
(10×)
5)
(R
0.
15
)
0.665±0.05
22.22±0.10
(R
0.1
0.125 +0.075
-0.035
0.
25
)
(0.80)
#33
(1.50)
(10×)
(R
(1.50)
(10×)
#1
11.76±0.20
(0.80)
#34
10.16±0.10
#66
(0.50)
Units : Millimeters
0.25TYP
0×~8×
Rev 1.8 (Oct. 2003)
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