ON NB2305AI1DTG 3.3 v zero delay clock buffer Datasheet

NB2305A
3.3 V Zero Delay
Clock Buffer
The NB2305A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks. It accepts one reference input and drives
out five low−skew clocks. It is available in a 8 pin package.
The −1H version of the NB2305A operates at up to 133 MHz, and
has higher drive than the −1 devices. All parts have on−chip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is on−chip
and is obtained from the CLKOUT pad.
Multiple NB2305A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2305A is available in two different configurations, as shown
in the ordering information table. The NB2305AI is the base part. The
NB2305AI1H is the high drive version of the −1 and its rise and fall
times are much faster than −1 part.
• 15 MHz to 133 MHz Operating Range, Compatible with CPU and
•
•
•
•
•
PCI Bus Frequencies
Zero Input − Output Propagation Delay
Multiple Low−Skew Outputs
Output−Output Skew Less than 250 ps
Device−Device Skew Less than 700 ps
One Input Drives 5 Outputs
Less than 200 ps Cycle−to−Cycle Jitter is Compatible with PentiumR
Based Systems
Accepts Spread Spectrum Clock at the Input
Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm
3.3 V Operation, Advanced 0.35 CMOS Technology
Guaranteed Across Commercial and Industrial Temperature Ranges
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 11
MARKING
DIAGRAMS*
8
8
XXXX
ALYW
G
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
XXX
YWW
AG
1
1
Features
•
•
•
•
•
•
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1
TSSOP−8
DT SUFFIX
CASE 948S
XXXX
A
L
Y
W
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
Publication Order Number:
NB2305A/D
NB2305A
PLL
REF
CLKOUT
REF
1
CLK2
2
CLK1
8
CLKOUT
7
CLK4
NB2305A
CLK2
CLK1
3
6
VDD
GND
4
5
CLK3
CLK3
CLK4
Figure 1. Block Diagram
Figure 2. Pin Configuration
Table 1. PIN DESCRIPTION
Pin #
Pin Name
Description
1
REF (Note1)
2
CLK2 (Note 2)
Buffered clock output.
3
CLK1 (Note 2)
Buffered clock output.
4
GND
5
CLK3 (Note 2)
6
VDD
7
CLK4 (Note 2)
8
CLKOUT (Note 2)
Input reference frequency, 5 V tolerant input.
Ground.
Buffered clock output.
3.3 V supply.
Buffered clock output.
Buffered clock output, internal feedback on this pin.
1. Weak pulldown.
2. Weak pulldown on all outputs.
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2
NB2305A
Table 2. MAXIMUM RATINGS
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.5
+7.0
V
DC Input Voltage (Except REF)
−0.5
VDD + 0.5
V
DC Input Voltage (REF)
−0.5
7.0
V
Storage Temperature
−65
+150
°C
Maximum Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
>2000
V
Static Discharge Voltage (per MIL−STD−883, Method 3015)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. RECOMMENDED OPERATING CONDITIONS FOR INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Min
Max
Unit
3.0
3.6
V
−40
0
85
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
7
pF
Industrial
Commercial
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ELECTRICAL CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage (Note 3)
VIH
Input HIGH Voltage (Note 3)
IIL
Input LOW Current
VIN = 0 V
50
A
IIH
Input HIGH Current
VIN = VDD
100
A
VOL
Output LOW Voltage
IOL = 8 mA (−1)
IOL = 12 mA (−1H)
0.4
V
VOH
Output HIGH Voltage
IOH = −8 mA (−1)
IOH = −12 mA (−1H)
IDD
Supply Current (Commercial Temp)
Unloaded outputs at 66.67 MHz,
Select inputs at VDD
34
mA
IDD
Supply Current (Industrial Temp)
Unloaded outputs at
50
34
19
mA
2.0
100 MHz
66.67 MHz
33 MHz
Select inputs at VDD or GND, at Room
Temp
V
2.4
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. REF input has a threshold voltage of VDD/2.
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NB2305A
Table 5. SWITCHING CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 4)
Parameter
Description
1/t1
Output Frequency
1/t1
Duty Cycle = (t2 / t1) * 100
t3
Test Conditions
Min
Typ
Max
Unit
100
133
MHz
60
55
%
30 pF load
10 pF load
15
15
(−1, −1H)
(−1H)
Measured at 1.4 V, FOUT = 66.67 MHz
< 50 MHz
40
45
Output Rise Time
(−1)
(−1H)
Measured between 0.8 V and 2.0 V
2.5
1.5
ns
t4
Output Fall Time
(−1)
(−1H)
Measured between 2.0 V and 0.8 V
2.5
1.5
ns
t5
Output−to−Output Skew
All outputs equally loaded
250
ps
t6
Delay, REF Rising Edge to CLKOUT
Rising Edge
Measured at VDD/2
0
±350
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the CLKOUT pins of
the device
0
700
ps
tJ
Cycle−to−Cycle Jitter
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF pin
1.0
ms
4. All parameters specified with loaded outputs.
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4
50
50
NB2305A
Zero Delay and Skew Control
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero−input−output
delay.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
SWITCHING WAVEFORMS
t1
t2
1.4 V
1.4 V
0.8 V
0.8 V
OUTPUT
t3
Figure 3. Duty Cycle Timing
3.3 V
2.0 V
2.0 V
1.4 V
0V
t4
Figure 4. All Outputs Rise/Fall Time
V DD
2
1.4 V
OUTPUT
INPUT
V DD
2
1.4 V
OUTPUT
OUTPUT
t5
t6
Figure 5. Output − Output Skew
Figure 6. Input − Output Propagation Delay
V DD
2
CLKOUT, Device 1
V DD
2
CLKOUT, Device 2
t7
Figure 7. Device − Device Skew
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5
NB2305A
TEST CIRCUITS
VDD
1 k
VDD
VDD
CLKOUT
OUTPUTS
0.1 F
GND
10 pF
1 k
VDD
0.1 F
OUTPUTS
0.1 F
CLOAD
VDD
0.1 F
GND
Figure 8. Test Circuit #1
GND
GND
Figure 9. Test Circuit #2
For parameter t8 (output slew rate) on −1H devices
ORDERING INFORMATION
Marking
Operating Range
Package
Shipping†
NB2305AI1DG
5I1
Industrial &
Commercial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2305AI1DR2G
5I1
Industrial &
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2305AI1HDG
5I1H
Industrial &
Commercial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2305AI1HDR2G
5I1H
Industrial &
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2305AI1DTG
5I1
Industrial &
Commercial
TSSOP−8
(Pb−Free)
100 Units / Rail
NB2305AI1DTR2G
5I1
Industrial &
Commercial
TSSOP−8
(Pb−Free)
2500 Tape & Reel
NB2305AI1HDTG
5IH
Industrial &
Commercial
TSSOP−8
(Pb−Free)
100 Units / Rail
NB2305AI1HDTR2G
5IH
Industrial &
Commercial
TSSOP−8
(Pb−Free)
2500 Tape & Reel
Device
Availability
Now
Now
Now
Now
Now
Now
Now
Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NB2305A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NB2305A
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S
ISSUE C
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
B
−U−
1
PIN 1
IDENT
S
T U
S
V
J J1
4
K1
K
A
−V−
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
5
L
0.20 (0.008) T U
M
DETAIL E
G
0.25 (0.010)
N
M
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
N
F
DETAIL E
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB2305A/D
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