® ® ADC-305 8-Bit, 20MHz CMOS A/D Converters FEATURES • • • • • • • 8-bit resolution, 20MHz min. sampling rate ±½LSB max. differential nonlinearity error 18MHz input signal bandwidth Subranging, S&H enclosed +5V single power, low 85mW max. dissipation CMOS compatible logic input 3-State TTL compatible output INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION DATEL's ADC-305 is an 8-bit, 20MHz sampling, CMOS, subranging (two-pass) A/D converter. It processes signals at speeds comparable to a full flash converter by using a subranging conversion technique with multiple comparator blocks, each containing a sample and hold amplifier. The ADC-305 features CMOS low power dissipation (60mW typical) and a wide 18MHz (–1dB) input signal bandwidth. The ADC-305-1 is packaged in 400 mil 24-pin DIP and the ADC-305-3 in 300 mil 24-pin SOP. Other features are CMOS compatible input logic, 3-state TTL compatible output logic, +5V single power operation, self bias mode and low cost. PIN 1 2 3 4 5 6 7 8 9 10 11 12 FUNCTION PIN OUTPUT ENABLE (OE) DGND BIT 8 (LSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) +DVS (+5V) CLOCK INPUT (A/D CLK) 24 23 22 21 20 19 18 17 16 15 14 13 FUNCTION DGND REF. BOTTOM (VRB) SELF BIAS 1 (VRBS) AGND AGND ANALOG INPUT (VIN) +AVS (+5V) REFERENCE TOP (VRT) SELF BIAS 2 (VRTS) +AVS (+5V) +AVS (+5V) +DVS (+5V) Both the ADC-305-1 and the ADC-305-3 have the same pin assignment. 24 DGND OUTPUT ENABLE 1 REFERENCE VOLTAGE DGND 2 23 VRB 22 VRBS BIT 8 (LSB) 3 BIT 7 4 BIT 6 5 LOWER DATA LATCHES LOWER ENCODER (4 BIT) B BLOCK COMPARATORS WITH S/H (4 BIT) BIT 4 7 BIT 2 9 UPPER DATA LATCHES BIT 1 (MSB) 10 LOWER ENCODER (4 BIT) A BLOCK COMPARATORS WITH S/H (4 BIT) UPPER ENCODER (4 BIT) UPPER COMPARATORS WITH S/H (4 BIT) 18 +AVS 17 VRT 16 VRTS 15 +AVS +DVS 11 A/D CLK 12 20 AGND 19 VIN BIT 5 6 BIT 3 8 21 AGND CLOCK GENERATOR 14 +AVS 13 +DVS Figure 1. Functional Block Diagram DATEL, Inc., Mansfield, MA 02048-1151 (USA) • Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • Email: [email protected] • Internet www.datel.com ® ® ADC-305 ABSOLUTE MAXIMUM RATINGS (TA = 25°C) PARAMETERS MIN MAX UNITS Power Supply Voltage (+AVS, +DVS) Analog Input Voltage (VIN) Reference Input Voltage (VRT, VRB) Digital Input Voltage (VIH, VIL) Digital Output Voltage (VOH, VOL) –0.5 –0.5 –0.5 –0.5 –0.5 +7 +AVS +0.5 +AVS +0.5 +DVS +0.5 +DVS +0.5 Volts Volts Volts Volts Volts MIN. TYP. MAX. UNITS — — +0.5 to +2.5 11 — — Volts pF VRT to VRB VRT VRB Offset Voltage VRT VRB Self Bias I ➀ ➁VRBS VRTS-VRBS Self Bias II ➀ ➂VRTS MAX. UNITS Power Supply (+AVS, +DVS) I A GND - D GND I Power Supply Current Power Dissipation +4.75 — — — +5.0 — 12 60 +5.25 100 17 85 Volts mV mA mW — — 12.5 18 — — kΩ MHz 230 4.5 +1.8 0 –10 0 +0.6 +1.96 +2.25 300 6.6 — — –35 +15 +0.64 +2.09 +2.39 450 8.7 +2.8 VRT –60 +45 +0.68 +2.21 +2.53 Ω mA Volts Volts mV mV Volts Volts Volts –40 to +85°C –55 to +150°C 24-pin Plastic DIP 24-pin Plastic SOP 2.0 grams 0.3 grams TECHNICAL NOTES 1. The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS and +DVS be powered from a single supply since a time lag between start up of separate supplies could induce latch up. Other external logic circuits must be powered from a separate digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together externally. Power supply grounds must be connected at one point to the ground plane directly beneath the device. Digital returns should not flow through analog grounds. REFERENCE INPUTS Ref. Resitance Ref. Current Ref. Voltage ➀ TYP. Operating Temp. Range Storage Temp. Range Package Type ADC-305-1 ADC-305-3 Weight ADC-305-1 ADC-305-3 (Specification are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS = +5v, fS = 20MHz sampling unless otherwise specified.) Input Voltage Range (VIN) ➀ Input Capacitance (VIN = 1.5Vdc+0.07VRMS) Input Impedance Input Signal Bandwidth (VIN-2Vp-p, –1dB) MIN. PHYSICAL/ENVIRONMENTAL FUNCTIONAL SPECIFICATIONS ANALOG INPUTS POWER REQUIREMENTS DIGITAL INPUTS 2. Bypass all power lines to ground with a 0.1µF ceramic chip capacitor in parallel with a 47µF electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible. Input Voltage (CMOS) Logic Levels (VIH) "1" Logic Level (VIL) "0" Input Current (@VIH=+DVS)"1" (@VIL=0) "0" Clock Pulse Width TPW1 (A/D CLK) TPW0 3. Even though the analog input capacitance is a low 15pF, it is recommended that high frequency input be provided via a high speed buffer amplifier. A parasitic oscillation may be generated when a high speed amplifier is used. A 75 ohm resister inserted between the output of an amplifier and the analog input of the ADC-305 will improve the situation. A resistor larger than 100 ohms may degrade linearity. +4 — — — 25 25 — — — — — — — +1 5 5 — — Volts Volts µA µA ns ns 4. The input voltage range is determined by voltages applied to VRB (Reference Bottom) and VRT (Reference Top). Keep to the following equations; DIGITAL OUTPUTS Output Data Output Voltage Output Current ➃ Logic Level "1" Logic Level "0" Output Current ➄ Logic Level "1" Logic Level "0" Output Data Delay, Td 8-bit Binary Parallel 3-State TTL compatible — — 18 16 16 30 µA µA ns 8 20 — — — — — — — — — — 4 30 ±0.3 +0.5 1 0.5 — — 0.5 — — ±0.5 +1.3 — — Bit MHz MHz ns ps LSB LSB % deg The analog input range is normally 2Vp-p. Self Bias Mode a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is +0.64V to +2.73V nominal. PERFORMANCE Resolution Maximum Sampling Rate Minimum Sampling Rate Aperature Delay, TA Aperature Jitter Differential Linearity Error Integral Linearity Error Differential Gain Error ➅ Differential Phase Error ➅ Table 1. Digital Output Coding OV Zero +0.9922V +1.000V +1/2FS –1LSB +1/2FS 127 128 7F 80 0111 1000 1111 0000 0 00 0000 0000 ➔ ➔ ➔ +1.9922V 2 DATA BITS OUT MSB LSB CODE ➔ ➃ OE=OV, VOH=+DVS–0.5V, VOL=+0.4V ➄ OE=+DVS, VOH=+DVS, VOL=0V ➅ NTSC 40IRE mode ramp, 14.3MHz sampling STEP DEC HEX VIN ➔ Footnotes: ➀ See Technical Note 4 ➁ Short VRB (pin 23) to VRBS (pin 22). Short VRT (pin 17) to VRTS (pin 16). ➂ Short VRB (pin 23) to A GND. Short VRT (pin 17) to VRTS (pin 16). b. Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to +2.39V in this case. ➔ — — — 0V≤V RB≤V RT≤2.8V 1.8V≤V RT–VRB≤2.8V ➔ mA mA ➔ — — ➔ — — ➔ –1.1 +3.7 +FS 255 FF 1111 1111 ® ® ADC-305 These values may differ from one device to another. Voltage changes on the +5V supply have a direct influence on the performance of the device. The use of external references is recommended for applications sensitive to gain error. longer TPW1 will improve linearity of the system for higher frequency input signals. 7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to +5V. It is recommended that the data outputs be latched and buffered through output registers. External Reference Mode Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference resistance between VRB and VRT is about 300 ohms. It is important to make the output impedance of the reference source small enough while, at the same time, keeping sufficient drive capacity. Insert a 0.1µF bypass ceramic chip capacitor between VRT and GND to minimize the effect of the 20MHz clock running nearby. See Figure 5. 8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the result of the (N-3) conversion can be obtained. Data is stored firmly in an output register, such as an 74LS574, using the rising edge of a start convert pulse as a trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2 and 4. 5. Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is recommended to pull up to +5V if the device is driven with TTL. 9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device at sampling rates slower than 500kHz because the droop characteristics of the internal sample and holds will then exceed the limit required to maintain the specified accuracy of the device. 6. The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are 25ns minimum. A slightly Ta ANALOG INPUT N TPW1 N+1 N+2 TPW0 N+3 N+4 N N+1 CLOCK DATA OUTPUT N-3 N-2 N-1 Td= 30ns max. Figure 2. Timing Diagram +DVS +AVS +DVS OE VIN 19 A/D CLK +DGND DGND Digital Output Circuit, Bit1 through Bit 8 AGND Equivalent Circuit for OE and A/D CLK OE - Low data is output when high digital output pins turn to high impedance. Analog Input +AVS +AVS VRT VRB 17 23 VRBS AGND 22 AGND Voltage Reference (VRT,VRB) Equivalent Circuit Generates +0.6V when shorted with VB Figure 3. Equivalent Circuits 3 VRTS 16 Generates +2.6V when shorted with VT ® ® ® ® ADC-305 N+3 N+2 ANALOG INPUT (VIN) N+1 N A/D CLK UPPER SAMPLING COMPARATOR BLOCK S(N) UPPER OUTPUT DATA C(N) MD(N-1) LOWER REFERENCE VOLTAGE S(1) OUTPUT DATA S(N+2) C(N-1) S(N+3) C(1) S(3) RV(N+2) H(3) C(3) LD(N) S(N+1) H(N+1) LD(N-3) C(N+1) S(N+3) LD(N-1) N-3 C(N+3) MD(N+2) RV(N+1) LD(N-2) H(0-1) C(N+2) MD(N+1) RV(N) H(1) LOWER DATA A LOWER OUTPUT DATA B C(N+1) MD(N) RV(N-1) LOWER SAMPLING COMPARATOR A BLOCK LOWER SAMPLING COMPARATOR B BLOCK S(N+1) N-2 Figure 4. Timing Chart 4 H(N+3) LD(N+1) N-1 N ® ® ADC-305 +5V(A) +5V(D) 47µF 47µF 100µH Bias Adjust 0.1µF 0.1µF 0.1µF 13 14 11 1 20 0.1µF 15 10 2 19 0.1µF 16 9 3 18 17 8 4 17 18 7 5 16 6 6 20 5 7 14 21 4 8 13 22 3 9 12 23 2 10 11 24 1 VIN (RIN = 75 Ω) 470µF 390 100 Gain Adjust 2SC2785 2SC2785 22µF 120 0.1µF 2.2k 51 75 10k 2SC2785 0.1µF 680 2.2k –5V(A) +5V(A) 0.1µF 19 ADC-305 0.1µF 2SC2785 2k 74LS574 BIT 1 (MSB) BIT 2 BIT 3 BIT 4 15 BIT 5 BIT 6 BIT 7 BIT 8 (LSB) 0.1µF VRT Adjust 510 VRB Adjust 0.1µF 12 2SC2785 2k 1 14 2 13 3 4 510 11 74HC04 510 9 6 7 47µF –5V(A) Clock Input (A/D CLK) (RIN = 75Ω) 75 Figure 5. Typical Connection Diagram LSB 20 0.6 +DVS=+AVS=+5V VIN = 1kHz Ta=25°C 15 Supply Current Supply Current 20 15 10 SNR + THD vs. Input Signal Frequency dB +DVS=+AVS=+5V FS = 20.48MHz Ta=25°C 46 SNR + THD mA Diff. Linearity Error mA Differential Linearity Error vs. Input Signal Frequency Supply Current vs. Sampling Voltage Supply Current vs. Sampling Rate 0.4 42 +DVS=+AVS=+5V FS = 20.48MHz Ta=25°C 38 0.2 5 10 36 5 10 15 20 25 30MHz Sampling Rate 4.0 4.5 5.0 5.5V Supply Voltage 2 4 6 8 Input Signal Frequency Figure 6. Typical Performance Curves 5 10MHz 1 3 5 2 4 6 7MHz Input Signal Frequency ® ® ADC-305 MECHANICAL DIMENSIONS INCHES (MM) 1.195 ±0.010 (30.35 .±0.25) ADC-305-1 24-Pin DIP (Plastic) 400mil 2.0g 13 24 0.339 ±0.008 (8.60 ±0.20) ADC-305-1 1 12 0.400 (10.16) 0.152 ±0.010 (3.85 ±0.25) 0.118 MIN. (3.00 MIN.) 0.011 ±0.003 (0.28 ±0.08) 0° to 15° 0.020 ±0.004 (0.50 ±0.10) 0.100 TYP. (2.54) SEATING PLANE 0.020 MIN. (0.50 MIN.) 0.047 ±0.006 (1.20 ±0.15) ADC-305-3 24-Pin SOP (Plastic) 300mil 0.3g 0.596 ±0.010 (15.15 ±0.25) 24 13 1 0.307 ±0.012 (7.80 ±0.30) 0.213 ±0.008 (5.40 ±0.20) ADC-305-3 12 0.078 ±0.011 (1.97 ±0.28) 0.272 (6.90) 0.007 ±0.005 (0.18 ±0.13) 0.050 TYP. (1.27) 0.009 ±0.003 (0.23 ±0.08) 0.018 ± 0.004 (0.45 ± 0.10) 0.020 ±0.008 (0.50 ±0.20) ORDERING INFORMATION ® ® MODEL NUMBER PACKAGE ADC-305-1 ADC-305-3 24-Pin Plastic DIP 400 mil 24-Pin Plastic SOP 300 mil ISO 9001 R DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: [email protected] Data Sheet Fax Back: (508) 261-2857 E G I S T E R E D DS-0342 6/98 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.