0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA GENERAL DESCRIPTION The AL2007LA is a Phase-Locked Loop (PLL) frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation: Fout = ( m*Fin ) / ( p* 2S) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m,p and s are the values for programmable dividers. AL2007LA consists of a phase/Frequency Detector(PFD), a Charge Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown in Figure1. FEATURES — 0.35um CMOS device technology — 3.3 Volt Single power supply — VCO frequency range: 60~170MHz — Output frequency range: 20~170MHz — Jitter ±150ps — Duty ratio 40% to 60% at 170MHz — Frequency changed by programmable divider — Power down mode IMPORTANT NOTICE Please contact SEC application engineer to confirm the proper selection of M,P,S value. FUNCTIONAL BLOCK DIAGRAM Fin Pre Divider P PFD Charge Pump Loop Filter (External) VCO Post Scaler S Fout Main Divider M Figure 1. Phase Lockd Loop Block Diagram 1 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA CORE PIN DESCRIPTION Name I/O Type I/O Pad VDD DP vddd Digital power supply VSS DG vssd Digital ground VDDA AP vdda Analog power supply VSSA AG vssa Analog ground VBB AB/DB vbba Analog/Digital sub bias Power FIN DI picc_bb FILTER AO poar50_bb FOUT DO pot12_bb PWRDN DI picc_bb FSPLL clock power down. - PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSS. P[5:0] DI picc_bb The values for 6bit programmable pre-divider. M[7:0] DI picc_bb The values for 8bit programmable main divider. S[1:0] DI picc_bb The values for 2bit programmable post scaler. I/O Type Abbr. — AI: Analog Input — DI: Digital Input — AO: Analog Output — DO: Digital Output — AB: Analog Bidirectional — DB: Digital Bidirectional — AP: Analog Power — DP: Digital Power — AG: Analog Ground — DG: Digital Ground 2 Pin Description PLL clock input - Pump out is connected to Filter - A capacitor is connected between the pin and analog ground 20MHz~170MHz clock output 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA CORE CONFIGURATION FIN FOUT PWRDN M[7:0] P[5:0] S[1:0] M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] FILTER al2007la P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1] 3 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Applicable pin Supply Voltage VDD VDDA -0.3 to 3.8 V VDD,VDDA,VSS,VSSA Voltage on Any Digital Pin Vin Vss-0.3 to Vdd+0.3 V P[5:0],M[7:0],S[1:0] PWRDN Storage Temperature Tstg -45 to 125 °C - NOTES: 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5K resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit Supply Voltage Differential VDD - VDDA -0.1 0 +0.1 V External Loop Filter Capacitance LF Operating Temperature Topr 820 0 pF 70 °C NOTE: It is strongly recommended that all the supply pins (VDDA, VDD) be powered from the same source to avoid power latch-up. 4 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Operating Voltage VDD/VDDA 3.15 3.3 3.45 V Digital Input Voltage High Vih 2.0 Digital Input Voltage Low Vil 0.8 V Dynamic Current (CORE Level without I/O Cell) Idd 3.5 mA Power Down Current Ipd 120 uA V AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Input Frequency FIN 3 14.318 40 MHz Output Clock Frequency FOUT 20 170 MHz VCO Output Clock Frequency Fvco 20 170 MHz Input Clock Duty Cycle TID 40 60 % Output Clock Duty Cycle TOD 40 60 % Locking Time TLT 150 us Cycle to Cycle Jitter TJCC +150 ps -150 5 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA FUNCTION DESCRIPTION A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. — The voltage-controlled oscillator to generate the output frequency — The divider P devides the reference frequency by p — The divider M devides the VCO output frequency by m — The divider S divides the VCO output frequency by s — The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. — The loop filter removes high frequency components in charge pump voltage and does smooth and clean control of VCO The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = m * Fin / p*s If Fin = 14.318MHz, and m=M+8 , p=P+2, s=2^S Digital data format: Main Divider Pre Divider Post Scaler M7,M6,M5,M4,M3,M2,M1,M0 P5,P4,P3,P2,P1,P0 S0,S1 NOTES: 1. S[1] - S[0]: Output Frequency Scaler 2. M[7] - M[0]: VCO Frequency Divider 3. P[5] - P[0]: Reference Frequency Input Divider 6 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA OUTPUT FREQUENCY EQUATION & TABLE FOU T = Frequency Equation : (m+8) (p+2) x 2 S x F IN Table 1. Example of Divider Ratio M7 M6 M5 M4 M3 M2 M1 M0 m M P6 P5 P4 P3 P2 P1 P0 p (m+8) 0 1 0 1 0 1 0 1 85 93 P S1 S0 2S 0 0 1 (p+2) 0 1 0 1 0 1 0 42 44 NOTES: 1. Don't set the P or M as zero, that is 000000 / 00000000 2. The proper range of P and M : 1<=P<=62, 1<=M<=248 3. The P and M must be selected considering stability of PLL and VCO output frequency range 4. Please consult with SEC application engineer to select the proper P, M and S values 7 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA CORE EVALUATION GUIDE For the embedded PLL, we must consider the test circuits for the embedded PLL core inmultiple applications. Hence the following requirements should be satisfied. — The FILTER and FOUT pins must be bypassed for external test. — For PLL test (Below 2 examples), it is needed to control the dividers - M[7:0],P[5:0] and S[1:0] -that generate multiple clocks. Example #1. Registers can be used for easy control of divider values. Example #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX. 3.3V Power Digital 3.3V Analog Power GND External Clock Source GND FIN VDD VSS VDDA VSSA VBBA FOUT PWRDN al2007la M[7:0] #1.16bit Register Block FILTER P[5:0] 820pF S[1:0] VSSA Select Pin NOTES Test Pins of N Sample bits Internal Divider Signal Line 8 #2 M U X : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 103 CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA CORE LAYOUT GUIDE — The digital power(VDD,VSS) and the analog power(VDA,VSSA) must be dedicated to PLL only and seperated. If the dedicated VDD and VSS is not allowed that of the least power consuming block is shared with the PLL. — The PIA pad is used as a FILTER pad that contains only ESD production diodes without any resistors and buffers. — The FOUT and FILTER pins must be placed far from the internal signals in order to avoid overlapping signal lines. — The blocks having a large digital switching current must be located away from the PLL core. — The PLL core must be shielded by guardring. — For the FOUT pad, you can use a custom drive buffer or POT12 buffer considering the drive current. WITHOUT XTAL-DRIVER USERS GUIDE — There are two crystal driver cell (XTAL-OSC and PSOSCM2) options for the AL2007LA PLL core. 1. If the crystal component not used , an external clock source is applied to the FIN * Please contact an SEC application engineer when using a crystal. 2. If the crystal component not used , an external clock I/O Buffer offered from Samsung's STD90 library is recommanded for use – When implementing an embedded PLL block, the following pins must be bypassed externally for testing the PLL locking function: * Without Xtal-driver : FIN,FILTER,FOUT,VDDA,VSSA,VDD and VSS. 9 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA FILTER FOUT VDDA VSSA Divider P FIN VDD VSS VBBA PFD &CP LF VCO Scaler S Used PICC_BB PAD Divider M PWRDN P[5:0] M[7:0] S[1:0] Glue Logic MUX * Divider Bus * Optional Test Pins Figure 1. The example of PLL block without crystal component (Normal Case) 10 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA PACKAGE CONFIGURATION 2bit Post Scaler Dummy Test Block Control pins 3.3V Digital PAD Power C 36 L L L L H H H H 3.3V I/O Power C 35 34 33 32 31 30 29 28 27 26 25 V D D D V S S D V S S D S 0 S 1 T S E L 0 T S E L 1 V D D O V S S O N C N C L H V D D 37 M0 D L H 38 M1 L H 39 M2 L H 40 L H 41 M4 VBBA 20 L H 42 M5 VBBA 19 L H 43 M6 8bit Main Divider NC 24 FOUT 23 al2007la M3 C 22 NC 21 PWRDN 18 103 10uF M7 NC FILTER 17 45 P0 NC 16 H 46 P1 FIN 15 L H 47 P2 VDDA 14 L H 48 P3 L H 44 L H L 6bit Pre Divider Input P 5 N C N C N C N C N C N C N C N C V S S A 1 2 3 4 5 6 7 8 9 10 11 H H L L P 4 V VDDA S S A 13 H L 820pF External Clock Source C 3.3V Analog Power 12 NOTES: 1. TSEL0,TSEL1 pins are internal dummy block test pins. 2. NC is Noconnection pin 11 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA PACKAGE PIN DESCRIPTION Name Pin No I/O Type Pin Description VDDD 35,36 DP Digital power supply VSSD 33,34 DG Digital ground PWRDN 18 DI FSPLL clock power down -PWRDN is High, PLL do not operating under this condition. - If isn't used this pin, tied to VSS. P[0]~P[5] 1,2,45~48 DI Pre-Divider Input(LSB) VDDA 13,14 AP Analog power supply VSSA 11,12 AG Analog ground VBBA 19,20 AB/DB Analog / Digtal Sub Bias Power FIN 15 AI Crystal input or external FREF input FOUT 22 DO 20MHZ~170MHz clock output FILTER 17 AO Pump out is connected to the FILTER. A 820pF Capcitor is connected between the pin and analog pin TSEL0 30 DI FOUT divide control pins. -End users used not this pins, tied to VDD or VSS TSEL1 29 DI FOUT divide control pins. -End users used not this pins, tied to VDD or VSS S[0]~S[1] 31,32 DI Post scaler input M[0]~M[7] 37~44 DI 8bit main divider input VDDO 28 PP I/O PAD Power VSSO 27 PG I/O PAD Ground NOTE: I/O TYPE PP and PG denote PAD power and PAD ground respectively. 12 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA DESIGN CONSIDERATIONS The following design consideratios apply: • Phase tolerance and jitter are independent of the PLL frequency. • Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA). It increases when the noise level increases. • A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. • The use of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. • The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA) connections to the PLL core. Seperate the traces from the chip's VDD/VSS,VDDA/VSSA supplies. - Use proper VDD/VSS,VDDA/VSSA de-coupling. - Use good power and ground sources on the board. - Use Power VBB for minimize substrate noise • The PLL core should be placed as close as possible to the dedicated loop filter and analog Power and ground pins. • It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. • Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction 13 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA FEEDBACK REQUEST Thank you for having an interest in our products. Please fill out this form, especially the items which you want to request. Parameter Customer SEC Unit Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle to cycle jitter (TJCC) 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M Period jitter (TJP) 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M Output duty ratio (TOD) Lock up time (TLT) Dynamic current Stand by current Filter capacitor — How many PLLs are embedded in your system ? — Do you need synchronization between input clock and output clock ? — Do you need another spec of jitter ? Parameter Customer Unit Long-term jitter (TJLT) psec (pk-pk) Tracking Jitter (TJT) psec (pk-pk) If you have another special request, please describe below. 14 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA JITTER DEFINITION Period Jitter Period jitter is the maximum deviation of output clock's transition from its ideal position. T1 Ideal Cycle Fout TJP Cycle-to-Cycle Jitter Cycle-to-cycle jitter is the maximum deviation of output clock's transition from its corresponding position of the previous cycle. Ti-1 Ti Ti+1 Fout TJCC = max (Ti+1 - Ti) Long-Term Jitter Long-term jitter is the maximum deviation of output clock' transition from its ideal position, after many cycles. The term "many" depends on the application and the frequency. Cycle 0 Cycle N TJLP 15 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA Tracking Jitter Tracking jitter is the maximum deviation of output clock(FOUT)'s transition from input clock (FIN) position. Trigger Fin Delay Fout TJT 16