DM54LS299/DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The ’LS299 is an 8-bit universal shift/storage register with TRI-STATEÉ outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. Y Y Y Y Common I/O for reduced pin count Four operation modes: shift left, shift right, load and store Separate shift right serial input and shift left serial input for easy cascading TRI-STATE outputs for bus oriented applications Connection Diagram Dual-In-Line Package TL/F/9827 – 1 Order Number DM54LS299E, DM54LS299J, DM54LS299W, DM74LS299WM or DM74LS299N See NS Package Number E20A, J20A, M20B, N20A or W20A Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0–I/O7 Q0–Q7 Description Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9827 RRD-B30M115/Printed in U. S. A. DM54LS299/DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins June 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM54LS299 Parameter DM74LS299 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts(H) ts(L) Setup Time HIGH or LOW S0 or S1 to CP 24 24 24 24 ns th(H) th(L) Hold Time HIGH or LOW S0 or S1 to CP 5 5 0 0 ns ts(H) ts(L) Setup Time HIGH or LOW I/On, DS0, DS7 to CP 15 15 10 10 ns th(H) th(L) Hold Time HIGH or LOW I/On, DS0, DS7 to CP 5 5 0 0 ns tw(H) tw(L) CP Pulse Width HIGH or LOW 15 15 15 15 ns tw(L) MR Pulse Width LOW 15 15 ns trec Recovery Time MR to CP 10 10 ns 2 2 V V 0.7 0.8 V Q0, Q7 b 0.4 b 0.4 mA I/O0–I/O7 b 2.6 b 2.6 mA 4 8 mA 24 mA 70 §C Q0, Q7 I/O0–I/O7 12 b 55 125 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max Min DM54 Q0, Q7 DM74 I/O0 – I/O7 VOL II Low Level Output Voltage Input Current @ Max Input Voltage Typ (Note 1) Max Units b 1.5 V 2.5 2.7 3.4 V 2.4 VCC e Min, IOL e Max VIH e Min DM54 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VCC e Max, VI e 10V (DM54) VI e 7V (DM74) Inputs 0.1 mA Sn 0.2 mA 2 0.4 V Electrical Characteristics (Continued) Over recommended operating free air temperature range (unless otherwise noted) Symbol IIH Parameter Conditions High Level Input Current IIL Low Level Input Current IOS VCC e Max, VI e 2.7V VCC e Max, VI e 0.4V Typ (Note 1) Min Max Units Sn 40 mA Inputs 20 mA Sn b 0.8 mA Inputs b 0.4 mA Short Circuit Output Current VCC e Max (Note 2) Q0, Q7 b 20 b 100 I/O0 – I/O7 b 30 b 130 ICC Supply Current VCC e Max, OE e 4.5V 60 mA IOZH TRI-STATE Output Off Current High VCC e Max VO e 2.7V 40 mA IOZL TRI-STATE Output Off Current Low VCC e Max VO e 0.4V b 400 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol RL e 2 kX CL e 15 pF Parameter Min Units Max fmax Maximum Input Frequency 35 tPLH tPHL Propagation Delay CP to Q0 or Q7 26 28 MHz ns tPLH tPHL Propagation Delay CP to I/On 25 35 ns tPHL Propagation Delay MR to Q0 or Q7 28 ns tPHL Propagation Delay MR to I/On 35 ns tPZH tPZL Output Enable Time 18 25 ns tPHZ tPLZ Output Disable Time 15 20 ns Logic Symbol TL/F/9827 – 2 VCC e Pin 20 GND e Pin 10 3 mA Functional Description A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. The ’LS299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by the S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. Mode Select Table Inputs Response MR S1 S0 CP L H H H H X H L H L X X Asynchronous Reset; Q0 – Q7 e LOW H L Parallel Load; I/On x Qn H L Shift Right; DS0 x Q0, Q0 x Q1, etc. L L Shift Left; DS7 x Q7, Q7 x Q6, etc. L X Hold H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial 4 TL/F/9827 – 3 Logic Diagram 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number DM54LS299E NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS299J NS Package Number J20A 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS299WM NS Package Number M20B 20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS299N NS Package Number N20A 7 DM54LS299/DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flat Package (W) Order Number DM54LS299W NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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