MCP6021/1R/2/3/4
Rail-to-Rail Input/Output, 10 MHz Op Amps
Features
Description
•
•
•
•
The MCP6021, MCP6021R, MCP6022, MCP6023 and
MCP6024 from Microchip Technology Inc. are rail-torail input and output op amps with high performance.
Key specifications include: wide bandwidth (10 MHz),
low noise (8.7 nV/√Hz), low input offset voltage and low
distortion (0.00053% THD+N). The MCP6023 also
offers a Chip Select pin (CS) that gives power savings
when the part is not in use.
•
•
•
•
•
•
Rail-to-Rail Input/Output
Wide Bandwidth: 10 MHz (typical)
Low Noise: 8.7 nV/√Hz, at 10 kHz (typical)
Low Offset Voltage:
- Industrial Temperature: ±500 µV (maximum)
- Extended Temperature: ±250 µV (maximum)
Mid-Supply VREF: MCP6021 and MCP6023
Low Supply Current: 1 mA (typical)
Total Harmonic Distortion:
- 0.00053% (typical, G = 1 V/V)
Unity Gain Stable
Power Supply Range: 2.5V to 5.5V
Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Applications
•
•
•
•
•
•
The MCP6021/1R/2/3/4 family is available in Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
Package Types
Automotive
Multi-Pole Active Filters
Audio Processing
DAC Buffer
Test Equipment
Medical Instrumentation
MCP6021
SOT-23-5
SPICE Macro Models
FilterLab® Software
Mindi™ Circuit Designer & Simulator
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
VOUTA 1
8 VDD
VSS 2
VINA– 2
7 VOUTB
VIN+ 3
4 VIN–
VINA+ 3
6 VINB–
VSS 4
5 VINB+
MCP6021R
SOT-23-5
VOUT 1
5 VSS
VDD 2
VIN+ 3
4 VIN–
MCP6021
PDIP SOIC,
MSOP, TSSOP
5.6 pF
Photo
Detector
100 kΩ
100 pF
MCP6022
PDIP SOIC, TSSOP
5 VDD
VOUT 1
Design Aids
•
•
•
•
•
•
The single MCP6021 and MCP6021R are available in
SOT-23-5. The single MCP6021, single MCP6023 and
dual MCP6022 are available in 8-lead PDIP, SOIC and
TSSOP. The Extended Temperature single MCP6021
is available in 8-lead MSOP. The quad MCP6024 is
offered in 14-lead PDIP, SOIC and TSSOP packages.
MCP6023
PDIP SOIC, TSSOP
NC 1
VIN– 2
8 CS
VIN+ 3
6 VOUT
VSS 4
5 VREF
MCP6024
PDIP SOIC, TSSOP
NC 1
8 NC
VIN– 2
7 VDD
VOUTA 1
14 VOUTD
VIN+ 3
6 VOUT
VINA– 2
13 VIND–
VSS 4
5 VREF
VINA+ 3
12 VIND+
VDD 4
MCP6021
VDD/2
7 VDD
11 VSS
VINB+ 5
10 VINC+
VINB– 6
9 VINC–
VOUTB 7
8 VOUTC
Transimpedance Amplifier
© 2009 Microchip Technology Inc.
DS21685D-page 1
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 2
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA
†† See Section 4.1.2 “
Absolute Maximum Ratings †
Input Voltage and Current Limits”.
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ................................. –65° C to +150° C
Maximum Junction Temperature (TJ)........................ .+150° C
ESD Protection On All Pins (HBM; MM) .............. ≥ 2 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2 and RL = 10 kΩ to VDD/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Industrial Temperature Parts
VOS
-500
—
+500
µV
VCM = 0V
Extended Temperature Parts
VOS
-250
—
+250
µV
VCM = 0V, VDD = 5.0V
Extended Temperature Parts
VOS
-2.5
—
+2.5
mV
VCM = 0V, VDD = 5.0V
TA = -40°C to +125°C
ΔVOS/ΔTA
—
±3.5
—
PSRR
74
90
—
Input Offset
Input Offset Voltage:
Input Offset Voltage Temperature Drift
Power Supply Rejection Ratio
µV/°C TA = -40°C to +125°C
dB
VCM = 0V
Input Current and Impedance
IB
—
1
—
pA
Industrial Temperature Parts
IB
—
30
150
pA
TA = +85°C
Extended Temperature Parts
IB
—
640
5,000
pA
TA = +125°C
IOS
—
±1
—
pA
Input Bias Current
Input Offset Current
Common-Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF
Common-Mode Input Range
VCMR
VSS-0.3
—
VDD+0.3
V
Common-Mode Rejection Ratio
CMRR
74
90
—
dB
VDD = 5V, VCM = -0.3V to 5.3V
CMRR
70
85
—
dB
VDD = 5V, VCM = 3.0V to 5.3V
CMRR
74
90
—
dB
VDD = 5V, VCM = -0.3V to 3.0V
Common-Mode
Voltage Reference (MCP6021 and MCP6023 only)
VREF Accuracy (VREF – VDD/2)
VREF_ACC
-50
—
+50
VREF Temperature Drift
ΔVREF/ΔT
—
±100
—
mV
AOL
90
110
—
VOL, VOH
VSS+15
—
VDD-20
mV
0.5V input overdrive
ISC
—
±30
—
mA
VDD = 2.5V
ISC
—
±22
—
mA
VDD = 5.5V
µV/°C TA = -40°C to +125°C
A
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
dB
VCM = 0V,
VOUT = VSS+0.3V to VDD-0.3V
Output
Maximum Output Voltage Swing
Output Short Circuit Current
© 2009 Microchip Technology Inc.
DS21685D-page 3
MCP6021/1R/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
VDD
2.5
—
5.5
V
IQ
0.5
1.0
1.35
mA
GBWP
—
10
—
MHz
Conditions
Power Supply
Supply Voltage
Quiescent Current per Amplifier
IO = 0
AC Response
Gain Bandwidth Product
Phase Margin
Settling Time, 0.2%
Slew Rate
PM
—
65
—
°
tSETTLE
—
250
—
ns
SR
—
7.0
—
V/µs
G = +1 V/V
G = +1 V/V, VOUT = 100 mVp-p
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = +1 V/V
THD+N
—
0.00053
—
%
VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V, RL = 600Ω
THD+N
—
0.00064
—
%
VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V
THD+N
—
0.0014
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +10 V/V
THD+N
—
0.0009
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +100 V/V
THD+N
—
0.005
—
%
VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
Noise
Input Noise Voltage
Eni
—
2.9
—
µVp-p
Input Noise Voltage Density
eni
—
8.7
—
nV/√Hz f = 10 kHz
f = 0.1 Hz to 10 Hz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
CS Logic Threshold, Low
VIL
CS Input Current, Low
ICSL
CS Logic Threshold, High
CS Input Current, High
Units
Conditions
VSS
—
0.2 VDD
V
-1.0
0.01
—
µA
VIH
0.8 VDD
—
VDD
V
ICSH
—
0.01
2.0
µA
CS = VDD
ISS
-2
-0.05
—
µA
CS = VDD
IO(LEAK)
—
0.01
—
µA
CS = VDD
CS Low to Amplifier Output Turn-on Time
tON
—
2
10
µs
G = +1, VIN = VSS,
CS = 0.2VDD to VOUT = 0.45VDD time
CS High to Amplifier Output High-Z Time
tOFF
—
0.01
—
µs
G = +1, VIN = VSS,
CS = 0.8VDD to VOUT = 0.05VDD time
VHYST
—
0.6
—
V
VDD = 5.0V, Internal Switch
CS Low Specifications
CS = VSS
CS High Specifications
GND Current
Amplifier Output Leakage
CS Dynamic Specifications
Hysteresis
DS21685D-page 4
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Industrial Temperature Range
TA
-40
—
+85
°C
Extended Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1:
The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any
case, the internal junction temperature (TJ) must not exceed the absolute maximum specification of 150°C.
1.1
CS
tON
VOUT
High-Z
ISS
-50 nA
(typical)
ICS
tOFF
Amplifier On
-1 mA
(typical)
High-Z
-50 nA
(typical)
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
VIN
RN
1 kΩ
10 nA
(typical)
10 nA
(typical)
10 nA
(typical)
FIGURE 1-1:
Timing diagram for the CS
pin on the MCP6023.
VDD
0.1 µF 1 µF
CB1 CB2
VOUT
MCP6021
VDD/2 RG
RF
2 kΩ
CL
60 pF
RL
10 kΩ
VL
2 kΩ
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD/2 RN
1 kΩ
VIN
VDD
0.1 µF 1 µF
CB1 CB2
VOUT
MCP6021
RG
RF
2 kΩ
2 kΩ
CL
60 pF
RL
10 kΩ
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
© 2009 Microchip Technology Inc.
DS21685D-page 5
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 6
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Input Offset Voltage (µV)
Input Offset Voltage (µV)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.5V.
© 2009 Microchip Technology Inc.
20
20
16
12
8
4
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
3.0
1.5
2.5
0.5
2.0
-40°C
+25°C
+85°C
+125°C
VDD = 5.5V
0.0
1.5
Common Mode Input Voltage (V)
500
400
300
200
100
0
-100
-200
-300
-400
-500
-0.5
Input Offset Voltage (µV)
Input Offset Voltage (µV)
FIGURE 2-5:
Input Offset Voltage Drift,
(Extended Temperature Parts).
-40°C
+25°C
+85°C
+125°C
1.0
-4
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage,
(Extended Temperature Parts).
500
400 VDD = 2.5V
300
200
100
0
-100
-200
-300
-400
-500
-0.5
0.0
0.5
438 Samples
VCM = 0V
TA = -40°C to +125°C
-8
E-Temp
Parts
-16
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-20
240
200
160
120
80
0
40
-40
-80
Percentage of Occurances
FIGURE 2-4:
Input Offset Voltage Drift,
(Industrial Temperature Parts).
438 Samples
VDD = 5.0V
VCM = 0V
TA = +25°C
-120
-160
-200
-240
Percentage of Occurances
E-Temp
Parts
16
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage,
(Industrial Temperature Parts).
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
12
500
400
300
200
100
0
-100
-200
-300
-400
-500
0%
8
2%
4
4%
0
6%
-4
8%
1192 Samples
VCM = 0V
TA = -40°C to +85°C
-8
10%
I-Temp
Parts
-12
12%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-12
1192 Samples
VCM = 0V
TA = +25°C
1.0
I-Temp
Parts
-16
14%
-20
16%
Percentage of Occurances
Percentage of Occurances
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
DS21685D-page 7
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
200
Input Offset Voltage (µV)
50
0
-50
-100
-150
-200
VDD = 5.0V
VCM = 0V
-250
VDD = 5.5V
50
0
VDD = 2.5V
-50
-100
-150
Output Voltage (V)
FIGURE 2-10:
Output Voltage.
FIGURE 2-8:
vs. Frequency.
1.E+02
1.E+03
1.E+04
100
1k
10k
Frequency (Hz)
1.E+05
1.E+06
100k 1M
5.5
1.E+01
10
5.0
1.E+00
1
4.5
1.E-01
0.1
f = 10 kHz
4.0
1
f = 1 kHz
3.5
10
VDD = 5.0V
3.0
100
24
22
20
18
16
14
12
10
8
6
4
2
0
-0.5
Input Noise Voltage Density
(nV/√Hz)
1,000
Input Offset Voltage vs.
2.5
Input Offset Voltage vs.
2.0
FIGURE 2-7:
Temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
125
1.5
0
25
50
75
100
Ambient Temperature (°C)
1.0
-25
0.5
-50
Input Noise Voltage Density
(nV/√Hz)
100
-200
-300
Common Mode Input Voltage (V)
Input Noise Voltage Density
FIGURE 2-11:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
110
100
PSRR+
PSRR-
105
PSRR, CMRR (dB)
90
CMRR, PSRR (dB)
VCM = VDD/2
150
0.0
Input Offset Voltage (µV)
100
80
70
60
CMRR
50
40
CMRR
100
95
90
PSRR (VCM = 0V)
85
80
75
30
20
100
1.E+02
1.E+03
1k
1.E+04
10k
1.E+05
100k
1.E+06
1M
70
-50
-25
Frequency (Hz)
FIGURE 2-9:
Frequency.
DS21685D-page 8
CMRR, PSRR vs.
FIGURE 2-12:
Temperature.
0
25
50
75
100
Ambient Temperature (°C)
125
CMRR, PSRR vs.
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
10,000
VDD = 5.5V
1,000
IB, TA = +125°C
IOS, TA = +125°C
100
IB, TA = +85°C
10
IOS, TA = +85°C
10,000
Input Bias, Offset Currents
(pA)
1,000
IOS
10
1
1
25 35 45 55 65 75 85 95 105 115 125
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
+125°C
+85°C
+25°C
-40°C
Ambient Temperature (°C)
FIGURE 2-16:
vs. Temperature.
Quiescent Current
(mA/amplifier)
FIGURE 2-13:
Input Bias, Offset Currents
vs. Common Mode Input Voltage.
Quiescent Current
(mA/amplifier)
IB
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-14:
Supply Voltage.
Quiescent Current vs.
20
15
+125°C
+85°C
+25°C
-40°C
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
FIGURE 2-15:
Output Short-Circuit Current
vs. Supply Voltage.
© 2009 Microchip Technology Inc.
Open-Loop Gain (dB)
30
25
VDD = 2.5V
VCM = VDD - 0.5V
-25
FIGURE 2-17:
Temperature.
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
1.E+00
1
Input Bias, Offset Currents
VDD = 5.5V
-50
35
Output Short Circuit Current
(mA)
VCM = VDD
VDD = 5.5V
0
25
50
75
100
Ambient Temperature (°C)
Quiescent Current vs.
0
-15
-30
-45
-60
-75
Phase
-90
-105
-120
-135
-150
Gain
-165
-180
-195
-210
10 100 1k 10k 100k 1M 10M 100M
1.E+01
125
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Open-Loop Phase (°)
Input Bias, Offset Currents (pA)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
1.E+08
Frequency (Hz)
FIGURE 2-18:
Frequency.
Open-Loop Gain, Phase vs.
DS21685D-page 9
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
120
VDD = 5.5V
DC Open-Loop Gain (dB)
120
110
VDD = 2.5V
100
90
115
110
105
VDD = 2.5V
100
95
90
1.E+02
1.E+03
1.E+04
1.E+05
1k
10k
Load Resistance (Ω)
FIGURE 2-19:
Load Resistance.
-50
100k
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-22:
Temperature.
DC Open-Loop Gain vs.
Gain Bandwidth Product
(MHz)
VCM = VDD/2
110
VDD = 5.5V
100
90
VDD = 2.5V
80
70
0.00
0.05
0.10
0.15
0.20
0.25
0.30
12
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
4
45
30
15
VDD = 5.0V
0
0
FIGURE 2-23:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
Gain Bandwidth Product
(MHz)
14
Phase Margin, G = +1 (°)
100
90
80
70
60
50
40
30
20
10
0
125
FIGURE 2-21:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
DS21685D-page 10
60
Phase Margin, G = +1
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
FIGURE 2-20:
Small Signal DC Open-Loop
Gain vs. Output Voltage Headroom.
GBWP, VDD = 5.5V
GBWP, VDD = 2.5V
PM,
VDD = 2.5V
PM,
VDD = 5.5V
90
75
8
Output Voltage Headroom (V);
VDD - VOH or VOL - VSS
10
9
8
7
6
5
4
3
2
1
0
105
Gain Bandwidth Product
10
2
125
DC Open-Loop Gain vs.
14
120
Gain Bandwidth Product
(MHz)
-25
Phase Margin, G = +1 (°)
80
100
DC Open-Loop Gain (dB)
VDD = 5.5V
12
105
Gain Bandwidth Product
10
75
8
Phase Margin, G = +1
6
60
45
4
2
90
30
VDD = 5.0V
VCM = VDD/2
15
0
Phase Margin, G = +1 (°)
DC Open-Loop Gain (dB)
130
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
FIGURE 2-24:
Gain Bandwidth Product,
Phase Margin vs. Output Voltage.
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
10
11
10
9
8
7
6
5
4
3
2
1
0
Falling, VDD = 5.5V
Rising, VDD = 5.5V
Falling, VDD = 2.5V
Rising, VDD = 2.5V
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-25:
100
VDD = 2.5V
1
1.E+04
1.E+05
10k
G = +100 V/V
THD+N (%)
G = +100 V/V
G = +10 V/V
0.0100%
G = +10 V/V
0.0010%
G = +1 V/V
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
0.0001%
0.0001%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
6
VDD = 5.0V
G = +2 V/V
5
VOUT
4
VIN
3
2
1
0
-1
10
20
30
40 50 60 70
Time (10 µs/div)
80
90
100
FIGURE 2-27:
The MCP6021/1R/2/3/4
family shows no phase reversal under overdrive.
© 2009 Microchip Technology Inc.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
FIGURE 2-29:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 20 kHz.
Channel to Channel Separation
(dB)
FIGURE 2-26:
Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
Input, Output Voltage (V)
1.E+07
10M
0.1000%
0.0010%
0
1.E+06
100k
1M
Frequency (Hz)
FIGURE 2-28:
Maximum Output Voltage
Swing vs. Frequency.
f = 1 kHz
BWMeas = 22 kHz
VDD = 5.0V
0.0100%
VDD = 5.5V
0.1
125
Slew Rate vs. Temperature.
0.1000%
THD+N (%)
Maximum Output Voltage
Swing (VP-P)
Slew Rate (V/µs)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
135
130
125
120
115
110
G = +1 V/V
105
1.E+03
1k
1.E+04
1.E+05
10k
100k
Frequency (Hz)
1.E+06
1M
FIGURE 2-30:
Channel-to-Channel
Separation vs. Frequency (MCP6022 and
MCP6024 only).
DS21685D-page 11
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
Output Voltage Headroom
VDD-VOH or VOL-VSS (mV)
Output Voltage Headroom;
VDD-VOH or VOL-VSS (mV)
1,000
100
10
VOL - VSS
VDD - VOH
1
0.01
0.1
1
Output Current Magnitude (mA)
VOL - VSS
VDD - VOH
-50
10
FIGURE 2-31:
Output Voltage Headroom
vs. Output Current.
-25
Output Voltage Headroom
G = -1 V/V
RF = 1 kΩ
Output Voltage (10 mV/div)
5.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
4.E-02
3.E-02
2.E-02
1.E-02
0.E+00
-1.E-02
-2.E-02
-3.E-02
-4.E-02
-5.E-02
-5.E-02
-6.E-02
-6.E-02
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
0.E+00
2.E-06
2.E-07
4.E-07
6.E-07
Time (200 ns/div)
FIGURE 2-32:
Pulse Response.
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Time (200 ns/div)
Small-Signal Non-inverting
FIGURE 2-35:
Response.
Small-Signal Inverting Pulse
5.0
5.0
G = +1 V/V
4.5
G = -1 V/V
RF = 1 kΩ
4.5
4.0
Output Voltage (V)
Output Voltage (V)
125
6.E-02
G = +1 V/V
5.E-02
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-34:
vs. Temperature.
6.E-02
Output Voltage (10 mV/div)
10
9
8
7
6
5
4
3
2
1
0
0.5
0.E+00
5.E-07
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
0.0
0.E+00
5.E-07
Time (500 ns/div)
FIGURE 2-33:
Pulse Response.
DS21685D-page 12
Large-Signal Non-inverting
1.E-06
2.E-06
2.E-06
3.E-06
3.E-06
4.E-06
4.E-06
5.E-06
5.E-06
Time (500 ns/div)
FIGURE 2-36:
Response.
Large-Signal Inverting Pulse
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
50
40
30
20
10
0
-10
-20
-30
-40
-50
VREF Accuracy; V REF – V DD/2
(mV)
VREF Accuracy; V REF – V DD/2
(mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
50
40
30
20
10
0
-10
-20
-30
-40
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-37:
VREF Accuracy vs. Supply
Voltage (MCP6021 and MCP6023 only).
VDD = 2.5V
-25
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-40:
VREF Accuracy vs.
Temperature (MCP6021 and MCP6023 only).
1.6
Op Amp
shuts off here
1.4
Quiescent Current
(mA/amplifier)
Op Amp
turns on here
1.4
Quiescent Current
(mA/amplifier)
VDD = 5.5V
-50
1.6
1.2
1.0
CS swept
high to low
0.8
Hysteresis
0.6
CS swept
low to high
VDD = 2.5V
G = +1 V/V
VIN = 1.25V
0.4
0.2
Op Amp
turns on here
Op Amp
shuts off here
1.2
Hysteresis
1.0
0.8
CS swept
high to low
0.6
0.4
0.2
VDD = 5.5V
G = +1 V/V
VIN = 2.75V
CS swept
low to high
0.0
0.0
0.0
0.5
1.0
1.5
2.0
Chip Select Voltage (V)
Chip Select Voltage (V)
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E-05
10µ
1.E-06
1µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
VDD = 5.0V
G = +1 V/V
VIN = VSS
CS Voltage
VOUT
Output
on
Output
on
Output High-Z
FIGURE 2-41:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 5.5V.
Input Current Magnitude (A)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.5
FIGURE 2-38:
Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
Chip Select Voltage,
Output Voltage (V)
Representative Part
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.0E-05
Time (5 µs/div)
FIGURE 2-39:
Chip Select (CS) to
Amplifier Output Response Time (MCP6023
only).
© 2009 Microchip Technology Inc.
3.5E-05
Input Voltage (V)
FIGURE 2-42:
Measured Input Current vs.
Input Voltage (below VSS).
DS21685D-page 13
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 14
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6021
MCP6021R MCP6022 MCP6023 MCP6024
Symbol
Description
PDIP,
SOIC,
MSOP,
TSSOP
(Note 1)
SOT-23-5
SOT-23-5
(Note 2)
PDIP,
SOIC,
TSSOP
PDIP,
SOIC,
TSSOP
PDIP,
SOIC,
TSSOP
6
1
1
1
6
1
2
4
4
2
2
2
VIN–, VINA–
3
3
3
3
3
3
VIN+, VINA+
7
5
2
8
7
4
VDD
—
—
—
5
—
5
VINB+
Non-inverting Input (op amp B)
—
—
—
6
—
6
VINB–
Inverting Input (op amp B)
—
—
—
7
—
7
VOUTB
Analog Output (op amp B)
—
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
—
10
VINC+
4
2
5
4
4
11
VSS
—
—
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
—
13
VIND–
Inverting Input (op amp D)
Analog Output (op amp D)
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
Non-inverting Input (op amp C)
Negative Power Supply
—
—
—
—
—
14
VOUTD
5
—
—
—
5
—
VREF
—
—
—
—
8
—
CS
Chip Select
1, 8
—
—
—
1
—
NC
No Internal Connection
Note 1:
2:
3.1
VOUT, VOUTA Analog Output (op amp A)
Reference Voltage
The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.
The MCP6021R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts.
Analog Outputs
3.4
Chip Select Digital Input (CS)
The op amp output pins are low-impedance voltage
sources.
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.2
3.5
Analog Inputs
The op amp non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Reference Voltage (VREF, )
MCP6021 and MCP6023
Mid-supply reference voltage provided by the single op
amps (except in SOT-23-5 package). This is an
unbuffered, resistor voltage divider internal to the part.
© 2009 Microchip Technology Inc.
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 2.5V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a bypass capacitor.
DS21685D-page 15
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 16
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.0
APPLICATIONS INFORMATION
VDD
The MCP6021/1R/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applications.
4.1
D1
V1
R1
Rail-to-Rail Input
4.1.1
R2
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
Input
Stage
Bond V –
IN
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
FIGURE 4-2:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-42. Applications that are
high impedance may need to limit the useable voltage
range.
VDD Bond
Pad
VIN+ Bond
Pad
MCP602X
V2
PHASE REVERSAL
The MCP6021/1R/2/3/4 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-42 shows the input voltage exceeding the supply voltage without any phase reversal.
4.1.2
D2
4.1.3
NORMAL OPERATION
The input stage of the MCP6021/1R/2/3/4 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this topology, the device operates with Vcm up to 0.3V above
VDD and 0.3V below VSS.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
© 2009 Microchip Technology Inc.
4.2
Rail-to-Rail Output
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
RL = 10 kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typical performance.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response.
DS21685D-page 17
MCP6021/1R/2/3/4
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
VIN
1 V/V (unity gain). CG also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
VIN
VOUT
RISO
MCP602X
CG
VOUT
RF
RG
CL
FIGURE 4-3:
Output Resistor RISO
Stabilizes Large Capacitive Loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5:
Non-inverting Gain Circuit
with Parasitic Capacitance.
The largest value of RF in Figure 4-5 that should be
used is a function of noise gain (see GN in Section 4.3
“Capacitive Loads”) and CG. Figure 4-6 shows results
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
Recommended RISO (Ω)
GN ≥ +1
100
Maximum RF (Ω)
1.E+05
100k
1,000
CG = 7 pF
CG = 20 pF
1.E+04
10k
1k
1.E+03
CG = 50 pF
CG = 100 pF
100
1.E+02
1
10
10
100
1,000
10,000
Normalized Capacitance; CL/GN (pF)
FIGURE 4-4:
Recommended RISO values
for capacitive loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.4
GN > +1 V/V
Gain Peaking
Figure 2-35 and Figure 2-36 use RF = 1 kΩ to avoid
(frequency response) gain peaking and (step
response) overshoot. The capacitance to ground at the
inverting input (CG) is the op amp’s common mode
input capacitance plus board parasitic capacitance. CG
is in parallel with RG, which causes an increase in gain
at high frequencies for non-inverting gains greater than
DS21685D-page 18
10
Noise Gain; GN (V/V)
FIGURE 4-6:
Non-inverting gain circuit
with parasitic capacitance.
4.5
MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is pulled high, the supply current drops
to 10 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pulldown resistor connected to VSS, so it will go low if
the CS pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS pulse.
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.6
MCP6021 and MCP6023 Reference
Voltage
RG
VOUT
VIN
The single op amps (MCP6021 and MCP6023), not in
the SOT-23-5 package, have an internal mid-supply
reference voltage connected to the VREF pin (see
Figure 4-7). The MCP6021 has CS internally tied to
VSS, which always keeps the op amp on and always
provides a mid-supply reference. With the MCP6023,
taking the CS pin high conserves power by shutting
down both the op amp and the VREF circuitry. Taking
the CS pin low turns on the op amp and VREF circuitry.
VREF
CB
FIGURE 4-9:
Inverting gain circuit using
VREF (MCP6021 and MCP6023 only).
VDD
50 kΩ
If you don’t need the mid-supply reference, leave the
VREF pin open.
4.7
VREF
50 kΩ
CS
5 MΩ
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.8
VSS
(CS tied internally to VSS for MCP6021)
FIGURE 4-7:
Simplified internal VREF
circuit (MCP6021 and MCP6023 only).
See Figure 4-8 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (CB) also reduces noise by coupling the op
amp input to the source.
RG
RF
RF
Unused Op Amps
An unused op amp in a quad package (MCP6024)
should be configured as shown in Figure 4-10. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6024 (A)
¼ MCP6024 (B)
VDD
VOUT
CB
VREF
R1
VDD
VDD
VIN
FIGURE 4-8:
Non-inverting gain circuit
using VREF (MCP6021 and MCP6023 only).
To use the internal mid-supply reference for an
inverting gain circuit, connect the VREF pin to the
non-inverting input, as shown in Figure 4-9. The
capacitor CB helps reduce power supply noise on the
output.
© 2009 Microchip Technology Inc.
R2
VREF
R2
V REF = V DD × ------------------R1 + R2
FIGURE 4-10:
Unused Op Amps.
DS21685D-page 19
MCP6021/1R/2/3/4
4.9
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/1R/2/3/4 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-11 shows an example of this type of layout.
Guard Ring
VIN– VIN+
Separate digital from analog, low speed from high
speed and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
4.11
Typical Applications
4.11.1
FIGURE 4-11:
Layout.
1.
2.
Example Guard Ring
Non-inverting Gain and Unity-Gain Buffer.
a) Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
Inverting (Figure 4-11) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.10
A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
Figure 4-12 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a bandwidth of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
1.0 nF
8.45 kΩ 14.7 kΩ
33.2 kΩ
1.2 nF
100 pF
MCP602X
FIGURE 4-12:
A/D Converter Driver and
Anti-aliasing Filter with a 20 kHz Cutoff
Frequency.
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
High Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques will help you
achieve the performance shown in Section 1.0 “Electrical Characteristics” and Section 2.0 “Typical Performance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
DS21685D-page 20
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
4.11.2
OPTICAL DETECTOR AMPLIFIER
Figure 4-13 shows the MCP6021 op amp used as a
transimpedance amplifier in a photo detector circuit.
The photo detector looks like a capacitive current
source, so the 100 kΩ resistor gains the input signal to
a reasonable level. The 5.6 pF capacitor stabilizes this
circuit and produces a flat frequency response with a
bandwidth of 370 kHz.
5.6 pF
Photo
Detector
100 kΩ
100 pF
MCP6021
VDD/2
FIGURE 4-13:
Transimpedance Amplifier
for an Optical Detector.
© 2009 Microchip Technology Inc.
DS21685D-page 21
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 22
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6021/1R/2/3/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model available for the
MCP6021/1R/2/3/4 op amps is on Microchip’s web site
at www.microchip.com. This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. Within the
macro model file is information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4
Microchip Advanced Part Selector
(MAPS)
5.5
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards and their corresponding user’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
Some boards that are especially useful are:
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N: SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N: SOIC14EV
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
© 2009 Microchip Technology Inc.
DS21685D-page 23
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 24
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example: (E-temp)
5-Lead SOT-23 (MCP6021/MCP6021R)
Device
XXNN
E-Temp Code
MCP6021
EYNN
MCP6021R
EZNN
EY25
Note: Applies to 5-Lead SOT-23
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP6021
I/P256
0903
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
MCP6021
e3
E/P^^256
0903
OR
Example:
MCP6021
I/SN0903
256
OR
MCP6021E
e3
SN^^0903
256
Example:
8-Lead MSOP
6021E
XXXXXX
YWWNNN
903256
Example:
8-Lead TSSOP
XXXX
6021
YYWW
E903
NNN
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS21685D-page 25
MCP6021/1R/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6024)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6024-I/P
XXXXXXXXXXXXXX
0903256
MCP6024
E/P^^
e3
0903256
OR
14-Lead SOIC (150 mil) (MCP6024)
Example:
MCP6024ISL
XXXXXXXXXX
0903256
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
MCP6024
e3
E/SL^^
0903256
OR
14-Lead TSSOP (MCP6024)
Example:
XXXXXX
YYWW
6024E
0903
NNN
256
DS21685D-page 26
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
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DS21685D-page 29
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DS21685D-page 31
MCP6021/1R/2/3/4
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© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
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MCP6021/1R/2/3/4
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© 2009 Microchip Technology Inc.
DS21685D-page 35
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 36
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
APPENDIX A:
REVISION HISTORY
Revision D (February 2009)
Revision B (November 2003)
• Second Release of this Document
The following is the list of modifications:
Revision A (November 2001)
1.
• Original Release of this Document.
2.
3.
4.
5.
6.
7.
8.
Changed all references to 6.0V back to 5.5V
throughout document.
Design Aids: Name change for Mindi Simulation Tool.
Section 1.0 “Electrical Characteristics”, DC
Electrical Specifications: Corrected “Maximum Output Voltage Swing” condition from 0.9V
Input Overdrive to 0.5V Input Overdrive.
Section 1.0 “Electrical Characteristics”, AC
Electrical Specifications: Changed Phase
Margin condition from G = +1 to G= +1 V/V.
Section 1.0 “Electrical Characteristics”, AC
Electrical Specifications: Changed Settling
Time, 0.2% condition from G = +1 to G = +1 V/V.
Section 1.0 “Electrical Characteristics”:
Added Section 1.1 Test Circuits.
Section 5.0 “Design AIDS”: Name change for
Mindi Simulation Tool. Added new boards to
Section 5.5 “Analog Demonstration and
Evaluation Boards” and new application notes
to Section 5.6 “Application Notes”.
Updates Appendix A: “Revision History”
Revision C (March 2006)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
8.
Added SOT-23-5 package option for single op
amps MCP6021 and MCP6021R (E-temp only).
Added MSOP-8 package option for E-temp
single op amp (MCP6021).
Corrected package drawing on front page for
dual op amp (MCP6022).
Clarified spec conditions (ISC, PM and THD+N)
in
Section 2.0
“Typical
Performance
Curves”.
Added Section 3.0 “Pin Descriptions”.
Updated Section 4.0 “Applications information” for THD+N, unused op amps, and gain
peaking discussions.
Corrected and updated package marking information in Section 6.0 “Packaging Information”.
Added Appendix A: “Revision History”.
© 2009 Microchip Technology Inc.
DS21685D-page 37
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 38
© 2009 Microchip Technology Inc.
MCP6021/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
MCP6021
MCP6021T
Single Op Amp
Single Op Amp
(Tape and Reel for SOT-23, SOIC, TSSOP,
MSOP)
MCP6021R Single Op Amp
MCP6021RT Single Op Amp
(Tape and Reel for SOT-23)
MCP6022
Dual Op Amp
MCP6022T Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
MCP6023
Single Op Amp w/ CS
MCP6023T Single Op Amp w/ CS
(Tape and Reel for SOIC and TSSOP)
MCP6024
Quad Op Amp
MCP6024T Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
c)
a)
MCP6021RT-E/OT:Tape and Reel,
Extended temperature,
5LD SOT-23.
a)
MCP6022-I/P:
b)
c)
a)
b)
Temperature Range:
I
E
= -40°C to +85°C
= -40°C to +125°C
Package:
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6021, E-Temp; MCP6021R, E-Temp)
MS = Plastic MSOP, 8-lead
(MCP6021, E-Temp)
P
= Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP, 8-lead
(MCP6021,I-Temp; MCP6022, I-Temp, E-Temp;
MCP6023, I-Temp, E-Temp;)
ST = Plastic TSSOP, 14-lead
© 2009 Microchip Technology Inc.
MCP6021T-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23.
MCP6021-E/P:
Extended temperature,
8LD PDIP.
MCP6021-E/SN: Extended temperature,
8LD SOIC.
c)
a)
b)
c)
Industrial temperature,
8LD PDIP.
MCP6022-E/P:
Extended temperature,
8LD PDIP.
MCP6022T-E/ST: Tape and Reel,
Extended temperature,
8LD TSSOP.
MCP6023-I/P:
Industrial temperature,
8LD PDIP.
MCP6023-E/P:
Extended temperature,
8LD PDIP.
MCP6023-E/SN: Extended temperature,
8LD SOIC.
MCP6024-I/SL:
Industrial temperature,
14LD SOIC.
MCP6024-E/SL: Extended temperature,
14LD SOIC.
MCP6024T-E/ST: Tape and Reel,
Extended temperature,
14LD TSSOP.
DS21685D-page 39
MCP6021/1R/2/3/4
NOTES:
DS21685D-page 40
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS21685D-page 41
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02/04/09
DS21685D-page 42
© 2009 Microchip Technology Inc.