AD ADN4605 4.25 gbps 40 ã 40 digital crosspoint switch 3 db, 6 db, or 12 db boost Datasheet

4.25 Gbps 40 × 40 Digital
Crosspoint Switch
ADN4605
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DVCC
IP[39:0]
VTTIA,
VTTIB
IN[39:0]
Rx
VCC
40 × 40
SWITCH
MATRIX
EQ
Tx
OP[39:0]
PREEMPHASIS
VTTOA,
VTTOB
ON[39:0]
EQUALIZATION
SETTINGS
CONNECTION
MAP 1
CONNECTION
MAP 0
RESET
SER/PAR
I2C/SPI
(UPDATE)
CS
SCL/SCK/
WE
SDI/RE
OUTPUT
LEVEL
SETTINGS
PREEMPHASIS
LEVEL
SETTINGS
DATA[0]/
SDA/SDO
DATA[1]
(UPDATE)
DATA[7:2]
PARALLEL/SERIA L CONTROL
LOGIC INTERFACE
ADDR[7:0]
ADN4605
VEE
09796-001
DC to 4.25 Gbps per port NRZ data rate
Adjustable receive equalization
3 dB, 6 dB, or 12 dB boost
Compensates over 40 inches of FR4 at 4.25 Gbps
Adjustable transmit preemphasis/deemphasis
Programmable boost and output level
Compensates over 40 inches of FR4 at 4.25 Gbps
Low power
105 mW per channel at 2.5 V (400 mV p-p differential
output level swing)
40 × 40, fully differential, nonblocking array
Double rank connection programming with dual maps
Low jitter, typically <25 ps
Flexible 2.5 V to 3.3 V supply range
DC- or ac-coupled differential PECL/CML inputs
Differential CML outputs
Per-lane polarity inversion for routing ease
50 Ω on-chip I/O termination with disable feature
Supports 8b10b, scrambled or uncoded NRZ data
Serial (IC slave or SPI) control interface
Parallel control interface
Figure 1.
APPLICATIONS
Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI)
Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI, 4x Fibre Channel, Infiniband®, and GbE over backplane
Data storage networks
GENERAL DESCRIPTION
The ADN4605 is a 40 × 40 asynchronous, protocol agnostic,
digital crosspoint switch, with 40 differential PECL/CMLcompatible inputs and 40 differential programmable CML
outputs.
The ADN4605 nonblocking switch core implements a 40 × 40
crossbar and supports independent channel switching through
serial and parallel control interfaces. The ADN4605 has low
latency and very low channel-to-channel skew.
The ADN4605 is optimized for NRZ signaling with data rates of
up to 4.25 Gbps per port. Each port offers adjustable levels of
input equalization, programmable output swing, and output
preemphasis/deemphasis.
An I2C, SPI, or parallel interface is used to communicate with
the device for control of connectivity and other features.
The ADN4605 is assembled in a 35 mm × 35 mm, 352 BGA
package and operates over a temperature range of −40°C
to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADN4605
TABLE OF CONTENTS
Features .............................................................................................. 1
Transmitters ................................................................................ 29
Functional Block Diagram .............................................................. 1
Termination................................................................................. 32
2
Applications....................................................................................... 1
I C Serial Control Interface........................................................... 33
General Description ......................................................................... 1
I2C Data Write............................................................................. 33
Revision History ............................................................................... 2
I2C Data Read.............................................................................. 34
Specifications..................................................................................... 3
SPI Serial Control Interface .......................................................... 35
Electrical Specifications............................................................... 3
Parallel Control Interface .............................................................. 38
2
I C Timing Specifications............................................................ 5
Address Inputs: ADDR[7:0]...................................................... 38
SPI Timing Specifications ........................................................... 5
Data Inputs/Outputs: DATA[7:0]............................................. 38
Parallel Mode Specifications ....................................................... 6
Write Operation.......................................................................... 38
Absolute Maximum Ratings............................................................ 7
Read Operation........................................................................... 38
ESD Caution.................................................................................. 7
Register Map ................................................................................... 39
Pin Configuration and Function Descriptions............................. 8
Applications Information .............................................................. 49
Typical Performance Characteristics ........................................... 18
Supply Sequencing ..................................................................... 51
Theory of Operation ...................................................................... 24
Power Dissipation....................................................................... 51
Introduction ................................................................................ 24
Output Compliance ................................................................... 51
Receivers ...................................................................................... 25
Printed Circuit Board (PCB) Layout Guidelines ................... 54
Polarity Inversion ....................................................................... 26
Outline Dimensions ....................................................................... 55
Switch Core ................................................................................. 27
Ordering Guide............................................................................... 55
Reset ............................................................................................. 28
REVISION HISTORY
6/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
ADN4605
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VCC = 2.5 V, VTTIx = 2.5 V, VTTOx = 2.5 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, output level (OLEV) = 4 (16 mA), preemphasis (PE) = 0 (0 dB),
equalizer (EQ) = 1 (3 dB), data rate = 4.25 Gbps (PRBS7 data pattern), ac-coupled inputs and outputs, differential input swing = 800 mV p-p,
TA = 25°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Data Rate (DR) per Channel (NRZ)
Deterministic Jitter
Random Jitter
Residual Deterministic Jitter with
Receive Equalization
Residual Deterministic Jitter with
Transmit Preemphasis
Propagation Delay
Channel-to-Channel Skew
Switching Time
Output Rise/Fall Time
INPUT CHARACTERISTICS
Minimum Differential Input
Voltage Swing1
Maximum Differential Input
Voltage Swing1
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Per-Port Output Current
TERMINATION CHARACTERISTICS
Resistance
Temperature Coefficient
POWER SUPPLY
Operating Range
VCC
DVCC
VTTIA, VTTIB
VTTOA, VTTOB
Supply Current
ICC
IDVCC
ITTIA + ITTIB
ITTOA+ ITTOB
Conditions
Min
Typ
dc
Max
Unit
4.25
Data rate ≤ 4.25 Gbps, no channel
RMS, no channel
Data rate = 4.25 Gbps, 20 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 30 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 40 in. FR4, EQ boost = 12 dB
Data rate = 4.25 Gbps, 20 in. FR4, PE boost = 5.6 dB
Data rate = 4.25 Gbps, 30 in. FR4, PE boost = 6.8 dB
Data rate = 4.25 Gbps, 40 in. FR4, PE boost = 9.5 dB
Input to output
Earliest input/output lane to latest input/output lane
Update logic switching to 50% output data
20% to 80%
20
0.8
14
15
25
22
28
32
920
200
20
108
Gbps
ps p-p
ps rms
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
ps p-p
ps
ps
ns
ps
VICM = VCC − 0.6 V
50
mV p-p diff
VICM = VCC − 0.6 V
2000
mV p-p diff
Single-ended absolute voltage level, VL
Single-ended absolute voltage level, VH
VEE + 1.0
Differential, PE boost = 0 dB, default output level, at dc
Single-ended absolute voltage level, VL
Single-ended absolute voltage level, VH
PE boost = 0 dB, default output level
PE boost = 6 dB, default output level
670
800
875
VCC – 1.4
VCC + 0.3
16
32
mV p-p diff
V
V
mA
mA
Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX
88
100
0.015
114
Ω
Ω/°C
VEE = 0 V
VEE = 0 V
VEE = 0 V
VEE = 0 V
Inputs/outputs disabled (reset condition)
2.25
3.0
2.5
3.3
2.5
2.5
3.6
3.6
VCC + 0.3
VCC + 0.3
V
V
V
V
55
0.3
0
0
64
1.1
1.5
1.5
mA
mA
mA
mA
Inputs floating
Outputs floating
Rev. 0 | Page 3 of 56
VCC + 0.3
V
V
ADN4605
Parameter
Supply Current
ICC
IDVCC
ITTIA + ITTIB
ITTOA+ ITTOB
Conditions
All outputs enabled, ac-coupled I/O,
200 mV I/O swings (400 mV p-p differential),
PE boost = 0 dB, 50 Ω far-end terminations
Supply Current
ICC
IDVCC
ITTIA + ITTIB
ITTOA + ITTOB
Supply Current
ICC
IDVCC
ITTIA+ ITTIB
ITTOA + ITTOB
THERMAL CHARACTERISTICS
Operating Temperature2
θJA
θJB
θJC
LOGIC CHARACTERISTICS
Input High Voltage Threshold (VIH)
All outputs enabled, ac-coupled I/O,
400 mV I/O swings (800 mV p-p differential),
PE boost = 0 dB, 50 Ω far-end terminations
Min
All outputs enabled, ac-coupled I/O,
400 mV I/O swings (800 mV p-p differential),
PE boost = 6 dB, 50 Ω far-end terminations
Typ
Max
Unit
1320
0.3
11
335
1410
1.1
15
360
mA
mA
mA
mA
1370
0.3
11
665
1460
1.1
15
715
mA
mA
mA
mA
1850
0.3
11
1340
1960
1.1
15
1380
mA
mA
mA
+85
°C
°C/W
°C/W
°C/W
−40
Still air; JEDEC multilayer test board
1 m/s air velocity
1 m/s air velocity
DVCC = 3.3 V
11.6
5.4
0.72
V
0.7 ×
DVCC
Input Low Voltage Threshold (VIL)
DVCC = 3.3 V
Output High Voltage (VOH)
IOH = −3 mA (I2C/SPI mode only)
Output Low Voltage (VOL)
IOL = +3 mA
1
VICM is the input common-mode voltage.
Junction temperature cannot exceed 125°C (see the Absolute Maximum Ratings section).
2
Rev. 0 | Page 4 of 56
0.75 ×
DVCC
VEE
0.25 ×
DVCC
DVCC
V
0.4
V
V
ADN4605
I2C TIMING SPECIFICATIONS
SDA
tf
tLOW
tf
tSU;DAT
tr
tHD;STA
tBUF
tr
tSP
tHD;STA
tHD;DAT
S
tSU;STO
tSU;STA
tHIGH
Sr
P
S
09796-002
SCL
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Specifications
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus Free Time Between a Stop Condition and a Start Condition
Bus Idle Time After a Reset
Reset Pulse Width
Symbol
fSCL
tHD; STA
tSU; STA
tLOW
tHIGH
tHD; DAT
tSU; DAT
tr
tf
tSU; STO
tBUF
Min
0
0.5
0.5
Max
500+
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
ns
ns
ns
1.4
0.6
0.02
0.02
1
1
0.5
1
20
20
300
300
SPI TIMING SPECIFICATIONS
CS
t1
t2
t7
SCLK
DIN
D7
D6
D5
t5
D4
D3
D2
t6
D1
D0
X
X
X
X
X
X
X
t8
t4
DOUT
X
X
X
X
X
X
X
X
D7
D6
X
D5
D4
D3
D2
D1
09796-003
t3
D0
Figure 3. SPI Timing Diagram
Table 3. SPI Timing Specifications
Parameter
SCK Clock Frequency
CS to SCLK Setup Time
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time After SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Hold Time After SCLK Rising Edge
CS to SCLK Hold Time
CS to SDO High Impedance
Reset Pulse Width
Symbol
fSCK
t1
t2
t3
t4
t5
t6
t7
t8
Min
0
30
30
45
10
30
0
45
20
Rev. 0 | Page 5 of 56
Max
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADN4605
PARALLEL MODE SPECIFICATIONS
1
t8
t1
CS
0
t3
t5
1
WE
0
t2
D7:D0
1
A7:A0
0
t4
t6
t7
09796-004
1
UPDATE
0
Figure 4. Parallel Mode Write Cycle
Table 4. Parallel Mode Write Cycle Timing Specifications
Parameter
Chip Select Setup Time
Parallel Data Setup Time
WE Pulse Width
Parallel Data Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Chip Select Hold Time
Reset Pulse Width
1
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Min
0
0
30
25
Limit
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Unit
ns
ns
50
25
40
30
0
20
t6
t1
CS
0
t4
1
t2
RE
0
t3
1
ADDR 2
ADDR 1
A7:A0
0
t5
1
DATA (ADDR 2)
DATA (ADDR 1)
09796-005
D7:D0
0
Figure 5. Parallel Mode Read Cycle
Table 5. Parallel Mode Read Cycle Timing Specifications
Limit
Typ
Parameter
Chip Select Setup Time
Parallel RE Setup to Valid Time
Symbol
t1
t2
Min
0
10
Data Access Time
Address to RE Hold Time
t3
t4
25
25
Data to RE Hold Time
t5
25
ns
Chip Select Hold Time
t6
5
ns
Rev. 0 | Page 6 of 56
50
ns
ns
ADN4605
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
VCC to VEE
DVCC to VEE
VTTIA, VTTIB
VTTOA, VTTOB
Internal Power Dissipation1
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Junction Temperature
1
Rating
3.7 V
3.7 V
VCC + 0.6 V
VCC + 0.6 V
8.4 W
2.0 V
VEE – 0.3 V < VIN < VCC + 0.6 V
−65°C to +125°C
125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Internal power dissipation is for the device in free air.
TA = 27° C; θJA = 11.6°C/W in still air.
Rev. 0 | Page 7 of 56
ADN4605
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
A
VEE
VEE
VEE ON39 OP39 ON37 OP37 ON35 OP35 ON33 OP33 ON31 OP31 ON29 OP29 ON27 OP27 ON25 OP25 ON23 OP23 ON21 OP21 VEE
4
5
25
26
VEE
VEE
A
B
VEE
VEE
VEE
VEE ON38 OP38 ON36 OP36 ON34 OP34 ON32 OP32 ON30 OP30 ON28 OP28 ON26 OP26 ON24 OP24 ON22 OP22 ON20 OP20 VEE
VEE
B
VCC DVCC VEE
VEE
C
VCC VCC
6
7
8
9
10
11
12
VCC VTTOB VTTOB VTTOB VTTOB VCC
13
14
15
16
VCC VTTOB VTTOB VTTOB VCC
17
18
19
20
21
22
VCC VTTOB VTTOB VTTOB VTTOB VCC
23
24
C
VEE
IP0
VEE
D
IP1
IN0
VCC DVCC VCC VCC
E
IN1
IP2
VCC
F
IP3
IN2 VTTIA VEE
VEE VTTIB IP38 IN37 F
G
IN3
IP4 VTTIA VEE
VEE VTTIB IN36 IP37 G
H
IP5
IN4 VTTIA VEE
WE VTTIB IP36 IN35 H
IN5
IP6 VTTIA SPI
K
IP7
IN6
VCC
SER/
PAR
CS
VCC IP34 IN33 K
L
IN7
IP8
VCC
RESET
DATA0
VCC IN32 IP33 L
M
IP9
IN8 VTTIA
ADDR0
DATA1
VTTIB IP32 IN31 M
N
IN9
IP10 VTTIA
ADDR1
DATA2
VTTIB IN30 IP31 N
P
IP11 IN10 VTTIA
ADDR2
DATA3
VTTIB IP30 IN29 P
R
IN11 IP12 VCC
ADDR3
DATA4
VCC IN28 IP29 R
T
IP13 IN12 VCC
ADDR4
DATA5
VCC IP28 IN27 T
U
IN13 IP14 VTTIA
ADDR5
DATA6
VTTIB IN26 IP27 U
V
IP15 IN14 VTTIA
ADDR6
DATA7
VTTIB IP26 IN25 V
W
IN15 IP16 VTTIA
ADDR7
Y
IP17 IN16 VTTIA VEE
VEE VTTIB IP24 IN23 Y
AA
IN17 IP18 VCC
VEE
VEE
VCC IN22 IP23 AA
AB
IP19 IN18 VCC
VEE
VEE
VCC IP22 IN21 AB
AC
IN19 VEE
J
VEE
VEE
VEE
VEE
VCC VCC
VEE
VEE
VEE
VCC VCC
VEE
VEE
VEE
VEE
VCC DVCC VCC
VEE
VEE
I2C/
VEE IN39 D
VCC IN38 IP39 E
RE VTTIB IN34 IP35 J
ADN4605
Top View
VEE VTTIB IN24 IP25 W
VCC DVCC VCC
VCC VEE
VEE
VEE
VEE
VCC
VCC
VCC VTTOA VTTOA VTTOA VCC
VEE
AD
VEE
VEE
VEE
VCC VCC
VCC VTTOA VTTOA VTTOA VTTOA VCC
AE
VEE
VEE
OP0
ON0
OP2
ON2
OP4
ON4
OP6
ON6
OP8
ON8
AF
VEE
VEE
VEE
OP1
ON1
OP3
ON3
OP5
ON5
OP7
ON7
OP9
ON9
1
2
3
4
5
6
7
8
9
10
11
12
13
VEE
VEE
VCC
VCC
VEE
VEE
VEE
VEE
VCC DVCC VCC IN20 IP21 AC
VCC VTTOA VTTOA VTTOA VTTOA VCC
VCC
VEE IP20 VEE
AD
OP10 ON10 OP12 ON12 OP14 ON14 OP16 ON16 OP18 ON18
VEE
VEE
VEE
VEE
AE
OP11 ON11 OP13 ON13 OP15 ON15 OP17 ON17 OP19 ON19
VEE
VEE
VEE
AF
24
25
26
14
15
16
Figure 6. Pin Configuration
Rev. 0 | Page 8 of 56
17
18
19
20
21
22
23
09796-006
3
ADN4605
Table 7. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
Mnemonic
VEE
VEE
VEE
ON39
OP39
ON37
OP37
ON35
OP35
ON33
OP33
ON31
OP31
ON29
OP29
ON27
OP27
ON25
OP25
ON23
OP23
ON21
OP21
VEE
VEE
VEE
VEE
VEE
VEE
VEE
ON38
OP38
ON36
OP36
ON34
OP34
ON32
OP32
ON30
OP30
ON28
OP28
ON26
OP26
ON24
OP24
ON22
OP22
Type
Power
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Negative Supply.
Negative Supply.
Negative Supply.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Rev. 0 | Page 9 of 56
ADN4605
Pin No.
B23
B24
B25
B26
C1
C2
C3
C4
C5
C6
C7
Mnemonic
ON20
OP20
VEE
VEE
VEE
IP0
VEE
VCC
VCC
VCC
VTTOB
Type
Output
Output
Power
Power
Power
Input
Power
Power
Power
Power
Power
C8
VTTOB
Power
C9
VTTOB
Power
C10
VTTOB
Power
C11
C12
C13
VCC
VCC
VTTOB
Power
Power
Power
C14
VTTOB
Power
C15
VTTOB
Power
C16
C17
C18
VCC
VCC
VTTOB
Power
Power
Power
C19
VTTOB
Power
C20
VTTOB
Power
C21
VTTOB
Power
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
VCC
VCC
DVCC
VEE
VEE
IP1
IN0
VCC
DVCC
VCC
VCC
VEE
VEE
VEE
VEE
VCC
VCC
Power
Power
Power
Power
Power
Input
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Description
High Speed Output Complement.
High Speed Output.
Negative Supply.
Negative Supply.
Negative Supply.
High Speed Input.
Negative Supply.
Positive Supply.
Positive Supply.
Positive Supply.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). T The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Positive Supply.
Positive Supply.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Positive Supply.
Positive Supply.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Output Termination Supply (B). The VTTOB pins are normally tied to the
VTTOA pins.
Positive Supply.
Positive Supply.
Digital Positive Supply.
Negative Supply.
Negative Supply.
High Speed Input.
High Speed Input Complement.
Positive Supply.
Digital Positive Supply.
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Positive Supply.
Rev. 0 | Page 10 of 56
ADN4605
Pin No.
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
E2
E3
E4
E23
E24
E25
E26
F1
F2
F3
Mnemonic
VEE
VEE
VEE
VCC
VCC
VEE
VEE
VEE
VEE
VCC
DVCC
VCC
VEE
IN39
IN1
IP2
VCC
VEE
VEE
VCC
IN38
IP39
IP3
IN2
VTTIA
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
F4
F23
F24
VEE
VEE
VTTIB
Power
Power
Power
F25
F26
G1
G2
G3
IP38
IN37
IN3
IP4
VTTIA
Input
Input
Input
Input
Power
G4
G23
G24
VEE
VEE
VTTIB
Power
Power
Power
G25
G26
H1
H2
H3
IN36
IP37
IP5
IN4
VTTIA
Input
Input
Input
Input
Power
H4
H23
VEE
WE/SCL/SCK
Power
Control
H24
VTTIB
Power
Description
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Digital Positive Supply.
Positive Supply.
Negative Supply.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
High Speed Input Complement.
High Speed Input
High Speed Input
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Negative Supply.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Negative Supply.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Parallel control interface: First-Rank Write Strobe (WE) Active Low.
I2C Control Interface: I2C Clock (SCL).
SPI Control Interface: SPI Clock (SCK).
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
Rev. 0 | Page 11 of 56
ADN4605
Pin No.
H25
H26
J1
J2
J3
Mnemonic
IP36
IN35
IN5
IP6
VTTIA
Type
Input
Input
Input
Input
Power
J4
I2C/SPI/UPDATE
Control
J23
RE/SDI
Control
J24
VTTIB
Power
J25
J26
K1
K2
K3
K4
IN34
IP35
IP7
IN6
VCC
SER/PAR
Input
Input
Input
Input
Power
Control
K23
K24
K25
K26
L1
L2
L3
L4
CS
VCC
IP34
IN33
IN7
IP8
VCC
RESET
Control
Power
Input
Input
Input
Input
Power
Control
L23
DATA0/SDA/SDO
Control
L24
L25
L26
M1
M2
M3
VCC
IN32
IP33
IP9
IN8
VTTIA
Power
Input
Input
Input
Input
Power
M4
ADDR0
Control
M23
DATA1/UPDATE
Control
M24
VTTIB
Power
M25
M26
N1
N2
N3
IP32
IN31
IN9
IP10
VTTIA
Input
Input
Input
Input
Power
N4
ADDR1
Control
Description
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
I2C Control Interface Selection (I2C).
SPI Control Interface Selection (SPI) Active Low.
Parallel Control Interface (UPDATE) Active Low.
Parallel Control Interface: Read Strobe (RE) Active Low.
SPI Control Interface: Data Input (SDI) SPI Control.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
Power Supply.
Serial Control Interface Selection (SER).
Parallel Control Interface Selection (PAR) Active Low.
Chip Select Active Low.
Positive Supply.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Positive Supply.
Configuration Registers: Reset (Active Low). This pin is normally pulled
up to DVCC.
Parallel Control Interface: Register Data Bit 0 (DATA0).
I2C Control Interface: Data In (SDA).
SPI Control Interface: Data Out (SDO).
Positive Supply.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 0.
I2C Control Interface: Slave Address Bit 0.
Parallel Control Interface: Register (DATA1). Data Bit 1.
I2C or SPI Serial Control Interface (UPDATE). Active Low.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 1.
I2C Control Interface: Slave Address Bit 1.
Rev. 0 | Page 12 of 56
ADN4605
Pin No.
N23
N24
Mnemonic
DATA2
VTTIB
Type
Control
Power
N25
N26
P1
P2
P3
IN30
IP31
IP11
IN10
VTTIA
Input
Input
Input
Input
Power
P4
ADDR2
Control
P23
P24
DATA3
VTTIB
Control
Power
P25
P26
R1
R2
R3
R4
IP30
IN29
IN11
IP12
VCC
ADDR3
Input
Input
Input
Input
Power
Control
R23
R24
R25
R26
T1
T2
T3
T4
DATA4
VCC
IN28
IP29
IP13
IN12
VCC
ADDR4
Control
Power
Input
Input
Input
Input
Power
Control
T23
T24
T25
T26
U1
U2
U3
DATA5
VCC
IP28
IN27
IN13
IP14
VTTIA
Control
Power
Input
Input
Input
Input
Power
U4
ADDR5
Control
U23
U24
DATA6
VTTIB
Control
Power
U25
U26
V1
V2
V3
IN26
IP27
IP15
IN14
VTTIA
Input
Input
Input
Input
Power
V4
ADDR6
Control
V23
DATA7
Control
Description
Parallel Control Interface: Register Data Bit 2.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 2.
I2C Control Interface: Slave Address Bit 2.
Parallel Control Interface: Register Data Bit 3.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Positive Supply.
Parallel Control Interface: Register Address Bit 3.
I2C Control Interface: Slave Address Bit 3.
Parallel Control Interface: Register Data Bit 4.
Positive Supply.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Positive Supply.
Parallel Control Interface: Register Address Bit 4.
I2C Control Interface: Slave Address Bit 4.
Parallel Control Interface: Register Data Bit 5.
Positive Supply.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 5.
I2C Control Interface: Slave Address Bit 5.
Parallel Control Interface: Register Data Bit 6.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 6.
I2C Control Interface: Slave Address Bit 6.
Parallel Control Interface: Register Data Bit 7.
Rev. 0 | Page 13 of 56
ADN4605
Pin No.
V24
Mnemonic
VTTIB
Type
Power
V25
V26
W1
W2
W3
IP26
IN25
IN15
IP16
VTTIA
Input
Input
Input
Input
Power
W4
ADDR7
Control
W23
W24
VEE
VTTIB
Power
Power
W25
W26
Y1
Y2
Y3
IN24
IP25
IP17
IN16
VTTIA
Input
Input
Input
Input
Power
Y4
Y23
Y24
VEE
VEE
VTTIB
Power
Power
Power
Y25
Y26
AA1
AA2
AA3
AA4
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB23
AB24
AB25
AB26
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
IP24
IN23
IN17
IP18
VCC
VEE
VEE
VCC
IN22
IP23
IP19
IN18
VCC
VEE
VEE
VCC
IP22
IN21
IN19
VEE
VCC
DVCC
VCC
VCC
VEE
VEE
VEE
VEE
Input
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Power
Power
Power
Power
Power
Power
Power
Power
Power
Description
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Parallel Control Interface: Register Address Bit 7.
I2C Control Interface: Slave Address Bit 7.
Negative Supply.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Negative Supply.
Input Termination Supply (B). The VTTOB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
Negative Supply.
Positive Supply.
Digital Positive Supply.
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Rev. 0 | Page 14 of 56
ADN4605
Pin No.
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Mnemonic
VCC
VCC
VEE
VEE
VEE
VCC
VCC
VEE
VEE
VEE
VEE
VCC
DVCC
VCC
IN20
IP21
VEE
VEE
VEE
VCC
VCC
VCC
VTTOA
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Input
Power
Power
Power
Power
Power
Power
Power
AD8
VTTOA
Power
AD9
VTTOA
Power
AD10
VTTOA
Power
AD11
AD12
AD13
VCC
VCC
VTTOA
Power
Power
Power
AD14
VTTOA
Power
AD15
VTTOA
Power
AD16
AD17
AD18
VCC
VCC
VTTOA
Power
Power
Power
AD19
VTTOA
Power
AD20
VTTOA
Power
AD21
VTTOA
Power
AD22
AD23
AD24
AD25
AD26
VCC
VCC
VEE
IP20
VEE
Power
Power
Power
Input
Power
Description
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Digital Positive Supply.
Positive Supply.
High Speed Input Complement.
High Speed Input.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Positive Supply.
Positive Supply.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Positive Supply.
Positive Supply.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Positive Supply.
Positive Supply.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Output Termination Supply (A). The VTTOA pins are normally tied to the
VTTOB pins.
Positive Supply.
Positive Supply.
Negative Supply.
High Speed Input.
Negative Supply.
Rev. 0 | Page 15 of 56
ADN4605
Pin No.
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
Mnemonic
VEE
VEE
OP0
ON0
OP2
ON2
OP4
ON4
OP6
ON6
OP8
ON8
OP10
ON10
OP12
ON12
OP14
ON14
OP16
ON16
OP18
ON18
VEE
VEE
VEE
VEE
VEE
VEE
VEE
OP1
ON1
OP3
ON3
OP5
ON5
OP7
ON7
OP9
ON9
OP11
ON11
OP13
ON13
OP15
ON15
OP17
ON17
OP19
Type
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Negative Supply.
Negative Supply.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Rev. 0 | Page 16 of 56
ADN4605
Pin No.
AF23
AF24
AF25
AF26
Mnemonic
ON19
VEE
VEE
VEE
Type
Output
Power
Power
Power
Description
High Speed Output Complement.
Negative Supply.
Negative Supply.
Negative Supply.
Rev. 0 | Page 17 of 56
ADN4605
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 2.5 V, VTTIx = 2.5 V, VTTOx = 2.5 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, output level (OLEV) = 4 (16 mA), preemphasis (PE) = 0 (0 dB),
equalizer (EQ) = 1 (3 dB), data rate = 4.25 Gbps (PRBS7 data pattern), ac-coupled inputs and outputs, differential input swing = 800 mV p-p,
TA = 25°C, unless otherwise noted.
DATA OUT
2
50Ω CABLES
INPUT
PIN
OUTPUT 2
PIN
50Ω CABLES
2
50Ω
ADN4605
AC-COUPLED
EVALUATION
BOARD
TP1
TP2
HIGH SPEED
SAMPLING
OSCILLOSCOPE
09796-048
PATTERN
GENERATOR
2
09796-034
09796-035
200mV/DIV
200mV/DIV
Figure 7. Standard Test Circuit
0.167UI/DIV
Figure 8. 3.25 Gbps Input Eye (TP1 from Figure 7)
Figure 10. 3.25 Gbps Output Eye (TP2 from Figure 7)
0.167UI/DIV
Figure 11. 4.25 Gbps Output Eye (TP2 from Figure 7)
Figure 9. 4.25 Gbps Input Eye (TP1 from Figure 7)
Rev. 0 | Page 18 of 56
09796-046
0.167UI/DIV
09796-047
200mV/DIV
200mV/DIV
0.167UI/DIV
ADN4605
DATA OUT
2
50Ω CABLES
2
50Ω CABLES
2
2
DIFFERENTIAL
STRIPLINE TRACES
TP1
TP2
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
LENGTHS = 10 INCHES, 20 INCHES,
30 INCHES, 40 INCHES
INPUT OUTPUT 2
PIN
PIN
50Ω CABLES
2
50Ω
ADN4605
AC-COUPLED
EVALUATION
BOARD
TP3
HIGH
SPEED
SAMPLING
OSCILLOSCOPE
09796-049
PATTERN
GENERATOR
FR4 TEST BACKPLANE
Figure 13. 4.25 Gbps Input Eye, 20 Inch FR4 Input Channel
(TP2 from Figure 12)
0.167UI/DIV
09796-038
0.167UI/DIV
09796-040
200mV/DIV
200mV/DIV
Figure 12. Equalization Test Circuit
Figure 14. 4.25 Gbps Input Eye, 40-Inch FR4 Input Channel
(TP2 from Figure 12)
0.167UI/DIV
09796-043
0.167UI/DIV
09796-045
200mV/DIV
200mV/DIV
Figure 15. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, EQ = 12 dB
(TP3 from Figure 12)
Figure 16. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, EQ = 12 dB
(TP3 from Figure 12)
Rev. 0 | Page 19 of 56
ADN4605
DATA OUT
2
50Ω CABLES
2
2
50Ω CABLES
2
50Ω
HIGH
DIFFERENTIAL
SPEED
STRIPLINE TRACES
TP2
TP3
SAMPLING
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
OSCILLOSCOPE
LENGTHS = 10 INCHES, 20 INCHES,
30 INCHES, 40 INCHES
ADN4605
TP1
FR4 TEST BACKPLANE
AC-COUPLED
EVALUATION
BOARD
09796-050
PATTERN
GENERATOR
50Ω CABLES
2
INPUT OUTPUT 2
PIN
PIN
0.167UI/DIV
Figure 20. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, PE = 5.6 dB
(TP3 from Figure 17)
0.167UI/DIV
Figure 19. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 0 dB
(TP3 from Figure 17)
09796-041
0.167UI/DIV
09796-044
200mV/DIV
200mV/DIV
Figure 18. 4.25 Gbps Output Eye, 20-Inch FR4 Output Channel, PE = 0 dB
(TP3 from Figure 17)
09796-036
200mV/DIV
0.167UI/DIV
09796-039
200mV/DIV
Figure 17. Preemphasis Test Circuit
Figure 21. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 9.5 dB
(TP3 from Figure 17)
Rev. 0 | Page 20 of 56
ADN4605
1000
EQ = 3dB
EQ = 6dB
EQ = 12dB
900
800
80
EYE HEIGHT (mV p-p DIFF)
DETERMINISTIC JITTER (ps)
100
60
40
700
600
500
400
300
200
20
0
1
2
3
4
5
DATA RATE (Gbps)
0
09796-033
0
0
3
4
5
Figure 25. Eye Height vs. Data Rate
1000
EQ = 3dB
EQ = 6dB
EQ = 12dB
900
800
80
EYE HEIGHT (mV p-p DIFF)
DETERMINISTIC JITTER (ps)
2
DATA RATE (Gbps)
Figure 22. Deterministic Jitter vs. Data Rate
100
1
09796-030
100
60
40
700
600
500
400
300
200
20
2.50
2.75
3.00
3.25
3.50
3.75
SUPPLY VOLTAGE (V)
0
2.25
09796-024
0
2.25
3.00
3.25
3.50
3.75
Figure 26. Eye Height vs. Supply Voltage
1000
EQ = 3dB
EQ = 6dB
EQ = 12dB
EQ = 3dB
EQ = 6dB
EQ = 12dB
900
800
EYE HEIGHT (mV p-p DIFF)
80
60
40
700
600
500
400
300
200
20
0
–40
–15
10
35
60
TEMPERATURE (°C)
85
0
–40
–15
10
35
60
TEMPERATURE (°C)
Figure 27. Eye Height vs. Temperature
Figure 24. Deterministic Jitter vs. Temperature
Rev. 0 | Page 21 of 56
85
09796-026
100
09796-025
DETERMINISTIC JITTER (ps)
2.75
SUPPLY VOLTAGE (V)
Figure 23. Deterministic Jitter vs. Supply Voltage
100
2.50
09796-027
100
ADN4605
60
0dB
2.2dB
3.5dB
5.4dB
6.0dB
7.4dB
9.5dB
90
DETERMINISTIC JITTER (ps)
50
DETERMINISTIC JITTER (ps)
100
EQ = 3dB
EQ = 6dB
EQ = 12dB
40
30
20
10
80
70
60
50
40
30
20
10
20
30
40
INPUT FR4 TRACE LENGTH (Inches)
0
09796-032
0
90
90
80
80
70
70
60
60
JITTER (ps)
50
40
50
60
70
40
DETERMINISTIC JITTER p-p
20
10
RANDOM JITTER RMS
0.1
1
0
09796-029
0
0.01
INPUT SWING (VDIFF p-p )
RANDOM JITTER RMS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE (V)
09796-028
10
Figure 32. Jitter vs. Input Common-Mode Voltage
Figure 29. Jitter vs. Differential Input Swing
0
VCC = 2.5V
VCC = 3.3V
–5
80
–10
70
–15
LOSS (dB)
60
50
40
–20
–25
–30
30
20
–35
10
–40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TERMINATION VOLTAGE (V)
09796-022
DETERMINISTIC JITTER (ps)
40
50
30
DETERMINISTIC JITTER p-p
20
0
30
–45
100k
6 INCHES
10 INCHES
20 INCHES
40 INCHES
30 INCHES
1M
10M
100M
FREQUENCY (Hz)
Figure 33. S21 Test Traces
Figure 30. Deterministic Jitter vs. Output Termination Voltage (VTTO)
Rev. 0 | Page 22 of 56
1G
10G
09796-017
JITTER (ps)
100
90
20
Figure 31. Deterministic Jitter vs. Output FR4 Channel Length
100
100
10
OUTPUT FR4 CHANNEL LENGTH (Inches)
Figure 28. Deterministic Jitter vs. Input FR4 Channel Length
30
0
09796-031
10
0
ADN4605
140
25000
STANDARD DEVIATION = 0.81ps
120
100
SAMPLES
RISE/FALL TIME (ps)
20000
80
60
15000
10000
40
5000
RISE TIME
FALL TIME
0
20
40
60
80
100
TEMPERATURE (°C)
0
–4.0
–3.7
–3.4
–3.0
–2.7
–2.4
–2.1
–1.8
–1.4
–1.1
–0.8
–0.5
–0.2
0.2
0.5
0.8
1.1
1.4
1.8
2.1
2.4
2.7
3.0
3.4
3.7
4.0
–20
09796-018
0
–40
RANDOM JITTER (ps)
Figure 37. Random Jitter Histogram
1200
1200
1150
1150
1100
1100
PROPAGATION DELAY (ps)
1050
1000
950
900
VCC = 2.5V
VCC = 3.3V
1050
1000
950
900
2.375
2.500
3.300
800
–40
09796-051
800
3.630
SUPPLY VOLTAGE (V)
20
40
60
80
100
10G
Figure 38. Propagation Delay vs. Temperature
5
0
–5
RETURN LOSS (dB)
–10
–15
–20
–25
–30
S22
–35
–40
S11
1080
1100
09796-023
PROPAGATION DELAY (ps)
1040
1060
1000
1020
960
980
920
940
880
900
–45
860
820
840
780
800
740
760
700
720
0
TEMPERATURE (°C)
Figure 35. Propagation Delay vs. Supply Voltage
160
152 PROP DELAY MEAN
922.4ps
144
136
128
120
112
104
96
88
80
72
64
56
48
40
32
24
16
8
0
–20
09796-020
850
850
09796-019
PROPAGATION DELAY (ps)
Figure 34. Rise/Fall Time vs. Temperature
SAMPLES
09796-021
20
Figure 36. Propagation Delay Histogram
–50
10M
100M
1G
FREQUENCY (Hz)
Figure 39. Return Loss (S11, S22)
Rev. 0 | Page 23 of 56
ADN4605
THEORY OF OPERATION
DVCC
INTRODUCTION
The ADN4605 is a 40 × 40, buffered, asynchronous crosspoint
switch that provides input equalization, output preemphasis,
and output level programming capabilities. The receivers
integrate an equalizer that is optimized to compensate for
typical backplane losses. The switch supports multicast and
broadcast operation, allowing the ADN4605 to work in
redundancy and port replication applications.
IP[39:0]
VTTIA,
VTTIB
IN[39:0]
Rx
VCC
40 × 40
SWITCH
MATRIX
EQ
Tx
OP[39:0]
PREEMPHASIS
VTTOA,
VTTOB
ON[39:0]
EQUALIZATION
SETTINGS
CONNECTION
MAP 1
CONNECTION
MAP 0
RESET
SER/PAR
I2C/SPI
(UPDATE)
CS
SCL/SCK/
WE
SDI/RE
PREEMPHASIS
LEVEL
SETTINGS
DATA[0]/
SDA/SDO
DATA[1]
(UPDATE)
DATA[7:2]
PARALLEL/SERIA L CONTROL
LOGIC INTERFACE
ADDR[7:0]
ADN4605
VEE
09796-007
The ADN4605 is configured through either the serial or parallel
control interface. The serial or parallel control interface is
selected using the SER/PAR dedicated control pin. The serial
interface supports both I2C and SPI protocols selected using the
I2C/SPI dedicated control pin. The ADN4605 control pins
function differently depending on which programming
interface is selected, as described in Table 8.
OUTPUT
LEVEL
SETTINGS
Figure 40. Block Diagram
Table 8. Parallel/Serial Interface Pin Control
I2C Mode
(SER/PAR = 1, I2C/SPI = 1)
Parallel Mode
(SER/PAR = 0)
Pin No.
K4
Pin Name
SER/PAR
J4
SPI Mode
(SER/PAR = 1, I2C/SPI = 0)
I2C/SPI/UPDATE
Pin Function
Serial/parallel control interface
selection
Update strobe
Pin Function
Serial/parallel control interface
selection
I2C/SPI control interface selection
Pin Function
Serial/parallel control interface
selection
I2C/SPI control interface selection
H23
WE/SCL/SCK
Parallel write strobe
I2C clock
SPI clock
J23
RE/SDI
Parallel read strobe
N/A
SPI data input
K23
CS
Chip select
N/A
Chip select
L23
M23
DATA0/SDA/SDO
DATA1/UPDATE
Parallel register data bit (LSB)
Parallel register data bits
I2C data input
Update strobe
SPI data output
Update strobe
N23, P23,
R23, T23,
U23, V23
L4
DATA2 to DATA7
Parallel register data bits
N/A
N/A
RESET
Device register reset (active low)
Device register reset (active low)
M4
ADDR0
N/A
N/A
N4, P4, R4,
T4, U4, V4,
W4
ADDR1to
ADDR7
Device register reset (active
low)
Parallel register address bit
(LSB)
Parallel register address bits
I2C LSB device address to I2C MSB
device address
N/A
Rev. 0 | Page 24 of 56
ADN4605
input channel to the specified logic combinations as shown in
Table 9.
RECEIVERS
Input Structure and Input Levels
VCC
The ADN4605 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and a fixed equalizer that is optimized
for operation over long backplane traces. Each receive channel also
provides a positive/negative (P/N) inversion function, which allows
the user to swap the sign of the input signal path to eliminate the
need for board-level crossovers.
VTTI
RP
53Ω
RN
53Ω
R1
210Ω
R3
630Ω
R2
210Ω
R4
630Ω
IPx
EQUALIZER
INx
Equalization
The ADN4605 receiver incorporates a continuous time equalizer
(EQ) that provides up to 12 dB of high frequency boost to compensate up to 40 inches of FR4 at 4.25 Gbps. Each input has two
equalizer control bits. The receiver is disabled by default. The boost
can be set to defined levels by programming the respective address
register bits (Address 0xC0 through Address 0xC9) for the target
600µA
09796-008
600µA
VEE
Figure 41. Simplified Input Circuit
Table 9. Equalization Control Registers
Register
Address
0xC0
Default
0x0
Register Name
Rx EQ Control
(Rx IN 3 to Rx IN 0)
0xC1
0x0
Rx EQ Control
(Rx IN 7 to Rx IN 4)
0xC2
0x0
Rx EQ Control
(Rx IN 11 to Rx IN 8)
0xC3
0x0
Rx EQ Control
(Rx IN 15 to Rx IN 12)
0xC4
0x0
Rx EQ Control
(Rx IN 19 to Rx IN 16)
0xC5
0x0
Rx EQ Control
(Rx IN 23to Rx IN 20)
0xC6
0x0
Rx EQ Control
(Rx IN 27 to Rx IN 24)
Bits
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Bit Name
RXEQIN [3]
RXEQIN [2]
RXEQIN [1]
RXEQIN [0]
RXEQIN [7]
RXEQIN [6]
RXEQIN [5]
RXEQIN [4]
RXEQIN [11]
RXEQIN [10]
RXEQIN [9]
RXEQIN [8]
RXEQIN [15]
RXEQIN [14]
RXEQIN [13]
RXEQIN [12]
RXEQIN [19]
RXEQIN [18]
RXEQIN [17]
RXEQIN [16]
RXEQIN [23]
RXEQIN [22]
RXEQIN [21]
RXEQIN [20]
RXEQIN [27]
RXEQIN [26]
RXEQIN [25]
RXEQIN [24]
Rev. 0 | Page 25 of 56
Functionality Description
00 = Rx disabled (default)
01 = 3 dB boost
10 = 6 dB boost
11 = 12 dB boost
ADN4605
Register
Address
0xC7
Default
0x0
Register Name
Rx EQ Control
(Rx IN 31 to Rx IN 28)
0xC8
0x0
Rx EQ Control
(Rx IN35 to Rx IN 32)
0xC9
0x0
Rx EQ Control
(Rx IN 39 to Rx IN 36)
0xCA
0x0
(Write only)
Rx EQ Control
(Rx IN Broadcast)
Bits
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
1:0
Bit Name
RXEQIN [31]
RXEQIN [30]
RXEQIN [29]
RXEQIN [28]
RXEQIN [35]
RXEQIN [34]
RXEQIN [33]
RXEQIN [32]
RXEQIN [39]
RXEQIN [38]
RXEQIN [37]
RXEQIN [36]
RXEQIN BC
Functionality Description
00 = Rx disabled (default)
01 = 3 dB boost
10 = 6 dB boost
11 = 12 dB boost
POLARITY INVERSION
The P/N inversion is a feature intended to allow the user to implement the equivalent of a board-level crossover in a much smaller area
and without additional via impedance discontinuities that degrade the high frequency integrity of the signal path. The P/N inversion is
available independently for each of the 40 input and output channels, which are controlled by writing to the RXSIGN bit of the RX Sign
control registers (Addresses 0xCB through Address 0xCF) and the TXSIGN bit of the TX control registers (Address 0xA9 through
Address 0xAD).
Table 10. Signal Path Polarity Control
Register
Address
0xCB
Default
0x00
0xCC
0x00
0xCD
0x00
0xCE
0x00
0xCF
0x00
0xA9
0x00
0xAA
0x00
0xAB
0x00
0xAC
0x00
0xAD
0x00
Register Name
RX SIGN
RX IN 07 to RX IN 00
RX SIGN
RX IN 15 to RX IN 08
RX SIGN
RX IN 23 to RX IN 16
RX SIGN
RX IN31 to RX IN 24
RX SIGN
RX IN 39 to RX IN 32
TX SIGN
TX OUT 07 to TX OUT 00
TX SIGN
TX OUT 15 to TX OUT 08
TX SIGN
TX OUT 23 to TX OUT 16
TX SIGN
TX OUT 31 to TX OUT 24
TX SIGN
TX OUT 39 to TX OUT 32
Bits
7: 0
Bit Name
RXSIGN [7]to RXSIGN [0]
7: 0
RXSIGN [15] to RXSIGN [8]
7: 0
RXSIGN[23] to RXSIGN [16]
7: 0
RXSIGN [31] to RXSIGN [24]
7: 0
RXSIGN [39] to RXSIGN [32]
7: 0
TXSIGN [7] to TXSIGN [0]
7: 0
TXSIGN [15] to TXSIGN [8]
7: 0
TXSIGN [23] to TXSIGN [16]
7: 0
TXSIGN [31] to TXSIGN [24]
7: 0
TXSIGN [39] to TXSIGN [32]
Rev. 0 | Page 26 of 56
Functionality Description
Signal path polarity inversion (input/output)
0 = noninvert
1 = invert
ADN4605
Similarly, by default, Map 1 contains the opposite diagonal
connection configuration where Input 0 is connected to
Output 39, Input 1 to Output 38, and so on. Both maps are
read/write accessible registers. The active map is selected by
writing to the XPT Map Table Select register (Address 0x02).
SWITCH CORE
The ADN4605 switch core is a fully nonblocking 40 × 40 array
that allows multicast and broadcast configurations. The configuration of the switch core is programmed through either the
serial or parallel control interface. The crosspoint configuration
map, which controls the connectivity of the switch core, consists
of a double rank register architecture, as shown in Figure 42.
The crosspoint is configured by addressing the register assigned
to the desired output and writing the desired connection data
into the first rank of latches in either Map 0 or Map 1. The
connection data is equivalent to the binary coded value of the
input number. This process is repeated until each of the desired
connections is programmed.
The second rank registers contain the current state of the
crosspoint. The first rank registers contain the next state. Each
entry in the connection map stores six bits per output, which
indicates which of the 40 inputs are connected to a given
output. An entire connectivity matrix can be programmed
at once by passing data from the first rank registers into the
second rank by writing 0x01 to the XPT Update register
(Address 0x01). An external UPDATE pin can also be used to
control the data transfer as shown in Table 8.
In situations where multiple outputs are to be programmed to
a single input, a broadcast command is available. A broadcast
command is issued by writing the binary value of the desired
input to the XPT Broadcast register (Address 0x03). The broadcast is applied to the selected map table.
The current state of the crosspoint connectivity is available
by reading the XPT Status registers (Address 0x54 to Address
0x7B). Register descriptions for Map 0, Map 1, and XPT status
registers are shown in Table 11.
The first rank registers store connection configurations for
the crosspoint. Map 0 is the default map and is located at
Address 0x04 to Address 0x2B. By default, Map 0 contains
a diagonal connection configuration whereby Input 0 is
connected to Output 0, Input 1 to Output 1, Input 2 to
Output 2, and so on.
FIRST RANK REGISTERS
0
XPT MAP 0
OUTPUTS
39
INPUTS
0
SECOND
RANK REGISTERS
XPT CORE
OUTPUTS
39
0
INPUTS
39
REGISTER 0x04 TO REGISTER 0x2B
0
0
XPT MAP 1
OUTPUTS
39
39
REGISTER 0x2C TO REGISTER 0x53
1
MAP TABLE
SELECT
REGISTER 0x02
39
UPDATE
REGISTER 0x01/
EXTERNAL PIN
XPT STATUS READ
REGISTER 0x54 TO REGISTER 0x7B
Figure 42. Crosspoint Connection Map Block Diagram
Rev. 0 | Page 27 of 56
09796-009
0
INPUTS
0
ADN4605
Table 11. XPT Control Registers
Register
Address
0x00
0x01
0x02
0x03
0x04 to 0x2B
Default
0x00
(Write only)
0x00
(Write only)
0x00
Register Name
Software Reset
Bits
0
Bit Name
Software reset
Functionality Description
Reset the ADN4605 registers to default values
XPT Update
0
XPT Update
Updates XPT switch core (active high)
XPT Map Table Select
0
Map Table Select
0x00
(Write only)
0x00 to 0x27
XPT Broadcast
5:0
XPT BCAST [5:0]
0: Map 0 is selected (default)
1: Map 1 is selected
Assigns all output values at once for the selected XPT table map
XPT Map 0
5:0
OUT x [5:0]
Output (x = 0 to 39) connection assignments
5:0
OUT x [5:0]
Output (x = 39 to 0) connection assignments
5:0
OUT x [5:0]
Output (x = 0 to 39) connection status
Control 0 to Control 39
0x2C to 0x53
0x27 to 0x00
0x54 to 0x7B
0x00 to 0x00
XPT Map 1
Control 39 to Control 0
XPT Status
Control 39 to Control 0
RESET
On initial power-up, or at any point in operation, the ADN4605 register set can be restored to the default values by pulling the RESET pin
low according to the control logic timing specifications. During normal operation, however, the RESET pin must be pulled up to DVCC. A
software reset is also available by writing the value 0x01 to the Reset register at Address 0x00. This register is write-only.
Rev. 0 | Page 28 of 56
ADN4605
Table 12 summarizes the absolute output levels and
preemphasis level control settings. The output level control sets
the dc current level, and the preemphasis level control sets the
PE current in the transmitter, as shown in Figure 43. The full
resolution of eight settings is available through the serial or
parallel interface. A single setting can be programmed to all
outputs simultaneously by writing to the TX Lane Control
Broadcast Register (Address 0xA8).
TRANSMITTERS
Output Structure and Output Levels
The ADN4605 transmitter outputs incorporate 50 Ω termination resistors, ESD protection, and output current switches.
Each channel provides independent control of both the absolute
output level and the preemphasis output level. Note that the
choice of output current affects the output common-mode level.
Preemphasis
In addition to the enabled state, the Tx has three possible
disabled states (standby, squelched, and disabled) controlled
by the Tx Drive Control registers (Address 0xB0 to Address
0xB9) shown in Table 13. Disabled is the lowest power-down
state. When squelched, the output voltage at both the P and N
outputs is the common-mode voltage as defined by the output
current settings. Note that the squelch feature is only available
when using a 3.3 V core supply voltage (VCC). In standby, the
output level of both P and N outputs is pulled up to the
termination supply (VTTOA or VTTOB).
Transmission line attenuation can be equalized at the transmitter using preemphasis. The transmit equalizer setting can
be chosen by matching the channel loss to the amount of boost
provided by the preemphasis.
Transmitter preemphasis levels, as well as dc output levels, can
be set through either the serial or parallel control interface.
VCC
ESD
ON-CHIP TERMINATION
VTTOx
V3
VC
RP
50Ω
RN
50Ω
V2
VP
OPx
V1
VN
ONx
Q1
IDC + IPE = IT
VEE
09796-010
Q2
Figure 43. Simplified Tx Output Circuit
Table 12. Preemphasis and Output Level Settings
Register Address
0x80 (Output 0) to 0xA7 (Output 39)
and 0xA8 (Tx Broadcast)
Default
0x40
Register Name
Tx Lane Control Output 0 to Tx
Lane Control Output 39 and Tx
Broadcast
Bits
7
6:4
Bit Name
Reserved
OLEV
Description
0 (Reserve bit)
000: 0 mA
001: 4 mA
010: 8 mA
011: 12 mA
100: 16 mA
101: 20 mA
110: 24 mA
111: (Reserve bit)
Rev. 0 | Page 29 of 56
3
Overdrive
1: overdrive (increases OLEV and
PE currents by 25%)
0: no overdrive
2:0
PE
000: 0 mA
001: 2 mA
010: 3 mA
011: 4 mA
100: 5 mA
101: 6 mA
110: 7 mA
111: 8 mA
ADN4605
Table 13. Transmitter Output Enable State Settings
Register Address
0xB0
Default
0x00
Register Name
Tx Drive Control
Tx3 to Tx0
0xB1
0x00
Tx Drive Control
Tx7 to Tx4
0xB2
0x00
Tx Drive Control
Tx11 to Tx8
0xB3
0x00
Tx Drive Control
Tx15 to Tx12
0xB4
0x00
Tx Drive Control
Tx19 to Tx16
0xB5
0x00
Tx Drive Control
Tx23 to Tx20
0xB6
0x00
Tx Drive Control
Tx27 to Tx24
0xB7
0x00
Tx Drive Control
Tx31 to Tx28
0xB8
0x00
Drive Control
Tx35 to Tx32
0xB9
0x00
Drive Control
Tx39 to Tx36
0xBA
0x00
(Write only)
Tx Drive Control
Bits
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
1:0
Rev. 0 | Page 30 of 56
Bit Name
TXEN [3]
TXEN [2]
TXEN [1]
TXEN [0]
TXEN [7]
TXEN [6]
TXEN [5]
TXEN [4]
TXEN [11]
TXEN [10]
TXEN [9]
TXEN [8]
TXEN [15]
TXEN [14]
TXEN [13]
TXEN [12]
TXEN [19]
TXEN [18]
TXEN [17]
TXEN [16]
TXEN [23]
TXEN [22]
TXEN [21]
TXEN [20]
TXEN [27]
TXEN [26]
TXEN [25]
TXEN [24]
TXEN [31]
TXEN [30]
TXEN [29]
TXEN [28]
TXEN [35]
TXEN [34]
TXEN [33]
TXEN [32]
TXEN [39]
TXEN [38]
TXEN [37]
TXEN [36]
TXENBC [39]
Functionality Description
11: enabled
10: Tx standby
01: Tx squelched
00: Tx disabled (default)
ADN4605
Table 14 provides an example of how the absolute output and
preemphasis level settings determine the amount of high
frequency boost at the Tx output. Note that the OLEV setting
refers to the main tap output current and the PE setting refers to
the delayed tap current.
VTTO
VH-PE
VH-DC
VOCM
VSW-PE
VL-DC
TPE
The preemphasis boost equation follows:
⎛ V
− V SW − DC ⎞
⎟⎟
Gain[dB] = 20 × log 10 ⎜⎜1 + SW − PE
V SW −DC
⎝
⎠
VSW-DC
VL-PE
09796-011
The amount of high frequency boost provided by the transmitter is determined by both the output and preemphasis level
settings.
Figure 44. Signal Level Definitions
(1)
Table 14. Preemphasis Boost and Overshoot vs. Setting Example
PE Setting
0
3
7
7
7
Delayed Tap
Current (mA)
0
4
8
8
8
OLEV Setting
4
5
6
4
3
Main Tap
Current (mA)
16
20
24
16
12
Gain (dB)
0.00
3.52
6.02
9.54
13.98
Overshoot (%)
0.00
50.00
100.00
200.00
400.00
DC Swing
(mV p-p Diff)
800
800
800
400
200
Table 15. Symbol Definitions
Symbol
IDC
IPE
ITTO
VDPP-DC
VDPP-PE
VSW-DC
VSW-PE
∆VOCM_DC-COUPLED
∆VOCM_AC-COUPLED
VOCM
VH-DC
VL-DC
VH-PE
VL-PE
Formula
Programmable
Programmable
IDC + IPE
25 Ω × IDC × 2
25 Ω × ITTO × 2
VDPP-DC/2 = VH-DC – VL-DC
VDPP-PE/2 = VH-PE – VL-PE
25 Ω × ITTO/2
50 Ω × ITTO/2
VTTO − ∆VOCM = (VH-DC + VL-DC)/2
VTTO − ∆VOCM + VDPP-DC/2
VTTO − ∆VOCM − VDPP-DC/2
VTTO − ∆VOCM + VDPP-PE/2
VTTO − ∆VOCM − VDPP-PE/2
Definition
Output current for main tap output level (OLEV)
Output current for PE delayed tap (PE)
Total transmitter output current
Peak-to-peak differential voltage swing of nonpreemphasized waveform
Peak-to-peak differential voltage swing of preemphasized waveform
DC single-ended voltage swing
Preemphasized single-ended voltage swing
Output common-mode shift, dc-coupled outputs
Output common-mode shift, ac-coupled outputs
Output common-mode voltage
DC single-ended output high voltage
DC single-ended output low voltage
Maximum single-ended output voltage
Minimum single-ended output voltage
Rev. 0 | Page 31 of 56
ADN4605
TERMINATION
Register Address 0xD1 (Input 20 to Input 39). The termination
control for the transmitter outputs can be accessed through
Register Address 0xBC (Output 0 to Output 19) and Register
Address 0x BD (Output 20 to Output 39).
The inputs and outputs include integrated 50 Ω termination
resistors. The internal resistors can be disabled for applications that
require external termination resistors. For example, disabling the
integrated 50 Ω termination resistors allow alternative termination
values such as 75 Ω as shown in Figure 45.
Table 16 shows the termination control registers. Each bit
controls the terminations settings for four inputs/outputs.
A Logic 0 enables the terminations for the respective group.
A Logic 1 disables the terminations for the respective group.
The terminations are enabled by default.
Note that the integrated 50 Ω termination resistors are optimal
for high data rate digital signaling. Disabling the terminations
can reduce the overall performance.
The termination control for the receiver inputs can be accessed
through Register Address 0xD0 (Input 0 to Input 19) and
VTTIx
VTTIx
VCC
VTTOx
VTTOx
75Ω
50Ω
50Ω
50Ω
50Ω
50Ω
75Ω
50Ω
50Ω
Rx
CML
ADN4605
75Ω
50Ω
VEE
09796-012
75Ω
Figure 45. 75 Ω to 50 Ω Impedance Translator
Table 16. Termination Control Register
Register
Address
0xBD
Default
0x00
Register Name
Tx Termination Control
Bit
4
3
2
1
0
Bit Name
TXB_TERM
TXB_TERM
TXB_TERM
TXB_TERM
TXB_TERM
Description
Output [39:36] (B side) termination control
Output [35:32] (B side) termination control
Output [31:28] (B side) termination control
Output [27:24] (B side) termination control
Output [23:20] (B side) termination control
0xBC
0x00
Tx Termination Control
4
3
2
1
0
TXA_TERM
TXA_TERM
TXA_TERM
TXA_TERM
TXA_TERM
Output [19:16] (A side) termination control
Output [15:12] (A side) termination control
Output [11:8] (A side) termination control
Output [7:4] (A side) termination control
Output [3:0] (A side) termination control
0xD1
0x00
Rx Termination Control
0xD0
0x00
Rx Termination Control
4
3
2
1
0
4
3
2
1
0
RXB_TERM
RXB_TERM
RXB_TERM
RXB_TERM
RXB_TERM
RXA_TERM
RXA_TERM
RXA_TERM
RXA_TERM
RXA_TERM
Input [39:36] (B side) termination control
Input [35:32] (B side) termination control
Input [31:28] (B side) termination control
Input [27:24] (B side) termination control
Input [23:20] (B side) termination control
Input [19:16] (A side) termination control
Input [15:12] (A side) termination control
Input [11:8] (A side) termination control
Input [7:4] (A side) termination control
Input [3:0] (A side) termination control
Rev. 0 | Page 32 of 56
Functionality
0 = terminations enabled
1= terminations disabled
ADN4605
2.
I2C SERIAL CONTROL INTERFACE
The ADN4605 register set is controlled through a 2-wire I2C
interface. To access the I2C serial interface, both the SER/PAR
line and I2C/SPI lines must be held at logic high. The ADN4605
acts only as an I2C slave device. Therefore, the I2C bus in the
system needs to include an I2C master to configure the
ADN4605 and other I2C devices that may be on the bus.
3.
4.
5.
6.
7.
2
The ADN4605 I C interface can be run in the standard
(100 kHz) and fast (400 kHz) modes. The SDA line only
changes value when the SCL pin is low with two exceptions.
To indicate the beginning or continuation of a transfer, the
SDA pin is driven low while the SCL pin is high; to indicate
the end of a transfer, the SDA line is driven high while the
SCL line is high. Therefore, it is important to control the
SCL clock to toggle only when the SDA line is stable unless
indicating a start, repeated start, or stop condition. To establish
I2C communication with the ADN4605, parallel address lines
(ADDR[7:1]) need to be configured to the user-assigned I2C
device address as shown in Table 17.
8.
9.
Table 17. Example of I2C Device Address Assignment
A6
0
0
0
0
A5
0
0
0
0
A4
1
1
1
1
A3
0
0
0
0
A2
0
0
1
1
A1
0
1
0
1
A0
X
X
X
X
I2C Device Address
0x90
0x92
0x94
0x96
I2C DATA WRITE
The ADN4605 write process is shown in Figure 46. The SCL
signal is shown along with a general write operation and a
specific example. In the example, Data 0x4B is written to
Address 0x6D of an ADN4605 part with a part address of 0x92.
The ADN4605 device address selections are more flexible than
shown. It is important to note that the SDA line only changes
when the SCL line is low, except for the case of sending a start,
stop, or repeated start condition, Step 1 and Step 9 in this case.
To write data to the ADN4605 register set, a microcontroller, or
any other I2C master, must send the appropriate control signals
to the ADN4605 slave device. The steps to be followed are listed
below; the signals are controlled by the I2C master unless otherwise specified. A diagram of the procedure is shown in Figure 46.
1.
Send a start condition (while holding the SCL line high,
pull the SDA line low).
SCL
SDA
START
b10010
ADDR R/W ACK
[1:0]
REGISTER ADDR
ACK
DATA
ACK
STOP
SDA
EXAMPLE
1
2
2
3
4
5
2
Figure 46. I C Write Diagram
Rev. 0 | Page 33 of 56
6
7
8
9a
09796-013
A7
1
1
1
1
Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
Send the write indicator bit (0).
Wait for the ADN4605 to acknowledge the request.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
Wait for the ADN4605 to acknowledge the request.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
Wait for the ADN4605 to acknowledge the request.
Do one or more of the following:
a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
b. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I2C Data
Write section) to perform a write.
c. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
d. Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
ADN4605
I2C DATA READ
12. Acknowledge the data.
To read data from the ADN4605 register set, a microcontroller,
or any other I2C master needs to send the appropriate control
signals to the ADN4605 slave device. The steps are listed below;
the signals are controlled by the I2C master unless otherwise
specified. A diagram of the procedure is shown in Figure 47.
13. Do one or more of the following:
a.
Send a stop condition (while holding the SCL line high
pull the SDA line high) and release control of the bus.
b.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I2C Data
Write section) to perform a write.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.
1. Send a start condition (while holding the SCL line high, pull
the SDA line low).
2. Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
c.
3. Send the write indicator bit (0).
d.
4. Wait for the ADN4605 to acknowledge the request.
5. Send the register address (eight bits) from which data is
to be read. This transfer should be MSB first. The register
address is kept in memory in the ADN4605 until the part
is reset or the register address is written over with the same
procedure (Step 1 to Step 6).
The ADN4605 read process is shown in Figure 47. The SCL
signal is shown along with a general read operation and a
specific example. In the example, Data 0x49 is read from
Address 0x6D of an ADN4605 part with a part address of 0x92.
The part address is seven bits wide and is composed of the
ADN4605 (ADDR[7:1]). In this example, the ADDR{1:0] bits
are set to b01.
6. Wait for the ADN4605 to acknowledge the request.
7. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low).
8. Send the ADN4605 part address (seven bits) whose bits are
controlled by the input pins ADDR[7:1]. This transfer
should be MSB first.
In Figure 47, the corresponding step number is visible in the
circle under the waveform. The SCL line is driven by the I2C
master and never by the ADN4605 slave. As for the SDA line,
the data in the shaded polygons is driven by the ADN4605,
whereas the data in the nonshaded polygons is driven by the I2C
master. The end phase case shown is that of Step13a.
9. Send the read indicator bit (1).
10. Wait for the ADN4605 to acknowledge the request.
11. The ADN4605 then serially transfers the data (eight bits)
held in the register indicated by the address set in Step 5.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, as in Step 1, Step 7, and Step 13. In Figure 47, A is
the same as ACK. Equally, Sr represents a repeated start where
the SDA line is brought high before SCL is raised. SDA is then
dropped while SCL is still high.
SCL
SDA START
b10010
ADDR R/
[1:0] W
A
REGISTER ADDR
A
Sr
5
6
7
b10010
ADDR
[1:0]
R/ A
W
DATA
A
STOP
11
12
13a
1
2
2
3
4
8
Figure 47. I2C Read Diagram
Rev. 0 | Page 34 of 56
8
9
10
09796-014
SDA
EXAMPLE
ADN4605
SPI SERIAL CONTROL INTERFACE
The SPI serial interface of the ADN4605 consists of four wires:
CS, SCK, SDI, and SDO. In order to access the SPI interface the
SER/PAR line must be held at logic high and the I2C/SPI line
must be held at logic low. The CS pin is used to select the device
when more than one device is connected to the serial clock and
data lines and must be held at logic low to enable write/read
capability to the device when in SPI control mode.
The SCK is used to clock data in and out of the part. The SDI
line is used to write to the registers, and the SDO line is used to
read data back from the registers. Data on SDI line is clocked on
the rising edge of SCK. Data on SDO changes on the falling
edge of SCK. The recommended pull-up resistor value is
between 500 Ω and 1 kΩ. Strong pull-ups are needed when
serial clock speeds that are close to the maximum limit are used
or when the SPI interface lines are experiencing large capacitive
loading. Larger resistor values can be used for pull-up resistors
when the serial clock speed is reduced.
The part operates in a slave mode and requires an externally
applied serial clock to the SCK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
There are two types of serial operations, a read and a write.
Command words are used to distinguish between a read and a
write operation as shown in Table 18.
Table 18. SPI Command Words
Write Command
Read Command
0x02 (0000 0010)
0x03 (0000 0011)
Write Operation
Figure 48 shows the diagram for a write operation to the
ADN4605. Data is clocked into the registers on the rising edge
of SCK. When the CS line is high, the SDI and SDO lines are in
three-state mode. Only when the CS goes from a high to a low
does the part accept any data on the SDI line. The 8-bit write
command must precede the register address byte. The register
address byte is then followed by the data byte as shown in
Figure 48.
To allow continuous writes, the address pointer register autoincrements by one without having to load the address pointer
register each time. Subsequent data bytes are written into
sequential registers. Note that not all registers in the 256-byte
address space exist and not all registers are writable. Zeroes
should be entered for nonexistent address fields when implementing a continuous write operation. Address space 0xE0 to
Address 0xFF is reserved and should not be overwritten.
Read Operation
To read back from a register, first send the read command
followed by the desired register address. Subsequent clock
cycles, with CS asserted low, stream data starting from the
desired register address onto SDO, MSB first. SDO changes on
the falling edge of SCK. Multiple data reads are possible in SPI
interface mode because the address pointer register is autoincremented.
Rev. 0 | Page 35 of 56
ADN4605
CS
1
8
1
8
SCK
D7
D6
X
SDO
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
D7
X
D6
X
D5
X
D4
X
D3
D2
X
X
D1
X
D0
X
X
START
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCK (CONTINUED)
SDI (CONTINUED)
SDO (CONTINUED)
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
X
STOP
DATA BYTE
Figure 48. SPI–Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
Rev. 0 | Page 36 of 56
09796-015
SDI
ADN4605
CS
1
8
1
8
SCK
D7
D6
X
SDO
D5
X
D4
X
D3
X
D2
X
D1
X
D0
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
X
X
START
READ COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCK (CONTINUED)
SDI (CONTINUED)
SDO (CONTINUED)
X
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
D0
STOP
DATA BYTE
Figure 49. SPI–Reading a Single Byte of Data from a Selected Register
Rev. 0 | Page 37 of 56
09796-016
SDI
ADN4605
PARALLEL CONTROL INTERFACE
The parallel control interface of the ADN4605 consists of
nineteen wires: ADDR[7:0], DATA[7:0], WE, RE, and CS. To
access the parallel control interface, the SER/PAR line must
be held at logic low. The CS line is used to select a device when
one or more devices share the same address and data lines. The
CS line must be held at logic low to enable write/read capability
to the device when in parallel control mode.
ADDRESS INPUTS: ADDR[7:0]
WRITE OPERATION
For first rank write enable, forcing this pin to logic low allows
the data on the DATA[7:0] lines to be stored in the first rank
latch for the register specified by the address lines (ADDR[7:0]).
The data is latched during the high-to-low transition of the
write enable pulse. The WE line must be returned to a logic
high state after the write cycle to avoid overwriting the first
rank data.
READ OPERATION
The binary coded address applied to the address lines
determines which device registers are being programmed or
read back.
DATA INPUTS/OUTPUTS: DATA[7:0]
In write mode, the binary encoded data applied to the data lines
(DATA[7:0]) determine the configuration setting of the register
specified by the address lines (ADDR[7:0]).
In read mode, data lines (DATA[7:0]) are low impedance
outputs indicating the data byte stored in the register specified
by the address lines (ADDR[7:0]). Note that some registers are
write only and may not be read from (see Table 19) The readback drivers are designed to drive high impedances only
(>1 kΩ).
For second rank read enable, forcing this line to a logic low state
enables the output drivers on the bidirectional data lines
(DATA[7:0]), placing the logic in readback mode of operation.
The register selected to read from is determined by the binary
encoded data configured on the address lines (ADDR[7:0]).
When the read enable line is at a logic low, the data stored in
the specified register will be latched onto the data lines
(DATA[7:0]). The RE line is higher priority than the WE line;
therefore, first rank programming is not possible while in
readback mode. Note that some registers are defined as write
only and are not accessible in readback mode (see Table 19).
Rev. 0 | Page 38 of 56
ADN4605
REGISTER MAP
In the Register Map, when settings are provided in the Description column for the first bit, note that these settings apply to all bits with
the same function.
Table 19. Register Map
Address: Channel
0x00
0x02
Default
0x00
Write only
0x0
Write only
0x00
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
Write only
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x01
Register Name
Software Reset
Bits
0
Bit Name
Reset
Description
Software reset
XPT Update
0
XPT Update
Updates crosspoint switch core
XPT Map Table
Select
XPT Broadcast
XPT Map 0 Control 0
XPT Map 0 Control 1
XPT Map 0 Control 2
XPT Map 0 Control 3
XPT Map 0 Control 4
XPT Map 0 Control 5
XPT Map 0 Control 6
XPT Map 0 Control 7
XPT Map 0 Control 8
XPT Map 0 Control 9
XPT Map 0 Control 10
XPT Map 0 Control 11
XPT Map 0 Control 12
XPT Map 0 Control 13
XPT Map 0 Control 14
XPT Map 0 Control 15
XPT Map 0 Control 16
XPT Map 0 Control 17
XPT Map 0 Control 18
XPT Map 0 Control 19
XPT Map 0 Control 20
XPT Map 0 Control 21
XPT Map 0 Control 22
XPT Map 0 Control 23
XPT Map 0 Control 24
XPT Map 0 Control 25
XPT Map 0 Control 26
XPT Map 0 Control 27
XPT Map 0 Control 28
XPT Map 0 Control 29
XPT Map 0 Control 30
XPT Map 0 Control 31
XPT Map 0 Control 32
XPT Map 0 Control 33
XPT Map 0 Control 34
XPT Map 0 Control 35
XPT Map 0 Control 36
XPT Map 0 Control 37
XPT Map 0 Control 38
XPT Map 0 Control 39
0
Map Table Select
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
XPT BCAST [5:0]
OUT 0 [5:0]
OUT 1 [5:0]
OUT 2 [5:0]
OUT 3 [5:0]
OUT 4 [5:0]
OUT 5 [5:0]
OUT 6 [5:0]
OUT 7 [5:0]
OUT 8 [5:0]
OUT 9 [5:0]
OUT 10 [5:0]
OUT 11 [5:0]
OUT 12 [5:0]
OUT 13 [5:0]
OUT 14 [5:0]
OUT 15 [5:0]
OUT 16 [5:0]
OUT 17 [5:0]
OUT 18 [5:0]
OUT 19 [5:0]
OUT 20 [5:0]
OUT 21 [5:0]
OUT 22 [5:0]
OUT 23 [5:0]
OUT 24 [5:0]
OUT 25 [5:0]
OUT 26 [5:0]
OUT 27 [5:0]
OUT 28 [5:0]
OUT 29 [5:0]
OUT 30 [5:0]
OUT 31 [5:0]
OUT 32 [5:0]
OUT 33 [5:0]
OUT 34 [5:0]
OUT 35 [5:0]
OUT 36 [5:0]
OUT 37[5:0]
OUT 38 [5:0]
OUT 39 [5:0]
0: Map 0 is selected
1: Map 1 is selected
All outputs connection assignment
Output 0 connection assignment
Output 1 connection assignment
Output 2 connection assignment
Output 3 connection assignment
Output 4 connection assignment
Output 5 connection assignment
Output 6 connection assignment
Output 7 connection assignment
Output 8 connection assignment
Output 9 connection assignment
Output 10 connection assignment
Output 11 connection assignment
Output 12 connection assignment
Output 13 connection assignment
Output 14 connection assignment
Output 15 connection assignment
Output 16 connection assignment
Output 17 connection assignment
Output 18 connection assignment
Output 19 connection assignment
Output 20 connection assignment
Output 21 connection assignment
Output 22 connection assignment
Output 23 connection assignment
Output 24 connection assignment
Output 25 connection assignment
Output 26 connection assignment
Output 27 connection assignment
Output 28 connection assignment
Output 29 connection assignment
Output 30 connection assignment
Output 31 connection assignment
Output 32 connection assignment
Output 33 connection assignment
Output 34 connection assignment
Output 35 connection assignment
Output 36 connection assignment
Output 37 connection assignment
Output 38 connection assignment
Output 39 connection assignment
Rev. 0 | Page 39 of 56
ADN4605
Address: Channel
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
Default
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Register Name
XPT Map 1 Control 0
XPT Map 1 Control 1
XPT Map 1 Control 2
XPT Map 1 Control 3
XPT Map 1 Control 4
XPT Map 1 Control 5
XPT Map 1 Control 6
XPT Map 1 Control 7
XPT Map 1 Control 8
XPT Map 1 Control 9
XPT Map 1 Control 10
XPT Map 1 Control 11
XPT Map 1 Control 12
XPT Map 1 Control 13
XPT Map 1 Control 14
XPT Map 1 Control 15
XPT Map 1 Control 16
XPT Map 1 Control 17
XPT Map 1 Control 18
XPT Map 1 Control 19
XPT Map 1 Control 20
XPT Map 1 Control 21
XPT Map 1 Control 22
XPT Map 1 Control 23
XPT Map 1 Control 24
XPT Map 1 Control 25
XPT Map 1 Control 26
XPT Map 1 Control 27
XPT Map 1 Control 28
XPT Map 1 Control 29
XPT Map 1 Control 30
XPT Map 1 Control 31
XPT Map 1 Control 32
XPT Map 1 Control 33
XPT Map 1 Control 34
XPT Map 1 Control 35
XPT Map 1 Control 36
XPT Map 1 Control 37
XPT Map 1 Control 38
XPT Map 1 Control 39
XPT Status 0
XPT Status 1
XPT Status 2
XPT Status 3
XPT Status 4
XPT Status 5
XPT Status 6
XPT Status 7
XPT Status 8
XPT Status 9
XPT Status 10
XPT Status 11
XPT Status 12
Bits
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
Bit Name
OUT 0 [5:0]
OUT 1 [5:0]
OUT 2 [5:0]
OUT 3 [5:0]
OUT 4 [5:0]
OUT 5 [5:0]
OUT 6 [5:0]
OUT 7 [5:0]
OUT 8 [5:0]
OUT 9 [5:0]
OUT 10 [5:0]
OUT 11 [5:0]
OUT 12 [5:0]
OUT 13 [5:0]
OUT 14 [5:0]
OUT 15 [5:0]
OUT 16 [5:0]
OUT 17 [5:0]
OUT 18 [5:0]
OUT 19 [5:0]
OUT 20 [5:0]
OUT 21 [5:0]
OUT 22 [5:0]
OUT 23 [5:0]
OUT 24 [5:0]
OUT 25 [5:0]
OUT 26 [5:0]
OUT 27 [5:0]
OUT 28 [5:0]
OUT 29 [5:0]
OUT 30 [5:0]
OUT 31 [5:0]
OUT 32 [5:0]
OUT 33 [5:0]
OUT 34 [5:0]
OUT 35 [5:0]
OUT 36 [5:0]
OUT 37[5:0]
OUT 38 [5:0]
OUT 39 [5:0]
OUT 0 [5:0]
OUT 1 [5:0]
OUT 2 [5:0]
OUT 3 [5:0]
OUT 4 [5:0]
OUT 5 [5:0]
OUT 6 [5:0]
OUT 7 [5:0]
OUT 8 [5:0]
OUT 9 [5:0]
OUT 10 [5:0]
OUT 11 [5:0]
OUT 12 [5:0]
Rev. 0 | Page 40 of 56
Description
Output 0 connection assignment
Output 1 connection assignment
Output 2 connection assignment
Output 3 connection assignment
Output 4 connection assignment
Output 5 connection assignment
Output 6 connection assignment
Output 7 connection assignment
Output 8 connection assignment
Output 9 connection assignment
Output 10 connection assignment
Output 11 connection assignment
Output 12 connection assignment
Output 13 connection assignment
Output 14 connection assignment
Output 15 connection assignment
Output 16 connection assignment
Output 17 connection assignment
Output 18 connection assignment
Output 19 connection assignment
Output 20 connection assignment
Output 21 connection assignment
Output 22 connection assignment
Output 23 connection assignment
Output 24 connection assignment
Output 25 connection assignment
Output 26 connection assignment
Output 27 connection assignment
Output 28 connection assignment
Output 29 connection assignment
Output 30 connection assignment
Output 31 connection assignment
Output 32 connection assignment
Output 33 connection assignment
Output 34 connection assignment
Output 35 connection assignment
Output 36 connection assignment
Output 37 connection assignment
Output 38 connection assignment
Output 39 connection assignment
Output 0 connection status
Output 1 connection status
Output 2 connection status
Output 3 connection status
Output 4 connection status
Output 5 connection status
Output 6 connection status
Output 7 connection status
Output 8 connection status
Output 9 connection status
Output 10 connection status
Output 11 connection status
Output 12 connection status
ADN4605
Address: Channel
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7D
0x80: Output 0
0x81: Output 1
0x82: Output 2
0x83: Output 3
0x84: Output 4
0x85: Output 5
0x86: Output 6
0x87: Output 7
0x88: Output 8
0x89: Output 9
0x8A: Output 10
0x8B: Output 11
0x8C: Output 12
0x8D: Output 13
0x8E Output 14
0x8F: Output 15
0x90: Output 16
0x91: Output 17
0x92: Output 18
0x93: Output 19
0x94: Output 20
0x95: Output 21
0x96: Output 22
0x97: Output 23
0x98: Output 24
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
Register Name
XPT Status 13
XPT Status 14
XPT Status 15
XPT Status 16
XPT Status 17
XPT Status 18
XPT Status 19
XPT Status 20
XPT Status 21
XPT Status 22
XPT Status 23
XPT Status 24
XPT Status 25
XPT Status 26
XPT Status 27
XPT Status 28
XPT Status 29
XPT Status 30
XPT Status 31
XPT Status 32
XPT Status 33
XPT Status 34
XPT Status 35
XPT Status 36
XPT Status 37
XPT Status 38
XPT Status 39
XPT Headroom
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Bits
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
5:0
0
7
6:4
Bit Name
OUT 13 [5:0]
OUT 14 [5:0]
OUT 15 [5:0]
OUT 16 [5:0]
OUT 17 [5:0]
OUT 18 [5:0]
OUT 19 [5:0]
OUT 20 [5:0]
OUT 21 [5:0]
OUT 22 [5:0]
OUT 23 [5:0]
OUT 24 [5:0]
OUT 25 [5:0]
OUT 26 [5:0]
OUT 27 [5:0]
OUT 28 [5:0]
OUT 29 [5:0]
OUT 30 [5:0]
OUT 31 [5:0]
OUT 32 [5:0]
OUT 33 [5:0]
OUT 34 [5:0]
OUT 35 [5:0]
OUT 36 [5:0]
OUT 37[5:0]
OUT 38 [5:0]
OUT 39 [5:0]
XPT_HDROOM
Reserved
OLEV [2:0]
Description
Output 13 connection status
Output 14 connection status
Output 15 connection status
Output 16 connection status
Output 17 connection status
Output 18 connection status
Output 19 connection status
Output 20 connection status
Output 21 connection status
Output 22 connection status
Output 23 connection status
Output 24 connection status
Output 25 connection status
Output 26 connection status
Output 27 connection status
Output 28 connection status
Output 29 connection status
Output 30 connection status
Output 31 connection status
Output 32 connection status
Output 33 connection status
Output 34 connection status
Output 35 connection status
Output 36 connection status
Output 37 connection status
Output 38 connection status
Output 39 connection status
0 = disabled, 1 = enabled (required when VCC > 2.7 V)
0 (Reserve bit)
000: 0 mA
001: 4 mA
010: 8 mA
011: 12 mA
100: 16 mA (default)
101: 20 mA
110: 24 mA
111: (Reserve bit)
3
Overdrive
1: overdrive (increases OLEV and PE currents by 25%)
0: no overdrive (default)
2:0
PE [2:0]
000: 0 mA (default)
001: 2 mA
010: 3 mA
011: 4 mA
100: 5 mA
101: 6 mA
110: 7 mA
111: 8 mA
Rev. 0 | Page 41 of 56
ADN4605
Address: Channel
0x99: Output 25
0x9A: Output 26
0x9B: Output 27
0x9C: Output 28
0x9D: Output 29
0x9E: Output 30
0x9F: Output 31
0xA0: Output 32
0xA1: Output 33
0xA2: Output 34
0xA3: Output 35
0xA4: Output 36
0xA5: Output 37
0xA6: Output 38
0xA7: Output 39
0xA8: Tx Broadcast
0xA9
Default
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x40
0x0
Register Name
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Lane Control
Tx Sign Control
0xAA
0x0
Tx Sign Control
0xAB
0x0
Tx Sign Control
0xAC
0x0
Tx Sign Control
Bits
Bit Name
Description
7
TXSIGN [7]
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TXSIGN [6]
TXSIGN [5]
TXSIGN [4]
TXSIGN [3]
TXSIGN [2]
TXSIGN [1]
TXSIGN [0]
TXSIGN [15]
TXSIGN [14]
TXSIGN [13]
TXSIGN [12]
TXSIGN [11]
TXSIGN [10]
TXSIGN [9]
TXSIGN [8]
TXSIGN [23]
TXSIGN [22]
TXSIGN [21]
TXSIGN [20]
TXSIGN [19]
TXSIGN [18]
TXSIGN [17]
TXSIGN [16]
TXSIGN [31]
TXSIGN [30]
TXSIGN [29]
TXSIGN [28]
TXSIGN [27]
TXSIGN [26]
TXSIGN [25]
TXSIGN [24]
Signal path polarity inversion Output 7
0 = noninverting
1 = inverting
Signal path polarity inversion Output 6
Signal path polarity inversion Output 5
Signal path polarity inversion Output 4
Signal path polarity inversion Output 3
Signal path polarity inversion Output 2
Signal path polarity inversion Output 1
Signal path polarity inversion Output 0
Signal path polarity inversion Output 15
Signal path polarity inversion Output 14
Signal path polarity inversion Output 13
Signal path polarity inversion Output 12
Signal path polarity inversion Output 11
Signal path polarity inversion Output 10
Signal path polarity inversion Output 9
Signal path polarity inversion Output 8
Signal path polarity inversion Output 23
Signal path polarity inversion Output 22
Signal path polarity inversion Output 21
Signal path polarity inversion Output 20
Signal path polarity inversion Output 19
Signal path polarity inversion Output 18
Signal path polarity inversion Output 17
Signal path polarity inversion Output 16
Signal path polarity inversion Output 31
Signal path polarity inversion Output 30
Signal path polarity inversion Output 29
Signal path polarity inversion Output 28
Signal path polarity inversion Output 27
Signal path polarity inversion Output 26
Signal path polarity inversion Output 25
Signal path polarity inversion Output 24
Rev. 0 | Page 42 of 56
ADN4605
Address: Channel
0xAD
Default
0x0
Register Name
Tx Sign Control
0xB0
0x0
0xB1
0xB2
0xB3
0xB4
0x0
0x0
0x0
0x0
Tx Drive Control
Bits
7
6
5
4
3
2
1
0
7:6
Bit Name
TXSIGN [39]
TXSIGN [38]
TXSIGN [37]
TXSIGN [36]
TXSIGN [35]
TXSIGN [34]
TXSIGN [33]
TXSIGN [32]
TXEN [3]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [2]
TXEN [1]
TXEN [0]
TXEN [7]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [6]
TXEN [5]
TXEN [4]
TXEN [11]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [10]
TXEN [9]
TXEN [8]
TXEN [15]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [14]
TXEN [13]
TXEN [12]
TXEN [19]
5:4
3:2
1:0
TXEN [18]
TXEN [17]
TXEN [16]
Rev. 0 | Page 43 of 56
Description
Signal path polarity inversion Output 39
Signal path polarity inversion Output 38
Signal path polarity inversion Output 37
Signal path polarity inversion Output 36
Signal path polarity inversion Output 35
Signal path polarity inversion Output 34
Signal path polarity inversion Output 33
Signal path polarity inversion Output 32
Tx enable state Output 3
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 2
Tx enable state Output 1
Tx enable state Output 0
Tx enable state Output 7
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 6
Tx enable state Output 5
Tx enable state Output 4
Tx enable state Output 11
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 10
Tx enable state Output 9
Tx enable state Output 8
Tx enable state Output 15
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 14
Tx enable state Output 13
Tx enable state Output 12
Tx enable state Output 19
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 18
Tx enable state Output 17
Tx enable state Output 16
ADN4605
Address: Channel
0xB5
0xB6
0xB7
0xB8
0xB9
Default
0x0
0x0
0x0
0x0
0x0
Register Name
Tx Drive Control
Bits
7:6
Bit Name
TXEN [23]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [22]
TXEN [21]
TXEN [20]
TXEN [27]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [26]
TXEN [25]
TXEN [24]
TXEN [31]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [30]
TXEN [29]
TXEN [28]
TXEN [35]
Tx Drive Control
5:4
3:2
1:0
7:6
TXEN [34]
TXEN [33]
TXEN [32]
TXEN [39]
TXEN [38]
TXEN [37]
TXEN [36]
TXENBC [39]
TX_HDROOM
0xBA
Write Only
Tx Drive Control
5:4
3:2
1:0
7:6
0xBB
0x0
Tx Headroom
0
Rev. 0 | Page 44 of 56
Description
Tx enable state Output 23
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 22
Tx enable state Output 21
Tx enable state Output 20
Tx enable state Output 27
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 26
Tx enable state Output 25
Tx enable state Output 24
Tx enable state Output 31
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 30
Tx enable state Output 29
Tx enable state Output 28
Tx enable state Output 35
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 34
Tx enable state Output 33
Tx enable state Output 32
Tx enable state Output 39
11 = enabled
10 = standby
01 = squelch
00 = disabled
Tx enable state Output 38
Tx enable state Output 37
Tx enable state Output 36
Tx enable state broadcast
11 = enabled
10 = standby
01 = squelch
00 = disabled
0 = disabled, 1 = enabled (required when VCC > 2.7 V)
ADN4605
Address: Channel
0xBC
0xBD
0xC0
0xC1
0xC2
0xC3
Default
0x0
0x0
0x0
0x0
0x0
0x0
Register Name
Tx Termination
Control
Bits
4
Bit Name
TXA_TERM [19:16]
3
2
1
0
4
TXA_TERM [15:12]
TXA_TERM [11:8]
TXA_TERM [7:4]
TXA_TERM [3:0]
TXB_TERM [39:36]
3
2
1
0
TXB_TERM [35:32]
TXB_TERM [31:28]
TXB_TERM [27:24]
TXB_TERM [23:20]
Rx EQ Control
7:6
RXEQIN [3]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [2]
RXEQIN [1]
RXEQIN [0]
RXEQIN [7]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [6]
RXEQIN [5]
RXEQIN [4]
RXEQIN [11]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [10]
RXEQIN [9]
RXEQIN [8]
RXEQIN [15]
5:4
3:2
1:0
RXEQIN [14]
RXEQIN [13]
RXEQIN [12]
Tx Termination
Control
Rev. 0 | Page 45 of 56
Description
Output[19:16] (B side) termination control
0: terminations enabled
1: terminations disabled
Output[15:12] (B side) termination control
Output[11:8] (B side) termination control
Output[7:4] (B side) termination control
Output[3:0] (B side) termination control
Output[39:36] (B side) termination control
0: terminations enabled
1: terminations disabled
Output[35:32] (B side) termination control
Output[31:28] (B side) termination control
Output[27:24] (B side) termination control
Output[23:20] (B side) termination control
Equalizer boost control for Input 3
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 2
Equalizer boost control for Input 1
Equalizer boost control for Input 0
Equalizer boost control for Input 7
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 6
Equalizer boost control for Input 5
Equalizer boost control for Input 4
Equalizer boost control for Input 11
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 10
Equalizer boost control for Input 9
Equalizer boost control for Input 8
Equalizer boost control for Input 15
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 14
Equalizer boost control for Input 13
Equalizer boost control for Input 12
ADN4605
Address: Channel
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
Default
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Register Name
Rx EQ Control
Bits
7:6
Bit Name
RXEQIN [19]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [18]
RXEQIN [17]
RXEQIN [16]
RXEQIN [23]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [22]
RXEQIN [21]
RXEQIN [20]
RXEQIN [27]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [26]
RXEQIN [25]
RXEQIN [24]
RXEQIN [31]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [30]
RXEQIN [29]
RXEQIN [28]
RXEQIN [35]
Rx EQ Control
5:4
3:2
1:0
7:6
RXEQIN [34]
RXEQIN [33]
RXEQIN [32]
RXEQIN [39]
Rx EQ Control
5:4
3:2
1:0
1:0
RXEQIN [38]
RXEQIN [37]
RXEQIN [36]
RXEQIN BC
Rev. 0 | Page 46 of 56
Description
Equalizer boost control for Input 19
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 18
Equalizer boost control for Input 17
Equalizer boost control for Input 16
Equalizer boost control for Input 23
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 22
Equalizer boost control for Input 21
Equalizer boost control for Input 20
Equalizer boost control for Input 27
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 26
Equalizer boost control for Input 25
Equalizer boost control for Input 24
Equalizer boost control for Input 31
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 30
Equalizer boost control for Input 29
Equalizer boost control for Input 28
Equalizer boost control for Input 35
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 34
Equalizer boost control for Input 33
Equalizer boost control for Input 32
Equalizer boost control for Input 39
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
Equalizer boost control for Input 38
Equalizer boost control for Input 37
Equalizer boost control for Input 36
Equalizer boost control for all inputs
11 = 12 dB
10 = 6 dB
01 = 3 dB
00 = disabled
ADN4605
Address: Channel
0xCB
Default
0x0
Register Name
Rx Sign Control
0xCC
0x0
Rx Sign Control
0xCD
0x0
Rx Sign Control
0xCE
0x0
Rx Sign Control
0xCF
0x0
Rx Sign Control
0xD0
0x0
Rx Termination
Control
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4
3
2
1
0
Bit Name
RXSIGN [7]
RXSIGN [6]
RXSIGN [5]
RXSIGN [4]
RXSIGN [3]
RXSIGN [2]
RXSIGN [1]
RXSIGN [0]
RXSIGN [15]
RXSIGN [14]
RXSIGN [13]
RXSIGN [12]
RXSIGN [11]
RXSIGN [10]
RXSIGN [9]
RXSIGN [8]
RXSIGN [23]
RXSIGN [22]
RXSIGN [21]
RXSIGN [20]
RXSIGN [19]
RXSIGN [18]
RXSIGN [17]
RXSIGN [16]
RXSIGN [31]
RXSIGN [30]
RXSIGN [29]
RXSIGN [28]
RXSIGN [27]
RXSIGN [26]
RXSIGN [25]
RXSIGN [24]
RXSIGN [39]
RXSIGN [38]
RXSIGN [37]
RXSIGN [36]
RXSIGN [35]
RXSIGN [34]
RXSIGN [33]
RXSIGN [32]
RXA_TERM [19:16]
Description
Signal path polarity inversion Input 7
Signal path polarity inversion Input 6
Signal path polarity inversion Input 5
Signal path polarity inversion Input 4
Signal path polarity inversion Input 3
Signal path polarity inversion Input 2
Signal path polarity inversion Input 1
Signal path polarity inversion Input 0
Signal path polarity inversion Input 15
Signal path polarity inversion Input 14
Signal path polarity inversion Input 13
Signal path polarity inversion Input 12
Signal path polarity inversion Input 11
Signal path polarity inversion Input 10
Signal path polarity inversion Input 9
Signal path polarity inversion Input 8
Signal path polarity inversion Input 23
Signal path polarity inversion Input 22
Signal path polarity inversion Input 21
Signal path polarity inversion Input 20
Signal path polarity inversion Input 19
Signal path polarity inversion Input 18
Signal path polarity inversion Input 17
Signal path polarity inversion Input 16
Signal path polarity inversion Input 31
Signal path polarity inversion Input 30
Signal path polarity inversion Input 29
Signal path polarity inversion Input 28
Signal path polarity inversion Input 27
Signal path polarity inversion Input 26
Signal path polarity inversion Input 25
Signal path polarity inversion Input 24
Signal path polarity inversion Input 39
Signal path polarity inversion Input 38
Signal path polarity inversion Input 37
Signal path polarity inversion Input 36
Signal path polarity inversion Input 35
Signal path polarity inversion Input 34
Signal path polarity inversion Input 33
Signal path polarity inversion Input 32
Input[19:16] (A Side) termination control
0: termination control enabled
1: termination control disabled
RXA_TERM [15:12] Input [15:12] (A side) termination control
RXA_TERM [11:8] Input [11:8] (A side) termination control
RXA_TERM [7:4]
Input [7:4] (A side) termination control
RXA_TERM [3:0]
Input [3:0] (A side) termination control
Rev. 0 | Page 47 of 56
ADN4605
Address: Channel
0xD1
Default
0x0
Register Name
Rx Termination
Control
Bits
4
Bit Name
RXB_TERM [39:36]
3
2
1
0
RXB_TERM [35:32]
RXB_TERM [31:28]
RXB_TERM [27:24]
RXB_TERM [23:20]
Rev. 0 | Page 48 of 56
Description
Input [39:36] (B Side) termination control
0: terminations enabled
1: terminations disabled
Input [35:32] (B Side) termination control
Input [31:28] (B Side) termination control
Input [27:24] (B Side) termination control
Input [23:20] (B Side) termination control
ADN4605
APPLICATIONS INFORMATION
protocols, four ADN4605s are used to create a full 40 × 40
matrix switch. Smaller arrays, such as 10 × 10 and 20 × 20,
require one and two ADN4605 devices, respectively. Proper
high speed PCB design techniques should be used to maintain
the signal integrity of the high data rate signals. It is important
to minimize the lane-to-lane skew and crosstalk in these
applications.
The ADN4605 is an asynchronous and protocol agnostic digital
switch and, therefore, is applicable to a wide range of applications including network routing and digital video switching.
The ADN4605 supports the data rates and signaling levels of
HDMI®, DVI®, DisplayPort and SD-, HD-, and 3G-SDI digital
video. The ADN4605 can be used to create matrix switches. An
example block diagram of a 40 × 40 matrix switch is shown in
Figure 50. Since HDMI, DVI, and DisplayPort are quad lane
IN 0
OUT 0
IN 1
OUT 1
SOURCE 1
DISPLAY 1
ADN4605
DISPLAY 2
SOURCE 2
IN 39
OUT 39
IN 0
OUT 0
OUT 1
IN 1
ADN4605
IN 39
OUT 39
IN 0
OUT 0
OUT 1
IN 1
ADN4605
SOURCE 39
IN 39
OUT 39
IN 0
OUT 0
IN 1
OUT 1
DISPLAY 39
SOURCE 40
DISPLAY 40
IN 39
OUT 39
Figure 50. ADN4605 Digital Video (DVI, HDMI, DisplayPort) Matrix Switch Block Diagram
Rev. 0 | Page 49 of 56
09796-052
ADN4605
ADN4605
O/E
IN 1
O/E
IN 2
OUT 1
CDR
E/O
OUT 2
CDR
E/O
CDR
E/O
ADN4605
O/E
IN 39
OUT 39
09796-053
40 × 40
CROSSPOINT
SWITCH
Figure 51. ADN4605 Networking Switch Application Block Diagram
8 LANE UPLINK PATH
Z0
Z0
EQ
PE
Z0
Z0
8 LANE DOWNLINK PATH
Z0
ASIC 2
Z0
PE
EQ
Z0
Z0
LOSSY CHANNEL
LOSSY CHANNEL
Figure 52. Multilane Signal Conditioning Application Diagram
Rev. 0 | Page 50 of 56
07934-053
ASIC 1
ADN4605
SUPPLY SEQUENCING
OUTPUT COMPLIANCE
Ideally, all power supplies should be brought up to the appropriate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 6). If the power supplies to the ADN4605 are
brought up separately, the supply power-up sequence is as
follows: DVCC powered first, followed by VCC, and, last the
termination supplies (VTTIA, VTTIB, VTTOA, and VTTOB).
In low voltage applications, users must pay careful attention
to both the differential and common-mode signal levels. The
choice of output voltage swing, preemphasis setting, supply
voltages (VCC and VTTOx), and output coupling (ac or dc) affect
peak and settled single-ended voltage swings and the commonmode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption.
The power-down sequence is reversed with termination
supplies being powered off first. The termination supplies
contain ESD protection diodes to the VCC power domain. To
avoid a sustained high current condition in these devices, the
VTTIx and VTTOx supplies should be powered on after VCC and
should be powered off before VCC.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
•
•
Since the absolute minimum output voltage specified in Table 1
is relative to VCC, decreasing VCC is required to maintain the
output levels within the specified limits when lower output
termination voltages are required. VTTOx voltages as low as 1.8 V
are allowable for output swings less than or equal to 400 mV
(single-ended).
Peak current from VTTIxor VTTOx to VCC < 200 mA
Sustained current from VTTIx or VTTOx to VCC < 100 mA
POWER DISSIPATION
The power dissipation of the ADN4605 depends on the supply
voltages, I/O coupling type, and device configuration. The input
termination resistors dissipate power depending on the
differential input swing and common-mode voltage. When accoupled, the common-mode voltage is equal to the termination
supply voltage (VTTIx or VTTOx). While the current drawn from
the input termination supply is effectively zero, there is still
power and heat dissipated in the termination resistors as a result
of the differential signal swing. The core supply current and
output termination current are strongly dependent on device
configuration, such as the number of channels enabled, output
level setting, and output preemphasis setting.
In high ambient temperature operating conditions, it is important to avoid exceeding the maximum junction temperature of
the device. Limiting the total power dissipation can be achieved
by the following:
•
•
•
•
Table 20 shows the change in output common mode (ΔVOCM =
VCC − VOCM) with output level and preemphasis setting. Singleended output levels are calculated for VTTOx supplies of 3.3 V
and 2.5 V to illustrate practical challenges of reducing the
supply voltage. The minimum VL (min VL) cannot be below the
absolute minimum level specified in Table 1.
Reducing the output swing
Reducing the preemphasis level
Decreasing the supply voltages within the allowable ranges
defined in Table 1
Disabling unused channels
Figure 53 illustrates an application where the ADN4605 is used
as a dc-coupled level translator to interface a 3.3 V CML driver
to an ASIC with 1.8 V I/Os. The diode in series with VCC
reduces the voltage at VCC for improved output compliance.
TX/XPT HEADROOM
The Tx Headroom and XPT Headroom registers are provided
to improve the output compliance range of the ADN4605 when
the core supply voltage (VCC) is greater than 2.7 V. Enabling
the XPT Headroom and Tx Headroom registers allows the
transmitter an extra 300 mV of output compliance. The
headroom circuitry should not be enabled when the core
supply voltage (VCC) is less than or equal to 2.7 V.
When set to 1, the XPT Headroom (Address 0x7D) and Tx
Headroom (Address 0xBB) registers are enabled for all
transmitter outputs. A value of 0 disables the headroom
generating circuitry. Note that both registers (XPT Headroom
and Tx Headroom) must be set for the headroom circuitry to
function properly.
Alternatively, the thermal resistance can be reduced by
•
•
Adding an external heat sink
Increasing the airflow
Refer to the Printed Circuit Board (PCB) Layout Guidelines
section for recommendations for proper thermal stencil layout
and fabrication.
Rev. 0 | Page 51 of 56
ADN4605
Example: VCC = 3.3 V, VTTOx = 2.5 V
In a typical application, the user can select a default output level
of 200 mV single-ended (400 mVp-p differential) and may want
the option to choose preemphasis settings of 0 dB and 9.5 dB.
With preemphasis disabled, a dc-coupled transmitter causes a
100 mV common-mode shift across the termination resistors,
whereas an ac-coupled transmitter causes twice the commonmode shift. When dc-coupled, the single-ended output voltage
swings between 2.5 V and 2.3 V and between 2.4 V and 2.2 V
when ac-coupled. In both cases, these levels are greater than the
minimum VL limit of 1.9 V (VL = VCC − 1.4 V).
With a PE setting of 9.5 dB, the ac-coupled transmitter has
single-ended swings from 2.2 V and 1.6 V, whereas the dccoupled transmitter outputs swing between 2.5 V and 1.9 V.
The minimum single-ended output voltage (VL-PE) of the
ac-coupled transmitter case exceeds the minimum VL limit of
1.9 V by 300 mV, violating the device specification.
Enabling the TX_HDROOM and XPT_HDROOM bit lowers
the minimum VL limit by approximately 300 mV to 1.6 V. This
transmitter configuration now complies with the output voltage
range specification.
Rev. 0 | Page 52 of 56
ADN4605
3.3V
3.3V
1.8V
VTTIx
VCC
VTTOx
1.8V
ASIC
3.3V
Z0
Z0
CML
Rx
CML
Z0
09796-055
ADN4605
Z0
VEE
Figure 53. DC-Coupled Level Translator Application Circuit
Table 20. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting
Single-Ended Output Levels and
PE Boost
VSW-DC 1
(mV)
100
100
100
150
150
200
200
200
250
250
300
300
300
350
350
400
400
400
450
450
500
500
550
600
1
VSW-PE1
(mV)
100
300
500
250
450
200
400
600
350
550
300
500
700
450
650
400
600
800
550
750
500
700
650
600
PE Boost
%
0.00
200.00
400.00
66.67
200.00
0.00
100.00
200.00
40.00
200.00
0.00
66.67
133.33
28.57
85.71
0.00
50.00
100.00
22.22
66.67
0.00
40.00
18.18
0.00
PE
(dB)
0.00
9.54
13.98
4.44
9.54
0.00
6.02
9.54
2.92
6.85
0.00
4.44
7.36
2.18
5.38
0.00
3.52
6.02
1.74
4.44
0.00
2.92
1.45
0.00
Tx Lane Control
Register Settings
OLEV [2:0]
0x01
0x02
0x03
0x02
0x03
0x02
0x03
0x04
0x03
0x04
0x03
0x04
0x05
0x04
0x05
0x04
0x05
0x06
0x05
0x06
0x05
0x06
0x06
0x06
PE [2:0]
0x00
0x03
0x07
0x01
0x05
0x00
0x03
0x07
0x01
0x05
0x00
0x03
0x07
0x01
0x05
0x00
0x03
0x07
0x01
0x05
0x00
0x03
0x01
0x00
AC-Coupled Outputs
VCC = VTTO =
VCC = VTTO =
3.3 V
2.5 V
Output
Current
ITTO1
(mA)
4
12
20
10
18
8
16
24
14
22
12
20
28
18
26
16
24
32
22
30
20
28
26
24
∆VOCM1
(mV)
100
300
500
250
450
200
400
600
350
550
300
500
700
450
650
400
600
800
550
750
500
700
650
600
VH-PE1
(V)
3.25
3.15
3.05
3.175
3.075
3.2
3.1
3
3.125
3.025
3.15
3.05
2.95
3.075
2.975
3.1
3.0
2.9
3.025
2.925
3.05
2.95
2.975
3.0
Symbol definitions are shown in Table 15.
Rev. 0 | Page 53 of 56
VL-PE1
(V)
3.15
2.85
2.55
2.925
2.625
3.0
2.7
2.4
2.775
2.475
2.85
2.55
2.25
2.625
2.325
2.7
2.4
2.1
2.475
2.175
2.55
2.25
2.325
2.4
VH-PE1
(V)
2.45
2.35
2.25
2.375
2.275
2.40
2.30
2.20
2.325
2.225
2.35
2.25
2.15
2.275
2.175
2.3
2.2
2.1
2.225
2.125
2.25
2.15
2.175
2.2
VL-PE1
(V)
2.35
2.05
1.75
2.125
1.825
2.20
1.90
1.60
1.975
1.675
2.05
1.75
1.45
1.825
1.525
1.9
1.6
1.3
1.675
1.375
1.75
1.45
1.525
1.6
DC-Coupled Outputs
∆VOCM1
(mV)
50
150
250
125
225
100
200
300
175
275
150
250
350
225
325
200
300
400
275
375
250
350
325
300
VCC = VTTO =
3.3 V
VCC = VTTO =
2.5 V
VH-PE1
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
VH-PE1
(V)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
VL-PE1
(V)
3.2
3.0
2.8
3.15
2.85
3.1
2.9
2.7
2.95
2.75
3.0
2.8
2.6
2.85
2.65
2.9
2.7
2.5
2.75
2.55
2.8
2.6
2.65
2.7
VL-PE1
(V)
2.4
2.2
2.0
2.25
2.05
2.3
2.1
1.9
2.15
1.95
2.2
2.0
1.8
2.05
1.85
2.1
1.9
1.7
1.95
1.75
2.0
1.8
1.85
1.9
ADN4605
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The high speed differential inputs and outputs should be routed
with 100 Ω controlled impedance differential transmission
lines. The transmission lines, either microstrip or stripline,
should be referenced to a solid low impedance reference plane.
An example of a PCB cross-section is shown in Figure 54. The
trace width (W), differential spacing (S), height above reference
plane (H), and dielectric constant of the PCB material determine
the characteristic impedance. Adjacent channels should be kept
apart by a distance greater than 3 W to minimize crosstalk.
W
S
W
Large voids in the thermal paddle area should be avoided. To
control voids in the thermal paddle area, solder masking may be
required for thermal vias to prevent solder wicking inside the
via during reflow, thus displacing the solder away from the
interface between the package thermal paddle and thermal
paddle land on the PCB. There are several methods employed
for this purpose, such as via tenting (top or bottom side), using
dry film solder mask; via plugging with liquid photo-imagible
(LPI) solder mask from the bottom side; or via encroaching.
These options are depicted in Figure 55. In case of via tenting,
the solder mask diameter should be 100 microns larger than the
via diameter.
SOLDER
MASK
COPPER
PLATING
VIA
SOLDERMASK
SIGNAL (MICROSTRIP)
H
PCB DIELECTRIC
REFERENCE PLANE
SIGNAL (STRIPLINE)
(A)
PCB DIELECTRIC
(B)
(C)
(D)
09796-101
PCB DIELECTRIC
Figure 55. Solder Mask Options for Thermal Vias: (A) Via Tenting from the
Top; (B) Via Tenting from the Bottom; (C) Via Plugging, Bottom; and (D) Via
Encroaching, Bottom
REFERENCE PLANE
W
S
W
09796-100
PCB DIELECTRIC
Figure 54. Example of a PCB Cross-Section
Rev. 0 | Page 54 of 56
ADN4605
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
35.10
35.00 SQ
34.90
26
25 23 21 19 17 15 13 11
9
7
5
3
1
6
24 22 20 18 16 14 12 10 8
4
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
BALL A1
INDICATOR
31.85
31.75 SQ
31.65
TOP VIEW
BOTTOM
VIEW
1.27
BSC
DETAIL A
DETAIL A
1.70 MAX
1.00
0.80
0.60
0.70
0.60
0.50
0.20 MIN
COPLANARITY
0.35
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2
022206-A
0.25 MIN
(4 )
0.90
0.75
0.60
BALL DIAMETER
Figure 56. 352-Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-352)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADN4605ABPZ
ADN4605-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
352-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 55 of 56
Package Option
BP-352
ADN4605
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09796-0-6/11(0)
Rev. 0 | Page 56 of 56