LINER LTC4121 40v 400ma synchronous step-down battery charger Datasheet

LTC4121/LTC4121-4.2
40V 400mA Synchronous
Step-Down Battery Charger
FEATURES
DESCRIPTION
Wide Input Voltage Range: 4.4V to 40V
nn Temperature Compensated Input Voltage
Regulation for Maximum Power Point Tracking
(MPPT)
nn Adjustable Float Voltage 3.5V to 18V (LTC4121)
nn Fixed 4.2V Float Voltage Option (LTC4121-4.2)
nn High Efficiency: Up to 95%
nn 50mA to 400mA Programmable Charge Current
nn ±1% Feedback Voltage Accuracy
nn Programmable 5% Accurate Charge Current
nn Thermally Enhanced, Low Profile (0.75mm)
16-Lead (3mm × 3mm) QFN Package
The LTC®4121 is a 400mA constant-current/constantvoltage (CC/CV) synchronous step-down battery charger.
In addition to CC/CV operation, the LTC4121 regulates its
input voltage to a programmable percentage of the input
open-circuit voltage. This technique maintains maximum
power transfer with high impedance input sources such
as solar panels.
nn
APPLICATIONS
Handheld Instruments
Solar Powered Devices
nn Industrial/Military Sensors and Devices
nn
nn
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
An external resistor programs the charge current up to
400mA. The LTC4121-4.2 is suitable for charging Li-Ion/
Polymer batteries, while the programmable float voltage
of the LTC4121 is suitable for several battery chemistries.
The LTC4121 and LTC4121-4.2 include an accurate RUN
pin threshold, low voltage battery preconditioning and bad
battery fault detection, timer termination, auto-recharge,
and NTC temperature qualified charging. The FAULT pin
provides an indication of bad battery or temperature faults.
Once charging is terminated, the LTC4121 signals end-ofcharge via the CHRG pin, and enters a low current SLEEP
mode. An auto-restart feature starts a new charging cycle
if the battery voltage drops by 2.2%.
TYPICAL APPLICATION
High Efficiency, Wide Input Voltage Range Charging with LTC4121
10k
INTVCC
RUN
BOOST
MPPT
+
–
LTC4121
SW
97
BAT
1.96M
PROG
FREQ
22µF
FB
787k
RPROG
95
22nF
SLF6025T-470MR48
CHGSNS
VIN
VBAT + 200mV
TO 40V
GND FBG
200mA, RPROG = 6.04k
400mA, RPROG = 3.01k
2.2µF
+
EFFICIENCY (%)
10µF
IN
LTC4121 Efficiency vs VIN at VFLOAT = 8.4V
93
91
89
Li-Ion
87
4121 TA01a
VBAT = 8.3V
5
10
15
20
25
VIN (V)
30
35
40
4121 TA01b
4121fc
For more information www.linear.com/LTC4121
1
LTC4121/LTC4121-4.2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN, RUN, CHRG, FAULT, MPPT.................... –0.3V to 43V
BOOST.................................... VSW – 0.3V to (VSW + 6V)
SW (DC)......................................... –0.3V to (VIN + 0.3V)
SW (Pulsed <100ns).......................–1.5V to (VIN + 1.5V)
CHGSNS, BAT, FB/BATSNS, FBG................. –0.3V to 18V
FREQ, NTC, PROG, INTVCC........................... –0.3V to 6V
ICHGSNS, IBAT...................................................... ±600mA
ICHRG , IFAULT, .........................................................±5mA
IFB, IFBG (LTC4121)..................................................±5mA
IBATSNS (LTC4121-4.2)............................................±5mA
IINTVCC................................................................... –5mA
Operating Junction Temperature Range
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range..................... –65°C to 150°
PIN CONFIGURATION
LTC4121
LTC4121-4.2
12 NTC
INTVCC 1
BOOST 2
11 FBG
BOOST 2
10 FB
7
8
GND
FREQ
CHGSNS
10 BATSNS
SW 4
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
9
5
6
7
8
CHGSNS
6
BAT
FREQ
5
MPPT
9
11 NC
GND
IN 3
GND
SW 4
12 NTC
MPPT
GND
PROG
16 15 14 13
INTVCC 1
IN 3
CHRG
RUN
16 15 14 13
FAULT
TOP VIEW
PROG
CHRG
FAULT
RUN
TOP VIEW
BAT
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 54°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB TO OBTAIN θJA
TJMAX = 125°C, θJA = 54°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB TO OBTAIN θJA
ORDER INFORMATION
(http://www.linear.com/product/LTC4121#orderinfo)
LTC4121 Options
PART NUMBER
FLOAT VOLTAGE
LTC4121
Programmable
LTC4121-4.2
4.2V Fixed
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4121EUD#PBF
LTC4121EUD#TRPBF
LGHC
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LTC4121IUD#PBF
LTC4121IUD#TRPBF
LGHC
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LTC4121EUD-4.2#PBF
LTC4121EUD-4.2#TRPBF LGMV
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LTC4121IUD-4.2#PBF
LTC4121IUD-4.2#TRPBF
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 125°C
LGMV
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VRUN = 15V, VCHGSNS = VBAT = 4V, RPROG = 3.01k,
VFB = 2.29V (LTC4121), VBATSNS = 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
IIN
DC Supply Current
40
V
0
18
V
LTC4121-4.2
0
Switching: FREQ = GND
4.2
3.5
V
mA
l
142
260
µA
l
60
110
µA
Disabled Mode: VSD < VRUN < VEN (Note 4)
l
37
80
µA
Shutdown Mode: (Note 4)
l
20
40
µA
Differential Undervoltage Lockout
VIN – VBAT Falling, VIN = 5V (LTC4121)
VIN – VBATSNS Falling, VIN = 5V (LTC4121-4.2)
l
80
160
mV
Hysteresis
VIN – VBAT Rising, VIN = 5V (LTC4121)
VIN – VBATSNS Rising, VIN = 5V (LTC4121-4.2)
INTVCC Undervoltage Lockout (Note 5)
INTVCC Rising, VIN = INTVCC + 100mV
Hysteresis
INTVCC Falling
Sleep Mode: (Note 4)
4.4V
6)
UVINTVCC
UNITS
4.4
l
Standby Mode: (Note 4)
∆VDUVLO
MAX
LTC4121 (Note 3)
Operating Input Supply Range
Battery Voltage Range
TYP
LTC4121-4.2: VBATSNS =
LTC4121: VFB = 2.51V (Note
20
115
l
4.00
4.15
mV
4.26
220
V
mV
Battery Charger
IBAT
BAT Standby Current
Standby Mode (LTC4121) (Notes 4, 8, 9)
Standby Mode (LTC4121-4.2) (Notes 4, 8, 9)
l
l
2.5
50
4.5
1000
µA
nA
BAT Shutdown Current
Shutdown Mode (LTC4121) (Notes 4, 8, 9)
Shutdown Mode (LTC4121-4.2) (Notes 4, 8, 9)
l
l
1100
10
2000
1000
nA
nA
BATSNS Standby Current (LTC4121-4.2)
Standby Mode (Notes 4, 8, 9)
l
5.4
10
µA
BATSNS Shutdown Current (LTC4121-4.2) Shutdown Mode (Notes 4, 8, 9)
l
1100
2000
nA
IFB
Feedback Pin Bias Current (LTC4121)
VFB = 2.5V (Note 6)
l
25
60
nA
IFBG_LEAK
Feedback Ground Leakage Current
(LTC4121)
Shutdown Mode (Note 4)
l
1
µA
RFBG
Feedback Ground Return Resistance
(LTC4121)
1000
2000
Ω
VFB(REG)
Feedback Pin Regulation Voltage
(LTC4121)
2.400
2.407
V
2.418
V
4.212
V
IBATSNS
VFLOAT
Regulated Float Voltage (LTC4121-4.2)
ICHG
Battery Charge Current
VRCHG
Battery Recharge Threshold
VRCHG_4.2
hPROG
Ratio of BAT Current to PROG Current
VPROG
PROG Pin Servo Voltage
RSNS
CHGSNS-BAT Sense Resistor
l
(Note 6)
2.393
l
2.370
4.188
4.200
l
4.148
RPROG = 3.01k
l
383
402
421
mA
RPROG = 24.3k
l
45
50
55
mA
VFB Falling Relative to VFB(REG) (LTC4121)
l
–38
–49
–62
mV
VBATSNS Falling Relative to VFLOAT (LTC4121-4.2)
l
–70
–93
–114
mV
VTRKL < VFB < VFB(REG) (LTC4121),
VTRKL_42 < VBATSNS < VFLOAT (LTC4121-4.2)
988
l
IBAT = –100mA
4.231
1.206
1.227
300
V
mA/mA
1.248
V
mΩ
4121fc
For more information www.linear.com/LTC4121
3
LTC4121/LTC4121-4.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VRUN = 15V, VCHGSNS = VBAT = 4V, RPROG = 3.01k,
VFB = 2.29V (LTC4121), VBATSNS = 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
ILOWBAT
Low Battery Linear Charge Current
VFB < VTRKL, VBAT = 2.6V (LTC4121) (Note 6)
MIN
TYP
MAX
6
9
16
2.15
2.21
2. 28
UNITS
mA
VBATSNS < VTRKL_4.2, VBAT = 2.6V (LTC4121-4.2)
VLOWBAT
Low Battery Threshold Voltage
VBAT Rising (LTC4121)
VBATSNS Rising (LTC4121-4.2)
l
Hysteresis
ITRKL
Switch Mode Trickle Charge Current
VLOWBAT < VBAT, VFB < VTRKL (LTC4121) (Note 6)
V
147
mV
ICHG /10
mA
122
mV
VLOWBAT < VBATSNS < VTRKL_42 (LTC4121-4.2)
PROG Pin Servo Voltage in Trickle Charge
VLOWBAT < VBAT, VFB > VTRKL (LTC4121) (Note 6)
VTRKL
Trickle Charge Threshold (LTC4121)
VFB Rising (Note 6)
Hysteresis (LTC4121)
VFB Falling (Note 6)
VTRKL_4.2
Trickle Charge Threshold (LTC4121-4.2)
VBATSNS Rising
Hysteresis (LTC4121-4.2)
VBATSNS Falling
End of Charge Indication Current Ratio
(Note 7)
VLOWBAT < VBATSNS < VTRKL_42 (LTC4121-4.2)
hC/10
l
1.65
1.68
l
2.86
2.91
1.71
50
V
mV
2.98
88
V
mV
0.1
mA/mA
Safety Timer Termination Period
1.3
2.0
2.8
hrs
Bad Battery Termination Timeout
19
30
42
min
Switcher
fOSC
Switching Frequency
tMIN_ON
Minimum Controllable On-Time
FREQ = INTVCC
l
1.0
1.5
2.0
MHz
FREQ = GND
l
0.5
0.75
1.0
MHz
120
Duty Cycle Maximum
ns
94
%
Top Switch RDSON
ISW = –100mA
0.8
Ω
Bottom Switch RDSON
ISW = 100mA
0.5
Ω
IPEAK
Peak Inductor Current Limit
Measured Across RSNS with a 15µH Inductor in
Series with RSNS (Note 10)
ISW
Switch Pin Current (Note 9)
585
1050
1250
mA
IN Open-Circuit, VBAT = VSW = 4.2V (LTC4121-4.2) l
7
15
µA
IN Open-Circuit, VBAT = VSW = 8.4V (LTC4121)
15
30
µA
l
Status Pins FAULT, CHRG
Pin Output Voltage Low
I = 2mA
Pin Leakage Current
V = 43V, Pin High-Impedance
Cold Temperature VNTC /VINTVCC Fault
Rising VNTC Threshold
550
mV
0
1
µA
74
75
NTC
l
73
Falling VNTC Threshold
Hot Temperature VNTC /VINTVCC Fault
Falling VNTC Threshold
72
l
35.5
l
1
Rising VNTC Threshold
NTC Disable Voltage
Falling VNTC Threshold
4
VNTC = VINTVCC
37.5
37.5
Rising VNTC Threshold
NTC Input Leakage Current
36.5
2
%INTVCC
%INTVCC
3
3
–50
%INTVCC
%INTVCC
%INTVCC
%INTVCC
50
nA
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VRUN = 15V, VCHGSNS = VBAT = 4V, RPROG = 3.01k,
VFB = 2.29V (LTC4121), VBATSNS = 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
Enable Threshold
VRUN Rising
Hysteresis
VRUN Falling
MIN
TYP
MAX
UNITS
2.35
2.45
2.55
V
RUN
VEN
VSD
Run Pin Input Current
VRUN = 40V
Shutdown Threshold
VRUN Falling
l
200
0.01
l
0.4
Hysteresis
mV
0.1
µA
1.2
V
220
mV
FREQ
FREQ Pin Input Low
l
FREQ Pin Input High
0.4
V
l
FREQ Pin Input Current
0 < VFREQ < VINTVCC
IMPPT
MPPT Pin Leakage Current
VMPPT = 4.2V
TMP
MPPT Sample Period
Period Between Charger Disabled Events
PWMP
MPPT Sample Pulse Width
Charger Disabled Pulse Width
KF
Internal Divider Gain
Internal DAC Voltage as a Ratio to VIN
VMP(OS)
MPPT Error Amp Gain Offset
VMPPT – VDAC, IBAT = 50%• ICHG
3.6
V
±1
µA
1000
nA
MPPT
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4121 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC4121E is guaranteed to meet performance specifications
for junction temperatures from 0°C to 85°C. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC4121I is guaranteed over the full –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance, and other environmental factors.
Note 3: If a battery voltage greater than 11V can be hot plugged to the
LTC4121 a reverse blocking diode is required in series with the BAT pin to
prevent large inrush current into the low impedance BAT pin.
15
l
28
s
36
ms
0.098
0.1
0.102
V/V
10
–45
–100
mV
Note 4: Standby mode occurs when the LTC4121/LTC4121-4.2 stops
switching due to an NTC fault, MPPT pause, or when the charge current
has dropped low enough to enter Burst Mode operation. Disabled mode
occurs when VRUN is between VSD and VEN. Shutdown mode occurs
when VRUN is below VSD or when the differential undervoltage lockout
is engaged. Sleep mode occurs after a timeout while the battery voltage
remains above the VRCHG or VRCHG_42 threshold.
Note 5: The internal supply INTVCC should only be used for the NTC
divider, it should not be used for any other loads
Note 6: For the LTC4121, the FB pin is measured with a resistance of 588k
in series with the pin.
Note 7: hC/10 is expressed as a fraction of measured full charge current as
measured at the PROG pin voltage when the CHRG pin de-asserts.
Note 8: In an application circuit with an inductor connected from SW to
CHGSNS, the total battery leakage current when disabled is the sum of
IBATSNS and ISW (LTC4121-4.2) or IBAT and IFBG_LEAK and ISW (LTC4121).
Note 9: When no supply is present at IN, the SW powers IN through the
body diode of the top side switch. This may cause additional SW pin
current depending on the load present at IN.
Note 10: Guaranteed by design and/or correlation to static test.
4121fc
For more information www.linear.com/LTC4121
5
LTC4121/LTC4121-4.2
TYPICAL PERFORMANCE CHARACTERISTICS
Typical VFB(REG) vs Temperature
4.24
4.23
2.41
4.22
2.40
4.21
VFLOAT (V)
2.39
2.38
HIGH LIMIT
DUT1
DUT2
DUT3
DUT4
LOW LIMIT
2.37
2.36
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
3 UNITS TESTED
LTC4121-4.2
VIN = 5V
HIGH LIMIT
DUT1 VFLOAT
DUT2 VFLOAT
DUT3 VFLOAT
LOW LIMIT
4.20
4.19
90
4.15
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
80
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
STANDBY FREQ HIGH
STANDBY FREQ LOW
4121 G03
BAT Pin Sleep/Shutdown Current
vs Temperature
8
Feedback Pin Standby or Sleep/
Disabled Current vs Temperature
60
LTC4121
7
LTC4121
50
STANDBY VFB = 2.51V
SLEEP/DIS VFB = 2.51V
6
IBAT (µA)
IIN (µA)
120
4.16
VIN = 15V
50
40
5
4
SLEEP VBAT = 8.4V
SLEEP VBAT = 4.2V
SHUTDOWN VBAT = 8.4V
SHUTDOWN VBAT = 4.2V
40
3
30
20
2
20
SLEEP
DIS
SD
10
10
1
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
4121 G06
4121 G05
4121 G04
BATSNS Pin Sleep/Standby or
Shutdown/Disabled Current
vs Temperature
BAT Pin Standby/Sleep/Shutdown
Current vs Temperature
800
LTC4121-4.2
7
700
6
600
5
500
SLEEP/STANDBY VBATSNS = 4.25V
SHUTDOWN/DIS VBATSNS = 4.25V
3
IBAT (nA)
IBATSNS (µA)
130
4121 G02
30
1
100
4121 G07
1120
1100
1080
3 UNITS TESTED
DUT1
DUT2
DUT3
1040
300
200
Typical RSNS Current Limit IPEAK
vs Temperature
LTC4121-4.2
SHUTDOWN VBAT = 4.25V
STANDBY VBAT = 4.25V
SLEEP VBAT = 4.25V
400
2
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
6
140
100
60
4
150
4.17
70
8
160
110
IN Pin Sleep/Disabled/Shutdown
Current vs Temperature
80
VIN = 15V
4.18
4121 G01
90
170
IFB (nA)
VFB(REG) (V)
2.42
180
4.25
LTC4121
VIN = 15V
IIN (µA)
4 UNITS TESTED
IN Pin Standby Current
vs Temperature
Typical VFLOAT vs Temperature
IPEAK (mA)
2.43
TA = 25°C, unless otherwise noted.
1020
1000
980
960
940
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
4121 G08
920
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
4121 G09
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Battery Charge Current
vs Temperature
Efficiency vs IBAT
450
100
400
VIN = 15V
VBAT = 3.8V
RPROG = 3.01k
RPROG = 6.04k
RPROG = 12.1k
RPROG = 24.3k
350
300
80
ICHG (mA)
EFFICIENCY (%)
90
VIN = 9V
VIN = 14V
VIN = 19V
VIN = 24V
70
60
100
0
200
IBAT (mA)
300
250
200
150
LTC4121-42
VBAT = 4.2V
FREQ = LOW
LSW = SLF12575T-470M2R7
50
40
TA = 25°C, unless otherwise noted.
100
50
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
400
4121 G11
4121 G10
Burst Mode Trigger Current
Typical Solar Charging Cycle
VBAT
350
IBAT
300
4.0
90
3.5
80
3.0
2.5
250
200
BAT = 500mAHr
LSW = TDK SLF7045
47µH
RFB1 = 732k,
RFB2 = 976k
RPROG = 3.01k
150
100
50
0
100
0
0.5
1
1.5
2
TIME (HR)
2.0
VCHRG
1.5
2.5
3
VBAT, VCHRG (V)
BATTERY CURRENT (mA)
400
4.5
70
IBAT (mA)
450
60
50
40
30
1.0
20
0.5
10
0
0
3.5
RPROG = 3.01kΩ
RPROG = 6.04kΩ
5
10
15
20
25
VIN (V)
30
35
4121 G13
4121 G12
IN Pin Shutdown Current
vs Input Voltage
Typical Burst Mode Waveforms
80
VPROG
200mV/DIV
ISW
200mA/DIV
VIN = 15V
VBAT = 4.2V
IBAT = 38mA
FREQ = GND
4µs/DIV
4121 G14
80
60
60
50
50
40
40
30
30
20
20
10
10
0
5
10
15
20
25
VIN (V)
DISABLED 130°C
DISABLED 25°C
DISABLED –45°C
70
IIN (µA)
IIN (µA)
VSW
5V/DIV
IN Pin Disabled Current
vs Input Voltage
SHUTDOWN 130°C
SHUTDOWN 25°C
SHUTDOWN –45°C
70
40
30
35
40
4121 G15
0
5
10
15
20
25
VIN (V)
30
35
40
4121 G16
4121fc
For more information www.linear.com/LTC4121
7
LTC4121/LTC4121-4.2
TYPICAL PERFORMANCE CHARACTERISTICS
IN Pin Switching Current
vs Input Voltage
7
IN Pin Sleep Current
vs Input Voltage
140
IBAT = 0
180
170
160
100
3
2
150
80
IIIN (µA)
FREQ = INTVCC
4
60
130°C
25°C
–45°C
1
5
10
15
20
25
VIN (V)
30
35
0
130
120
100
20
40
140
110
40
FREQ = GND
0
IN Pin Standby Current
vs Input Voltage
SLEEP 130°C
SLEEP 25°C
SLEEP –45°C
120
IIIN (µA)
IIN(SWITCHING) (mA)
6
5
TA = 25°C, unless otherwise noted.
STANDBY FREQ HIGH 25°C
STANDBY FREQ LOW 25°C
90
5
10
15
4121 G17
20
25
VIN (V)
30
35
40
4121 G18
80
5
10
15
20
25
VIN (V)
30
35
40
4121 G19
PIN FUNCTIONS
INTVCC (Pin 1): Internal Low Drop Out (LDO) Regulator
Output Pin. This pin is the output of an internal linear
regulator that generates the internal INTVCC supply from
IN. It also supplies power to the switch gate drivers and
the low battery linear charge current ILOWBAT. Connect
a 2.2µF low ESR capacitor from INTVCC to GND. Do not
place any external load on INTVCC other than the NTC bias
network. Overloading this pin can disrupt internal operation.
When the RUN pin is above VEN, and INTVCC rises above
the UVLO threshold and IN rises above BAT by ∆VDUVLO
and its hysteresis, the charger is enabled.
BOOST (Pin 2): Boosted Supply Pin. Connect a 22nF boost
capacitor from this pin to the SW pin.
IN (Pin 3): Positive Input Power Supply. Decouple to GND
with a 10µF or larger low ESR capacitor. The input supply
impedance and the input decoupling capacitor form an RC
network that must settle during the MPPT sample pulse
width of about 36ms. This allows the LTC4121 to sample
the open-circuit voltage.
SW (Pin 4): Switch Pin. The SW pin delivers power from
IN to BAT via the step-down switching regulator. An inductor should be connected from SW to CHGSNS. See
the Applications Information section for a discussion of
inductor selection.
8
GND (Pin 5, Exposed Pad Pin 17): Ground Pin. Connect to
Exposed Pad. The Exposed Pad must be soldered to PCB
GND to provide a low electrical and thermal impedance
connection to ground.
MPPT (Pin 6): Maximum Power Point Tracking Pin. This
pin is used to program an input voltage regulation loop.
Connect an external resistive divider from VIN to MPPT to
GND. This divider programs the maximum power point
voltage as percentage of the input open-circuit voltage.
For more information on programming the MPPT resistive divider refer to the Application Information section. If
the input voltage regulation feature is not used, connect
MPPT to either INTVCC or IN with a minimum 10k resistor.
Keep parasitic capacitance at the MPPT pin to a minimum
as capacitance at this pin forms a pole that may interfere
with switching regulator stability.
FREQ (Pin 7): Step-Down Regulator Switching Frequency
Select Input Pin. Connect to INTVCC to select a 1.5MHz
switching frequency or GND to select a 750kHz switching
frequency. Do not float.
CHGSNS (Pin 8): Battery Charge Current Sense Pin. An
internal current sense resistor between CHGSNS and BAT
pins monitors battery charge current. An inductor should
be connected from SW to CHGSNS.
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
PIN FUNCTIONS
BAT (Pin 9): Battery Output Pin. Battery charge current
is delivered from this pin through the internal charge
current sense resistor. In low battery conditions a small
linear charge current, ILOWBAT, is sourced from this pin
to precondition the battery. Decouple the BAT pin with a
low ESR 22µF ceramic capacitor to GND.
BATSNS (Pin 10, LTC4121-4.2 Only): Battery Voltage
Sense Pin. For proper operation, this pin must always be
connected physically close to the positive battery terminal.
FB (Pin 10, LTC4121 Only): Battery Voltage Feedback
Reference Pin. The charge function operates to achieve a
final float voltage of 2.4V at this pin. Battery float voltage
is programmed using a resistive divider from BAT to FB
to FBG, and can be programmed from 3.5V up to 18V.
The feedback pin input bias current, IFB, is 25nA. Using a
resistive divider with a Thevenin equivalent resistance of
588k compensates for input bias current error.
FBG (Pin 11, LTC4121 Only): Feedback Ground Pin. This
pin disconnects the external FB divider load from the battery
when it is not needed. When sensing the battery voltage
this pin presents a low resistance, RFBG, to GND. When in
disabled or shutdown modes this pin is high impedance.
NTC (Pin 12): Input to the Negative Temperature Coefficient
Thermistor Monitoring Circuit. The NTC pin connects to
a negative temperature coefficient thermistor which is
typically co-packaged with the battery to determine if the
battery is too hot or too cold to charge. If the battery’s
temperature is out of range, the LTC4121 enters STANDBY
mode and charging is paused until the battery temperature re-enters the valid range. A low drift bias resistor is
required from INTVCC to NTC and a thermistor is required
from NTC to GND. Tie the NTC pin to GND, and omit the
NTC resistive divider to disable NTC qualified charging if
NTC functionality is not required.
PROG (Pin 13): Charge Current Program and Charge
Current Monitor Pin. Connect a 1% resistor between
3.01k (400mA) and 24.3k (50mA) from PROG to ground
to program the charge current. While in constant-current
mode, this pin regulates to 1.227V. The voltage at this pin
represents the average charge current using the following
formula:
ICHG = hPROG •
VPROG
RPROG
where hPROG is typically 988. Keep parasitic capacitance
on the PROG pin to a minimum. If monitoring charge current via the voltage at the PROG pin add a series resistor
of at least 2k to isolate stray capacitance from this node.
CHRG (Pin 14): Open-drain Charge Status Output Pin.
Typically pulled up through a resistor to a reference
voltage, the CHRG pin indicates the status of the battery
charger. The pin can be pulled up to voltages as high as
IN when disabled, and can sink currents up to 5mA when
enabled. When the battery is being charged, the CHRG
pin is pulled low. When the termination timer expires or
the charge current drops below 10% of the programmed
value, the CHRG pin is forced to a high impedance state.
FAULT (Pin 15): Open-drain Fault Status Output Pin. Typically pulled up through a resistor to a reference voltage,
this status pin indicates fault conditions during a charge
cycle. The pin can be pulled up to voltages as high as IN
when disabled, and can sink currents up to 5mA when
enabled. An NTC temperature fault causes this pin to be
pulled low. A bad battery fault also causes this pin to
be pulled low. If no fault conditions exist, the FAULT pin
remains high impedance.
RUN (Pin 16): Run Pin. When RUN is pulled below VEN
and its hysteresis, the device is disabled. In disabled
mode, battery charge current is zero and the CHRG and
FAULT pins assume high impedance states. If the voltage
at RUN is pulled below VSD, the device is in SHUTDOWN
mode. When the voltage at the RUN pin rises above VEN,
the INTVCC LDO turns on. When the INTVCC LDO rises
above its UVLO threshold the charger is enabled. The
RUN pin should be tied to a resistive divider from VIN to
program the input voltage at which charging is enabled.
Do not float the RUN pin.
4121fc
For more information www.linear.com/LTC4121
9
10
+
+
+
D1
KR • VIN
CIN
10µF
For more information www.linear.com/LTC4121
RMPPT2
RMPPT1
RRUN2
RRUN1
KF • VIN
MPPT
NTC
CHRG
FAULT
IN
R
TMP
IN-80mV
9R
+
–
0.9
FREQ
+
–
2.45V
BAT
+
–
RUN
IN
LTC4121
+
–
IMPPT
NTC
INTVCC
CNTRL
INTVCC
DAC
INTVCC
HOT
COLD
DISABLE
LOWBAT
+
–
KF • VIN
+VMP(OS)
INTVCC
gm
2.21V
BAT
ITH
PWM
INTVCC
Figure 1. Block Diagram
–
+
SHUTDOWN
ENABLE
DUVLC
ENABLE
INTVCC
DZ
V-EA
+
–
INTVCC
C-EA
+
–
INTVCC
ENABLE
ENABLE
588k
LDO
FBG
FB
BAT
PROG
VFB(REG)
RSNS
0.3Ω
CHGSNS
GND
SW
BOOST
INTVCC
RPROG
3.01k
RFB2
RFB1
LSW
22µH
CBST
22nF
CBAT
22µF
T
CINTVCC
2.2µF
4121 F01
10k
RNOM
10k
LTC4121/LTC4121-4.2
BLOCK DIAGRAM
4121fc
LTC4121/LTC4121-4.2
BLOCK DIAGRAM
LTC4121-4.2
INTVCC
ITH
BATSNS
IN-80mV
VIN
RMPPT1
KR • VIN
IN
+
–
R
TMP
+
–
CBAT
22µF
INTVCC
+
–
588k
Li-Ion
2.4V
V-EA
INTVCC
9R
BAT
BATSNS
IMPPT
KF • VIN
RSNS
0.3Ω
C-EA
DUVLO
INTVCC
gm
MPPT
RMPPT2
+
–
CHGSNS
+
–
ENABLE
KF • VIN
+VMP(OS)
DAC
PROG
LOWBAT
–
+
BATSNS
DZ
2.21V
4121 F02
Figure 2. LTC4121-4.2 BATSNS Connections
4121fc
For more information www.linear.com/LTC4121
11
LTC4121/LTC4121-4.2
OPERATION
Overview
The LTC4121 is a synchronous step-down (buck)
monolithic battery charger with maximum power-point
tracking (MPPT) control of the source voltage. The
LTC4121/LTC4121-4.2 serves as a constant-current/
constant-voltage battery charger with the following built-in
charger functions: programmable charge current, battery
precondition with ½ hour timeout, precision shutdown/
run control, NTC thermal protection, a 2-hour safety termination timer, and automatic recharge. The LTC4121/
LTC4121-4.2 also provides output pins to indicate state
of charge and fault status.
demanded charge current. When the input voltage drops
to VMP, the charge current is reduced so as to maintain
VIN at VMP.
VOC
VIN RECOVERS
VIN
TIME
TMP = 30s
ICHG
IBAT
PAUSE CHARGER
PWMP = 36ms
TIME
SAMPLE VIN(OC) STORE
IN DAC: 23µs
4121 F03
Figure 3. MPPT Timing Diagram
Maximum Power Point Tracking
The LTC4121 employs an MPPT algorithm that compares a
stored open-circuit input voltage measurement against the
instantaneous input voltage while charging. The LTC4121
automatically reduces the charge current if the input voltage
falls below the user defined percentage of the open-circuit
voltage. This algorithm lets the LTC4121 optimize power
transfer for a variety of different input sources including
first order temperature compensation of a solar panel.
The LTC4121 periodically pauses charging to measure
the open-circuit voltage allowing the LTC4121 to track
fluctuations in the available power. About once every 30
seconds the LTC4121 pauses charging and waits about
36ms (PWMP) for the input voltage to recover to its
open-circuit potential. At the end of this recovery time,
the LTC4121 samples the input voltage divided by 10 (1/
KF), and stores this value on a digital to analog converter
(DAC). When charging resumes, the DAC voltage is compared against the MPPT pin voltage that is programmed
with a resistive divider. If the MPPT voltage falls below
the DAC voltage, the charge current is reduced to regulate
the input voltage at that level. This regulation loop serves
to maintain the input voltage at or above a user defined
level that corresponds to the peak power available from
the applied source.
A timing diagram illustrating the sampling of the opencircuit voltage is shown below. The charge current drops
to zero and the LTC4121 waits PWMP and then samples
the open-circuit voltage. When charging resumes the
input voltage collapses if the source cannot support the
12
VMP
Connect the MPPT pin to a resistive input voltage divider,
as shown in Figure 4, to program the fraction (KR) of the
input voltage where the input voltage regulation loop
reduces available charge current. The LTC4121 reduces
charge current if the MPPT pin voltage falls below the fixed
fraction (KF) of the open-circuit voltage (VOC). The ratio of
(KF/KR) defines the maximum power voltage (VMP) of the
applied power source as a ratio to the open-circuit voltage
(VOC) following the relation:
VMP KF 0.1 0.1• (RMPPT1 +RMPPT2 )
=
=
=
VOC KR KR
RMPPT2
where the MPPT pin resistive divider gain is KR = RMPPT2/
(RMPPT1 + RMPPT2). These equations can be rearranged to
solve for RMPPT2 in terms of KF (0.1) and the maximum power
voltage divided by the open circuit voltage, (VMP/VOC) as:
RMPPT2 =
0.1
• RMPPT1
V 
MP − 0.1


 VOC 
This function serves to maintain the input voltage at or
above the peak power voltage while the LTC4121 charges
a battery.
Because MPPT operation involves large changes of input
voltage, it is important to ensure that the programmed
maximum power voltage does not violate minimum input
operating conditions: 4.4V or 160mV above the battery
voltage, whichever is higher.
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
OPERATION
IN
CMPPT
(OPTIONAL)
LTC4121
LTC4121
RFB1
RMPPT1
IMPPT
VFLOAT
BAT
IFB
MPPT
FB
FBG
RMPPT2
22µF
+
Li-Ion
RFB2
ENABLE
GND
4121 F05
4121 F04
Figure 4. MPPT Resistive Divider
When no power source is applied to VIN, for example when
using a solar panel source and the panel is in the dark, the
MPPT pin divider drains power from the battery through the
body diode of the top side switch of the switching regulator. To eliminate this leakage path, the MPPT divider may
be connected to the anode of the Schottky diode that is in
series with the panel, for examples see Figures 1, 9, or 10.
For example, consider charging a battery from a source
with an open-circuit voltage of 30V and a source impedance
of 120Ω. This resistive supply has a short circuit current
of 250mA, and the peak available power of 1.875W occurs with a load of 125mA at 50% of VOC. To program the
LTC4120 to optimize the available power for this source
simply program VMP /VOC to 50% by selecting the MPPT
resistive divider gain KR = 0.2. This is obtained with a resistive divider as shown in Figure 4 with RMPPT2 = RMPPT1 /4.
With standard 1% resistors this is approximated with
RMPPT1 = 402k, and RMPPT2 = 100k.
If the MPPT pin sees excess capacitance to GND, this may
affect switching regulator stability. In such cases, one may
optionally add a 50pF to 150pF lead capacitor (CMPPT) as
shown in Figure 4.
The sampling of VOC is done at an extremely low duty
cycle so as to have minimum impact on the average
charge current. The time between sample events, TMP,
is typically about 30 seconds, with an idle time, PWMP,
of about 36ms to allow the source to recover to its
open-circuit voltage through the time constant associated with the input decoupling capacitor CIN. The time
constant for the source to recover to its open-circuit
voltage must be kept below the idle period. Limit the
Figure 5. Programming the Float Voltage with LTC4121
input capacitor to 10µF to avoid increasing the source
recovery time.
Programming the Battery Float Voltage
For the LTC4121, the battery float voltage is programmed
by placing a resistive divider from the battery to FB and
FBG as shown in Figure 5. The battery float voltage is
programmable anywhere from 3.5V up to 18V. The programmable battery float voltage, VFLOAT, is then governed
by the following equation:
VFLOAT = VFB(REG) •
(RFB1 +RFB2 )
RFB2
where VFB(REG) is typically 2.4V.
Due to the input bias current (IFB) of the voltage error amp
(V-EA), care must also be taken to select the Thevenin
equivalent resistance of RFB1//RFB2 close to 588kΩ. Start
by calculating RFB1 to satisfy the following relations:
RFB1 =
VFLOAT • 588k
VFB(REG)
Find the closest 0.1% or 1% resistor to the calculated
value. With RFB1 calculate:
RFB2 =
VFB(REG) • RFB1
VFLOAT − VFB(REG)
− 1000Ω
Where 1000Ω represent the typical value of RFBG. This is
the resistance of the FBG pin which serves as the ground
return for the battery float voltage divider.
Once RFB1 and RFB2 are selected re-calculate the value of
VFLOAT obtained with the resistors available. If the error
4121fc
For more information www.linear.com/LTC4121
13
LTC4121/LTC4121-4.2
OPERATION
is too large substitute another standard resistor value for
RFB1 and recalculate RFB2. Repeat until the float voltage
error is acceptable.
PROG resistor sets the maximum charge current, or
the current delivered while the charger is operating in
constant-current (CC) mode.
Table 1 and Table 2 below list recommended standard 0.1%
and 1% resistor values for common battery float voltages.
Analog Charge Current Monitor
Table 1. Recommended 0.1% Resistors for Common VFLOAT
VFLOAT (V)
RFB1 (kΩ)
RFB2 (kΩ)
TYPICAL ERROR (%)
3.6
887
1780
–0.13
4.1
1010
1420
0.15
4.2
1010
1350
–0.13
7.2
1800
898
0.08
8.2
2000
825
0.14
8.4
2050
816
0.27
Table 2 Recommended 1% Resistors for Common VFLOAT
VFLOAT (V)
RFB1 (kΩ)
RFB2 (kΩ)
TYPICAL ERROR (%)
3.6
887
1780
–0.13
4.1
1000
1430
0.26
4.2
1020
1370
–0.34
7.2
1780
887
0.16
8.2
2000
825
0.14
8.4
2100
845
–0.50
The PROG pin provides a voltage signal proportional
to the actual charge current. Care must be exercised in
measuring this voltage as any capacitance at the PROG pin
forms a pole that may cause loop instability. If observing
the PROG pin voltage, add a series resistor of at least 2k
and limit stray capacitance at this node to less than 50pF.
In the event that the input voltage cannot support the
demanded charge current, the PROG pin voltage may not
represent the actual charge current. In cases such as this,
the PWM switch frequency drops as the charger enters
dropout operation where the top switch remains on for
more than one clock cycle as the inductor current attempts
to ramp up to the desired current. If the top switch remains
on in dropout for 8 clock cycles a dropout detector forces
the bottom switch on for the remainder of the 8th cycle.
In such a case, the PROG pin voltage remains at 1.227V,
but the charge current may not reach the desired level.
Programming the Charge Current
NTC Thermal Battery Protection
The current-error amp (C-EA) measures the current
through an internal 0.3Ω current sense resistor between
the CHGSNS and BAT pins. The C-EA outputs a fraction
of the charge current, 1/hPROG, to the PROG pin. The
voltage-error amp (V-EA) and PWM control circuitry can
limit the PROG pin voltage to control charge current. An
internal clamp (DZ) limits the PROG pin voltage to VPROG,
which in turn limits the charge current to:
The LTC4121 monitors battery temperature using a thermistor during the charging cycle. If the battery temperature
moves outside a safe charging range, the IC suspends
charging and signals a fault condition until the tempera-
h
•V
1212V
ICHG = PROG PROG =
RPROG
RPROG
ICHG _ TRKL =
120V
RPROG
where hPROG is typically 988, VPROG is either 1.227V or
122mV during trickle charge, and RPROG is the resistance
of the grounded resistor applied to the PROG pin. The
LTC4121
BAT
INTVCC
RBIAS
TOO COLD
+
–
TOO HOT
+
–
IGNORE NTC
+
–
NTC
RADJ
OPT
74% INTVCC
37% INTVCC
RNTC
+
T
Li-Ion
2% INTVCC
4121 F06
Figure 6. NTC Connection
14
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
OPERATION
ture returns to the safe charging range. The safe charging
range is determined by two comparators that monitor the
voltage at the NTC pin. NTC qualified charging is disabled
if the NTC pin is pulled below about 85mV (VDIS).
Thermistor manufacturers usually include either a temperature lookup table identified with a characteristic curve
number, or a formula relating temperature to the resistor
value. Each thermistor is also typically designated by a
thermistor gain value B25/85.
The NTC pin should be connected to a voltage divider
from INTVCC to GND as shown in Figure 6. In the simple
application (RADJ = 0) a 1% resistor, RBIAS, with a value
equal to the resistance of the thermistor at 25°C is connected from INTVCC to NTC, and a thermistor is connected
from NTC to GND. With this setup, the LTC4121 pauses
charging when the resistance of the thermistor increases
to 285% the RBIAS resistor as the temperature drops. For
a Vishay Curve 2 thermistor with B25/85 = 3490 and 25°C
resistance of 10kΩ, this corresponds to a temperature
of about 0°C. The LTC4121 also pauses charging if the
thermistor resistance decreases to 58.8% of the RBIAS
resistor. For the same Vishay Curve 2 thermistor, this
corresponds to approximately 40°C. With a Vishay Curve
2 thermistor, the hot and cold comparators both have
about 2°C of hysteresis to prevent oscillations about the
trip points. The NTC comparator trip points are ratio metric
to the INTVCC voltage, so NTC trip points are defined as a
percentage of INTVCC. The HOT threshold is calculated as
285%/385% = 74% of INTVCC and the COLD threshold is
calculated as 58.8%/158% = 37% of INTVCC.
The hot and cold trip points may be adjusted using a different type of thermistor, or a different RBIAS resistor, or by
adding a desensitizing resistor, RADJ, or by a combination
of these measures as shown in Figure 6. For example, by
increasing RBIAS to 12.4kΩ, with the same thermistor as
before, the cold trip point moves down to –5°C, and the
hot trip point moves down to 34°C. If a Vishay Curve 1
thermistor with B25/85 = 3964 and resistance of 100kΩ
at 25°C is used, a 1% RBIAS resistor of 118kΩ and a 1%
RADJ resistor of 12.1kΩ results in a cold trip point of 0°C,
and a hot trip point of 39°C.
End-of-Charge Indication and Safety Timeout
The LTC4121 uses a safety timer to terminate charging.
Whenever the LTC4121 is in constant current mode the
timer is paused, and when FB rises or falls through the
VRCHG threshold the timer is reset. When the battery
voltage reaches the float voltage, the safety timer begins
counting down a 2-hour timeout. If charge current falls
below one tenth of the programmed maximum charge current (hC/10), the CHRG status pin rises, but top-off charge
current continues to flow until the timer finishes. After the
timeout, the LTC4121 enters a low-power sleep mode.
Automatic Recharge
In sleep mode, the IC continues to monitor battery voltage.
If the battery falls 2.2% (VRCHG or VRCHG_42) from the fullcharge float voltage, the LTC4121 engages an automatic
recharge cycle as the safety timer is reset. Automatic
recharge has a built in delay of about 0.5ms to prevent
triggering a new charge cycle if a load transient causes
the battery voltage to drop temporarily.
State of Charge and Fault Status Pins
The LTC4121 contains two open-drain outputs which
provide charge status and signal fault indications. The
CHRG pin pulls low to indicate charging at a rate higher
than C/10. The FAULT pin pulls low to indicate a bad battery timeout, or to indicate an NTC thermal fault condition.
During NTC faults the CHRG pin remains low, but when
a bad-battery timeout occurs the CHRG pin de-asserts.
When the open drain outputs are pulled up with a resistor,
Table 3 summarizes the charger state that is indicated by
the pin voltages.
Table 3 LTC4121 Open-Drain Indicators with Resistor Pull-Ups
FAULT
CHRG
CHARGER STATE
High
High
Off or Topping-Off Charge at a Rate Less Than C/10.
High
Low
Charging at Rate Higher Than C/10
Low
High
Bad Battery Fault
Low
Low
NTC Thermal Fault, Charging Paused
Low Battery Voltage Operation
The LTC4121 automatically preconditions heavily discharged batteries. If the battery voltage is below VLOWBAT
minus its hysteresis (typically 2.05V - e.g. battery pack
4121fc
For more information www.linear.com/LTC4121
15
LTC4121/LTC4121-4.2
OPERATION
protection has been engaged) a DC current, ILOWBAT, is
applied to the BAT pin from the INTVCC supply. When
the battery voltage rises above VLOWBAT, the switching
regulator is enabled and charges the battery at a trickle
charge level of 10% of the full scale charge current (in
addition to the DC ILOWBAT current). Trickle charging of
the battery continues until the sensed battery voltage rises
above the trickle charge threshold, VTRKL, or VTRKL_42.
When the battery rises above the trickle charge threshold
the full scale charge current is applied and the DC trickle
charge current is turned off. If the battery remains below
the trickle charge threshold for more than 30 minutes,
charging terminates and the fault status pin is asserted
to indicate a bad battery. After a bad battery fault, the
LTC4121 automatically restarts a new charge cycle once
the failed battery is removed and replaced with another
battery. The LTC4121-4.2 monitors the BATSNS pin voltage to sense LOWBAT and TRKL conditions.
Precision Run/Shutdown Control
The LTC4121 remains in a low power disabled mode until
the RUN pin is driven above VEN (typically 2.45V). While
the LTC4121 is in disabled mode, current drain from the
battery is reduced to extend battery lifetime, the status pins
are both de-asserted, and the FBG pin is high impedance.
Charging can be stopped at any time by pulling the RUN
pin below 2.25V. The LTC4121 also offers an extremely
low operating current shutdown mode when the RUN pin
is pulled below VSD (typically about 0.7V). In this condition
less than 20µA is pulled from the supply at IN. Tie the RUN
pin to a resistive divider from the IN supply to program
the voltage where the LTC4121 turns on. Examples are
shown in Figures 9 and 10.
Differential Under Voltage Lockout
The LTC4121 monitors the difference between the battery
voltage, VBAT, and the input supply voltage, VIN. If the
difference (VIN – VBAT) falls to ∆VDUVLO, all functions are
disabled and the part is forced into shutdown mode until
(VIN – VBAT) rises above the ∆VDUVLO rising threshold. The
LTC4121-4.2 monitors the VBATSNS and VIN pin voltages
to sense DUVLO condition.
16
User Selectable Switching Regulator Operating
Frequency
The LTC4121 uses a constant-frequency synchronous
step-down switching regulator architecture to produce high operating efficiency. The nominal operating
frequency, fOSC, is programmed by pulling the FREQ pin to
either INTVCC or to GND to obtain a switching frequency
of 1.5MHz or 750kHz, respectively. The high operating
frequency allows the use of smaller external components.
Selection of the operating frequency is a trade-off between
efficiency, component size, and margin from the minimum
on-time of the switcher. Operation at lower frequency
improves efficiency by reducing internal gate charge and
switching losses, but requires larger inductance values to
maintain low output ripple. Operation at higher frequency
allows the use of smaller components, but may require
sufficient margin from the minimum on-time at the lowest
duty cycle if fixed-frequency switching is required.
PWM Dropout Detector
If the input voltage approaches the battery voltage, the
LTC4121 may require duty cycles approaching 100%. This
mode of operation is known as dropout. In dropout, the
operating frequency may fall well below the programmed
fOSC value. If the top switch remains on for eight clock
cycles, the dropout detector activates and forces the
bottom switch on for the remainder of that clock cycle
or until the inductor current decays to zero. This avoids
a potential source of audible noise when using ceramic
input or output capacitors and prevents the boost supply capacitor for the top gate drive from discharging. In
dropout operation, the actual charge current may not be
able to reach the full-scale programmed value. In such a
scenario the analog charge current monitor function does
not represent actual charge current being delivered.
Burst Mode® Operation
At low charge currents, for example during constantvoltage mode, the LTC4121 automatically enters Burst
Mode operation. In Burst Mode operation the switcher is
periodically forced into standby mode in order to improve
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LTC4121/LTC4121-4.2
OPERATION
efficiency. The LTC4121 automatically enters Burst Mode
operation after it exits constant-current (CC) mode and as
the charge current drops below about 80mA. Burst Mode
operation is triggered at lower currents for larger PROG
resistors, and depends on the input supply voltage, the
battery voltage, and the selected inductor. Refer to the Burst
Mode Trigger Current and Typical Burst Mode Waveforms
graphs in the Typical Performance Characteristics section
for more information on Burst Mode operation. Burst Mode
operation has some hysteresis and remains engaged for
battery current up to about 150mA, depending on LSW,VIN
and VBAT. When operating in Burst Mode, the PROG pin
voltage to average charge current relationship is not well
defined. This may cause the CHRG pin to de-assert early
depending on the amplitude of the burst ripple.
Boost Supply Refresh
The BOOST supply for the top gate drive in the LTC4121
switching regulator is generated by bootstrapping the
BOOST flying capacitor to INTVCC whenever the bottom
switch is turned on. This technique provides a voltage of
INTVCC from the BOOST pin to the SW pin. In the event
that the bottom switch remains off for a prolonged period
of time, e.g. during Burst Mode operation, the BOOST
supply may require a refresh. Similar to the PWM dropout
timer, the LTC4121 counts the number of clock cycles
since the last BOOST refresh. When this count reaches
32 the next PWM cycle begins by turning on the bottom
side switch first. This pulse refreshes the BOOST flying
capacitor to INTVCC and ensures that the top-side gate
driver has sufficient voltage to turn on the top side switch
at the beginning of the next cycle.
Operation without an Input Supply or Shaded Panel
When a battery is the only available power source, care
should be taken to eliminate loading of the IN pin. Load
current on IN drains the battery voltage through the body
diode of the top side power switch as VIN falls below VSW.
A diode inserted in series with the solar panel, as shown
on the front page schematic, eliminates this discharge
path. Alternatively, a diode may be placed in series with
the BAT pin (as shown in Figure 8).
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17
LTC4121/LTC4121-4.2
APPLICATIONS INFORMATION
MPPT Programming
The maximum power-point tracking loop is programmed
by selecting a resistive divider from IN to MPPT to GND
as shown in Figure 4. This user programmable voltage
divider (KR) serves to define a fraction of the input voltage
that appears at the MPPT pin:
KR =
RMPPT2
V
= MPPT
RMPPT1 +RMPPT2
VIN
Using the schematic of Figure 4, this ratio is obtained by
selecting:
 K 
1−  F 
 75% 
RMPPT1 =
• RMPPT2
 KF 


 75% 
RMPPT1 = 6.5 • RMPPT2
This fraction of VIN is continuously compared against
a fixed fraction of the open-circuit input voltage that is
stored within the LTC4121. A fixed internal resistive divider
(0.1•VIN) is periodically sampled to compare the opencircuit input voltage against the user defined fraction of
the loaded input voltage (KR • VIN). On an interval of TMP,
the LTC4121 turns off all charger functions reverting to
STANDBY mode. The LTC4121 then waits for a delay, of
about 36ms, PWMP, after turning off the charge current to
allow the input supply to recover to its open-circuit voltage. Finally, the LTC4121 samples the open-circuit input
voltage VOC through a fixed internal divider; KF = 1/10.
After sampling the open-circuit voltage, the LTC4121 turns
on all functions and reverts to normal operation. During
normal operation, the stored 0.1•VOC voltage is compared
against the instantaneous MPPT pin voltage: KR • VIN. If
the MPPT voltage falls below the stored level, the charge
current is reduced to maintain the input voltage. The ratio
of 0.1/KR defines the percentage below the open-circuit
voltage where charge current is reduced to maintain the
maximum input power.
Because MPPT operation involves large changes of input
voltage, it is important to ensure that the programmed
maximum power voltage does not violate minimum input
operating conditions: 4.4V or 160mV above the battery
voltage, whichever is higher.
Using standard 1% resistors, this is obtained with:
RMPPT1 = 787k and RMPPT2 = 121k.
MPPT Error Terms
Uncertainty in programming the MPPT set point is bound
by three error terms: MPPT pin leakage, DAC quantization
error, and the finite offset error in the MPPT error amp. All
error terms are lumped into VMP(OS), with a typical value
of –45mV. This offset at the input to the MPPT error amp
is multiplied by 1/KR when observed at the IN regulation
point, VMP.
For example, with the same KR = 0.1333 (RMPPT1 = 787k
and RMPPT2 = 121k) the –45mV VMP(OS) error gets amplified to –45mV/0.1333 = –338mV at VIN from the VMP
set point of 75% of VOC. If VOC is 30V, the minimum VMP
regulation point is about 22.16V, or 73.9% of the opencircuit voltage.
For solar panel sources, the available power drops off
quickly on the high side, and relatively slowly on the low
side, this is illustrated in the curve in Figure 7. For these
types of sources, it is usually better to err on the low side
when programming the VMP voltage. This is what the
LTC4121 does normally, so most users can simply design
for a VMP voltage at (or just below) the level specified by
the solar panel manufacturer. For more information on
solar panels, refer to the panel’s data sheet.
For example, to select an MPPT set point, VMP, at 75%
of the open-circuit voltage, VOC, select ratio KR using the
following relation:
KR =
18
KF
0.1
=
= 0.1333
75% 0.75
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LTC4121/LTC4121-4.2
APPLICATIONS INFORMATION
The maximum input voltage allowed to maintain constant
frequency operation is:
4
25°C
POWER (W)
3
VIN(MAX) =
75°C
2
0
where VLOWBAT, is the lowest battery voltage where the
switcher is enabled.
50°C
1
0
5
20
15
10
PANEL VOLTAGE (V)
25
4121 F07
Figure 7. Typical 3W Panel Power vs Voltage
Input Voltage and Minimum On-Time
The LTC4121 maintains constant frequency operation under most operating conditions. Under certain situations with
high input voltage and high switching frequency selected
and a low battery voltage, the LTC4121 may not be able
to maintain constant frequency operation. These factors,
combined with the minimum on-time of the LTC4121,
impose a minimum limit on the duty cycle to maintain
fixed-frequency operation. The on-time of the top switch
is related to the duty cycle (VBAT/VIN) and the switching
frequency, fOSC in Hz:
tON =
VLOWBAT
fOSC • tMIN(ON)
VBAT
fOSC • VIN
When operating from a high input voltage with a low
battery voltage, the PWM control algorithm may attempt
to enforce a duty cycle which requires an on-time lower
than the LTC4121 minimum, tMIN(ON). This minimum
duty cycle is approximately 18% for 1.5MHz operation
or 9% for 750kHz operation. If this occurs, the charge
current and battery voltage remains in regulation, but the
switching duty cycle may not remain fixed, or the switching frequency may decreases to an integer fraction of its
programmed value.
Exceeding the minimum on-time constraint does not affect
charge current or battery float voltage, so it may not be
of critical importance in most cases and high switching
frequencies may be used in the design without any fear of
severe consequences. As the sections on Inductor Selection
and Capacitor Selection show, high switching frequencies
allow the use of smaller board components, thus reducing
the footprint of the applications circuit.
Fixed-frequency operation may also be influenced by
dropout and burst mode operation as discussed previously.
Switching Inductor Selection
The primary criterion for switching inductor value selection
in an LTC4121 charger is the ripple current created in that
inductor. Once the inductance value is determined, the
saturation current rating for that inductor must be equal
to or exceed the maximum peak current in the inductor,
IL(PEAK). The peak value of the inductor current is the sum
of the programmed charge current, ICHG, plus one half of
the ripple current, ∆IL. The peak inductor current must
also remain below the current limit of the LTC4121, IPEAK.
IL(PEAK) = ICHG +
∆IL
2
< IPEAK
The current limit of the LTC4121, IPEAK, is at least 585mA
(and at most 1250mA). The typical value of IPEAK is illustrated in a graph in the Typical Performance Characteristics,
RSNS Current Limit vs Temperature.
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19
LTC4121/LTC4121-4.2
APPLICATIONS INFORMATION
For a given input and battery voltage, the inductor value
and switching frequency determines the peak-to-peak
ripple current amplitude according to the following formula:
∆IL =
( VIN − VBAT ) • VBAT
CIN < PWMP / (5 • RSOURCE),
fOSC • VIN • LSW
Ripple current is typically set to be within a range of 20%
to 40% of the programmed charge current, ICHG. To obtain
a ripple current in this range, select an inductor value using the nearest standard inductance value available that
obeys the following formula:
LSW ≥
( VIN(MAX) − VFLOAT ) • VFLOAT
fOSC • VIN(MAX) • (30% •ICHG )
Reverse Blocking
Input Capacitor
The LTC4121 charger is biased directly from the input
supply at the VIN pin. This supply provides large switched
currents, so a high-quality, low ESR decoupling capacitor
is recommended to minimize voltage glitches at VIN. Bulk
capacitance is a function of the desired input ripple voltage
(∆VIN), and follows the relation:
CIN(BULK) =
VBAT
VIN
∆VIN
where RSOURCE is the impedance of the power source.
For a solar panel this is the impedance of the panel at the
open-circuit voltage. Looking at a panel's I-V curve, the
source impedance is approximated by (VOC – VMP)/IMP.
Typically VMP is about 80% of VOC, so the solar panels
source impedance can be approximated as:
RSOURCE ≈ VOC / (5 • IMP).
Then select an inductor with a saturation current rating
greater than IL(PEAK).
ICHG •
to accurately sample the open-circuit voltage at VIN.
Adequate settling is usually achieved in 3 to 5 R-C time
constants. To allow the LTC4121 to correctly sample the
open-circuit voltage, limit CIN to:
(µF)
Input ripple voltages (∆VIN) above 0.01V are not recommended. 10µF is typically adequate for most charger
applications, with a voltage rating of 40V.
When a fully charged battery is suddenly applied to the
BAT pin, a large in-rush current charges the CIN capacitor
through the body diode of the LTC4121 topside power
switch. While the amplitude of this current can exceed
several Amps, the LTC4121 will survive provided the battery voltage is below about 11V. To completely eliminate
this in-rush current, a blocking P-channel MOSFET should
be placed in series with the BAT pin. When the battery is
the only source of power, this PMOS also serves to decrease battery drain current due to any load placed at VIN,
conducted through the body diode of the topside power
switch on the LTC4121. The PMOS body diode shown in
Figure 8 serves as the blocking component since CHRG is
high impedance when the battery voltage is greater than
the input voltage. When CHRG pulls low, i.e. during most
of a normal charge cycle, the PMOS is on to reduce power
dissipation. The PMOS requires a forward current rating
equal to the programmed charge current and a reverse
breakdown voltage equal to the programmed float voltage.
The input capacitor also forms a pole with the source
impedance that supplies power to VIN. This R-C network
must settle within the 36ms PWMP period for the LTC4121
20
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LTC4121/LTC4121-4.2
APPLICATIONS INFORMATION
VIN
VIN
CHRG
4.99k*
49.9k
10µF
RUN
BAT
4.7µF
2.2µF
INTVCC
22µF
470k
LTC4121
Li-Ion
RFB1
PROG
FB
RFB2
RPROG
GND
VIN
VIN
FBG
*ADD 4.99k WHEN MAX BAT VOLTAGE APPROACHES 85%
OF VGS LIMIT FOR Si2343.
CHRG
49.9k
10µF
RUN
BAT
4.7µF
2.2µF
+
SI2343DS
INTVCC
22µF
470k
SI2343DS
LTC4121-4.2
+
Li-Ion
BATSNS
4121 F08
PROG
RPROG
GND
Figure 8. Reverse Blocking with a P-Channel MOSFET in Series with the BAT Pin
BAT Capacitor and Output Ripple: CBAT
Boost Supply Capacitor
The LTC4121 charger output requires bypass capacitance
connected from BAT to GND (CBAT). A 22µF ceramic capacitor is required for all applications. In systems where
the battery can be disconnected from the charger output,
additional bypass capacitance may be desired. In this
type of application, excessive ripple and/or low amplitude
oscillations can occur without additional output bulk
capacitance. For optimum stability, the additional bulk
capacitance should also have a small amount of ESR. For
these applications, place a 100µF low ESR non-ceramic
capacitor (chip tantalum or organic semiconductor capacitors such as Sanyo OS-CONs or POSCAPs) from BAT to
GND, in parallel with the 22µF ceramic bypass capacitor,
or use large ceramic capacitors with an additional small
series ESR resistor of less than 1Ω. This additional bypass
capacitance may also be required in systems where the
battery is connected to the charger with long wires. The
voltage rating of all capacitors applied to CBAT must meet
or exceed the battery float voltage.
The BOOST pin provides a bootstrapped supply rail that
provides power to the top gate drivers. The operating voltage of the BOOST pin is internally generated from INTVCC
whenever the SW pin pulls low. This provides a floating
voltage of INTVCC above SW that is held by a capacitor
tied from BOOST to SW. A low ESR ceramic capacitor
of 10nF to 33nF is sufficient, with a voltage rating of 6V.
INTVCC Supply and Capacitor
Power for the top and bottom gate drivers and most other
internal circuitry is derived from the INTVCC pin. A low
ESR ceramic capacitor of 2.2µF is required on the INTVCC
pin. The INTVCC supply has a relatively low current limit
(about 20mA) that is dialed back when INTVCC is low to
reduce power dissipation. Do not use the INTVCC voltage
to supply power for any external circuitry except for the
NTCBIAS network. When the RUN pin is above VEN, the
INTVCC supply is enabled, and when INTVCC rises above
UVINTVCC, the charger is enabled.
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21
LTC4121/LTC4121-4.2
APPLICATIONS INFORMATION
Calculating IC Power Dissipation
PCB Layout
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4121 package (θJA) is
54°C/W; provided that the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on the forced air cooling and other
heat sinking means, especially the amount of copper on
the PCB to which the LTC4121 is attached. The actual
power dissipation while charging is approximated by the
following formula:
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4121 is essential. For
maximum efficiency, the switch node rise and fall times
should be minimized. The following PCB design priority
list will help insure proper topology. Layout the PCB using
the guidelines listed below in this specific order:
(
)
PD = VIN − VBAT •ITRKL
1. VIN input capacitor should be placed as close as possible
to the IN pin with the shortest copper traces possible.
The ground return of the input capacitor should be
connected to a solid ground plane.
2. Place the inductor as close as possible to the SW
pin. Minimize the surface area of the SW pin node.
Make the trace width the minimum needed to support
the programmed charge current, and ensure that the
spacing to other copper traces be maximized to reduce
capacitance from the SW node to any other node.
+ VIN •IIN(SWITCHING)
+RSNS •I 2CHG
V 
+RDSON(TOP) •  BAT  •I 2CHG
 VIN 
 V 
+RDSON(BOT) • 1− BAT  •I 2CHG
VIN 

3. Place the BAT capacitor adjacent to the BAT pin and
ensure that the ground return feeds to the solid ground
plane.
During trickle charge (VBAT < VTRKL) the power dissipation
may be significant as ITRKL is typically 10mA, however
during normal charging the ITRKL term is zero. ITRKL is
also zero if VBAT approaches INTVCC, since ITRKL is sourced
from the INTVCC LDO.
The junction temperature can be estimated using the following formula:
TJ = TA + PD • ΘJA.
where TA is the ambient operating temperature.
4. Route analog ground (RUN pin divider grounded resistor,
the MPPT pin divider, and INTVCC capacitor ground) to
the solid ground plane.
5. It is important to minimize parasitic capacitance on
the PROG pin. The trace connecting to this pin should
be as short as possible with extra wide spacing from
adjacent copper traces.
6. Keep the GND capacitance of the MPPT pin to a minimum, and reduce coupling from the MPPT pin to any
of the switching pins (SW, BOOST, and CHGSNS) by
routing the MPPT trace away from these signals.
Maximize the copper area connected to the exposed pad.
Place via connections directly under the exposed pad to
connect a large copper ground plane to the LTC4121 to
improve heat transfer.
Example PCB layout files of the LTC4121 are available at
the following link:
http://www.linear.com/product/LTC4121#demoboards.
22
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LTC4121/LTC4121-4.2
APPLICATIONS EXAMPLES
Design Example 1
Consider the design example, shown in Figure 14 on the
last page, for the LTC4121-4.2. Input power is from a
solar panel that has an open-circuit voltage VOC = 21.6V,
and maximum power voltage VMP = 17V, or 79% of the
open-circuit voltage. The battery float voltage is 4.2V, and
the desired charge current is 400mA. The application has
a minimum battery voltage of 2.5V.
There is no requirement given for the input voltage where
the LTC4121-4.2 should turn on. Given that the MPPT set
point, VMP, is at 79% of the open-circuit voltage of 21.6V,
one may elect to turn-on the LTC4121-4.2 at an input
voltage anywhere below this set point. A level of 60% of
the open-circuit voltage is selected, or 13V. This selection
results in a RUN pin divider of RRUN1 = 464kΩ, and RRUN2
= 107kΩ. With this RUN pin divider, the LTC4121-4.2 enters DISABLED mode if the input supply drops below 12V.
Now select the MPPT resistive divider to obtain a maximum power point of 17V. The maximum power point of
17V is at 79% of the open-circuit voltage. This is used to
calculate the ratio
tON =
2.5V
= 154.3 > tMIN(ON)
750kHz • 21.6V
Next, the minimum standard inductance value is found
that maintains an inductor ripple current 30% of ICHG, at
the peak power input voltage of 17V using the following
formula:
LSW >
(17V − 4.2V) • 4.2V
= 35µH
750kHz • 17V • (30% • 400mA)
The next largest standard inductance value is 47µH. This
inductor selection results in a ripple current of 90mA and
peak inductor current IL(PEAK) of:
IL(PEAK) = 400mA +
(17V − 4.2V) • 4.2V
2 • 750kHz • 17V • 47µH
IL(PEAK) = 444mA
The saturation current of the switch inductor needs to be
greater than IL(PEAK).
VMP 0.1
=
VOC KR
Now select RPROG for the desired average charge current
during constant-current operation. The nearest standard
1% resistor to satisfy the following relation:
Select
KR = 0.1/0.79 = 0.1266
This ratio is obtained by selecting RMPPT1 and RMPPT2
following:
RMPPT1 =
The switching frequency of 750kHz is selected to achieve
an on-time of 154ns which is greater than tMIN(ON) at the
maximum input supply, and minimum battery voltage of
2.5V.
(1− 0.1266)
RMPPT2 = 6.9 • RMPPT2
0.1266
Using standard 1% resistors, select RMPPT1 = 698kΩ and
RMPPT2 = 100kΩ to obtain a KR of 0.1253, and an MPPT
set point of 17.24V.
As described in the MPPT Error Terms section, the actual
regulation voltage will vary from the programmed voltage
down to 45mV/KR = 359mV below the programmed voltage.
In this example, the expected regulation voltage is 16.88V
to 17.24V, or 78.2% to 80.1% of the open-circuit voltage.
RPROG =
hPROG • 1.227V
= 3.01kΩ
400mA
Select CIN = 10µF for the input decoupling capacitor,
achieving an input voltage ripple of 10mV.
∆VIN =
4.2V
17V = 10mV
10µF
400mA •
The minimum standard voltage rating for CIN is 50V.
Select CINTVCC = 2.2µF, and CBST = 22nF, and finally the
battery capacitor should be 22µF. The lowest standard
voltage rating for these capacitors is 6V.
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23
LTC4121/LTC4121-4.2
APPLICATIONS EXAMPLES
In this design example, maximum power dissipation is
calculated during trickle charge as:
PD = (17V − 2.5V) • 10mA
This ratio is obtained by selecting RMPPT1 and RMPPT2
following:
RMPPT1 =
+ 17V • 2.5mA
+ 0.3Ω • 0.04A 2
(1− 0.1245)
RMPPT2 = 7.03 • RMPPT2
0.1245
Using standard 1% resistors, select RMPPT1 = 715kΩ and
RMPPT2 = 102kΩ to obtain a KR of 0.1248 and nominal
MPPT set point of 17.94V. Including the effect of MPPT
error terms, the expected MPPT regulation voltage will
vary between 17.58V to 17.94V or 78.5% to 80.1% of the
open-circuit voltage.
4.2V
0.04A 2
17V
 2.5V 
2
+ 0.5Ω • 1−
 • 0.04A
 17V 
= 0.19W
+ 0.8Ω •
This dissipated power results in a junction temperature
rise of:
Next, the external feedback divider, RFB1/RFB2, is found
using standard 1% values listed in Table 2.
RFB1 = 2.05MΩ
RFB2 = 845kΩ
PD • ΘJA = 0.19W • 54C°/W = 10.2°C
Estimating IIN(SWITCHING) at 2.5mA from the IIN(SWITCHING)
Current vs Input Voltage graph at VIN = 17V, during
regular charging with VBAT > VTRKL, the power dissipation
reduces to:
PD = 17V • 2.5mA
+ 0.3Ω • 0.4A 2
With these resistors, and including the resistance of the
FBG pin, the battery float voltage is 8.22V.
Select the RUN pin divider to turn on the charger when
the solar-cell output reaches 14.7V. This is obtained by
selecting RRUN1 = 536kΩ, and RRUN2 = 107kΩ. This selection turns off the charger if the input falls below 13.52V.
The switching frequency is selected at 1.5MHz which meets
the minimum on-time requirement for battery voltages
as low as 5V.
4.2V
+ 0.8Ω •
0.4A 2
17V
 4.2V 
2
+ 0.5Ω • 1−
 • 0.4A
 17V 
= 0.18W
tON =
This dissipated power results in a junction temperature
rise of 9.8°C over ambient.
Design Example 2
5V
= 186ns > tMIN(ON)
1.5MHz • 17.94V
The minimum standard inductance value for a 30% ripple
current is
LSW >
(17.94V − 8.2V) • 8.2V
= 24.8µH
1.5MHz • 17.94V • (30% • 400mA)
Consider the design with a 3.5W or greater solar panel with
a maximum input voltage of VOC = 22.4V and a maximum
power voltage of VMP = 18V or 80.3% of the open-circuit
voltage. The minimum battery voltage is 5V, and the float
voltage is 8.2V, with a charge current of 400mA.
The nearest standard inductor value greater than this is
33µH. With an inductor of 33µH, the peak inductor current
is 445mA and the ripple current amplitude, ∆IL, is 90mA.
Select an inductor with a saturation current greater than
the peak inductor current.
The MPPT set point is at 80.3% of the open-circuit voltage. So select
Select RPROG = 3.01k, as the nearest standard 1% value
to provide a charge current of 403mA during constantcurrent operation.
KR = 0.1/0.803 = 0.1245
24
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LTC4121/LTC4121-4.2
APPLICATIONS EXAMPLES
Select a 50V rated capacitor for CIN = 10µF to achieve an
input voltage ripple of 10mV. And select 6V rated capacitors for CINTVCC = 2.2µF, CBOOST = 22nF, and a 10V rated
CBAT = 22µF.
Due to the large float voltage diode D7 is placed in series
with the BAT pin to prevent exceeding the ABS MAX current rating on the RSNS resistor in the event that a fully
charged battery may be connected.
This dissipated power results in a junction temperature
rise of:
PD • ΘJA = 0.077W • 54°C/W = 4.2°C
During regular charging with VBAT = 8.2V, and assuming
VIN is at the MPPT voltage of 17.94V, the power dissipation increases to:
PD = 18V • 4mA
In this design example, maximum power dissipation is
calculated during trickle charge with the following assumptions: VBAT = 5.7V, VIN is 19V, and IIN(SWITCHING) is
estimated from the IIN(SWITCHING) Current vs Input Voltage
graph in the Typical Performance Characteristics section
at VIN = 19V and FREQ = INTVCC as 4mA.
+ 0.3Ω • 0.4A 2
8.2V
0.4A 2
19V
 8.2V 
2
+ 0.5Ω • 1−
 • 0.4A
 19V 
= 0.22W
+ 0.8Ω •
PD = 19V • 4mA
+ 0.3Ω • 0.04A 2
This dissipated power results in a junction temperature
rise of 12°C over ambient.
5.7V
0.04A 2
19V
 5.7V 
2
+ 0.5Ω • 1−
 • 0.04A
 19V 
= 77mW
+ 0.8Ω •
BAT54
VOC = 22.4V, VMP = 18V
CIN
10µF
INTVCC
INTVCC
CINTVCC
2.2µF
FREQ
RRUN1
536k
BOOST
RUN
RMPPT1
715k
+
IN
RRUN2
107k
LTC4121
CBST LSW
22nF 33µH
SW
CHGSNS
SI2343DS
CHRG
MPPT
49.9k
RMPPT2
102k
BAT
4.7µF
+
IN
470k
FB
FAULT
+
RFB1
2.05M
PROG
CBAT
22µF
470k
FBG
GND
VFLOAT = 8.2V
RFB2
845k
10k
NTC
RPROG
3.01k
T
+
Li-Ion
T = NTHS0805N02N1002F
4121 F09
Figure 9. Design Example 2 with LTC4121
4121fc
For more information www.linear.com/LTC4121
25
LTC4121/LTC4121-4.2
APPLICATIONS EXAMPLES
Design Example 3
disable NTC qualified charging and highlight the float voltage programming over a wide temperature range. With an
NTC pin network connected, as in example 1 or example 4,
the charger would be disabled below 0°C or above 40°C.
Consider the design of a sealed lead acid charger with
temperature compensation of the float voltage. Sealed Lead
Acid batteries require the float voltage be decreased as
cell temperature rises. With the LTC4121 this is achieved
using an NTC thermistor in the feedback pin divider as
shown in Figure 10.
The sealed lead acid charger of example 3 is configured
to charge from a variable supply that can range from 6.2V
up to 40V. The switch frequency is selected at 750kHz to
meet minimum on time requirements at VBAT = 4.2V. And
a 47µH switch inductor is selected to keep ripple current
below 30% of ICHG at VIN = 40V.
Using the circuit of Figure 10 above, the float voltage
automatically decreases with temperature as shown in
Figure 11. The NTC pin is grounded in this example to
IN
INTVCC
INTVCC
BOOST
CIN
10µF
RUN
CBST
22nF
SW
LTC4121
CHGSNS
VFLOAT = 6V
BAT
CFF
1nF
MPPT
VIN
NTC
RFB1C
102k
RFB1B
464k
FB
PROG
RT1
100k
+
SLA
RFB2
698k
FREQ
GND
CBAT
22µF
RFB1A
866k
RMPPT1
10k
+
–
CINTVCC
2.2µF
LSW
47µH
FBG
RPROG
3.01k
RT1 = NTHS0402E3104FHT
4121 F10
Figure 10. Design Example 3, SLA Charging with LTC4121
7.0
6.8
NTC = GND
6.6
VFLOAT (V)
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
4121 F11
Figure 11. Sealed Lead Acid Float Voltage
26
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
APPLICATIONS EXAMPLES
Design Example 4
VBAT = 4.2V. And above 28.3V, the charger attains the full
programmed charge current of 400mA so MPPT regulation lets go. While the LTC4121 regulates VIN, the battery
charge current is automatically scaled to track available
input power. Figure 13 illustrates the circuit performance
measured with VBAT held at 4.0V, showing the ratio of
VMP/VOC and IBAT versus VOC with RIN = 100Ω in series
with the supply.
Consider the design of a Li-Ion charger from a resistive
supply. With a resistive supply voltage, the maximum
power point is at 50% of the open-circuit voltage. Program
a 50% peak power point using KR = 0.199 with RMPPT1 =
332k and RMPPT2 = 82.5k. This network keeps the input
voltage at the peak power point for any input resistance
so long as the R-C time constant of RIN • CIN does not
exceed PWMP/5, here CIN is 22µF.
LSW is sized to maintain ripple current below 30% of ICHG
at VIN = 16V. The FB pin network is programmed to set
VFLOAT = 4.2V. An NTC network is configured to enable
charging when the battery temperature is between 0°C
and 40°C.
With 100Ω of source impedance, the input voltage regulation loop holds the ratio of (VMP/VIN) at about 49% for
VIN ranging from 9V up to 28.3V. For lower input voltages
than 8.7V, the MPPT set point is below DUVLO when
VMP
IN
INTVCC
INTVCC
BOOST
CIN
22µF
RUN
SW
CHGSNS
LTC4121
VFLOAT = 4.2V
BAT
RFB1
1.01M
RMPPT1
332k
MPPT
RIN
+
CINTVCC
2.2µF
CBST LSW
22nF 33µH
CBAT
22µF
FB
RFB2
1.35M
RMPPT2
82.5k
10k
FBG
VIN
–
FREQ
GND
PROG
NTC
Li-Ion
+
RPROG
3.01k
T = NTCS0402E3103FHT
T
4121 F12
Figure 12. Design Example 4, LTC4121 2-Cell Li-Ion Charger with MPPT Tracking for a Resistive Supply
100
90
400
80
350
70
300
60
250
50
200
40
150
30
100
20
50
10
5
10
15
20
25
VIN(OC) (V)
30
35
40
I BAT (mA)
VMP / VOC (%)
450
VBAT = 4V
RIN = 100Ω
0
4121 F13
Figure 13. VMP/VOC and IBAT vs VIN(OC)
4121fc
For more information www.linear.com/LTC4121
27
LTC4121/LTC4121-4.2
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4121#packaging for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
0.70 ±0.05
3.50 ±0.05
1.45 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
15
PIN 1
TOP MARK
(NOTE 6)
16
0.40 ±0.10
1
1.45 ± 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
28
0.25 ±0.05
0.50 BSC
4121fc
For more information www.linear.com/LTC4121
LTC4121/LTC4121-4.2
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/15
Clarified device options.
Clarified Note 4.
Modified End-of-Charge Indication section.
Enhanced Reverse Blocking section.
Modified Related Parts list.
B
C
11/15
02/16
PAGE NUMBER
Added Note 5 reference to INTVCC UVLO spec.
1
5
15
20-21
28
3
Expanded INTVCC Pin Function description.
8
Enhanced Figure 8.
21
Enhanced Figure 9.
25
Enhanced Figure 10.
26
Modified Figure 1.
10
Modified Figure 9. Made all GND symbols the same.
25
Modified Figure 14. Added LTC4070 to Related Parts.
30
4121fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC4121
29
LTC4121/LTC4121-4.2
TYPICAL APPLICATION
470k
470k
VOC = 21.6V, VMP = 17V
CIN
10µF
IN
CHRG
FAULT
RRUN1
464k
BOOST
RUN
+
RMPPT1
698k
LTC4121-4.2
RRUN2
107k
INTVCC
INTVCC
SW
CBST
22nF LSW
47µH
CHGSNS
BAT
BATSNS
+
MPPT
RMPPT1
100k
CINTVCC
2.2µF
VFLOAT = 4.2V
CBAT
22µF
10k
NTC
GND
PROG
+
FREQ
RPROG
3.01k
T
+
Li-Ion
T = NTHS0805N02N1002F
4121 TA02
Figure 14. Design Example 1 with LTC4121-4.2
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3650-4.1/
LT3650-4.2
Monolithic 2A Switch Mode
Non-Synchronous 1-Cell Li-Ion Battery
Charger
Standalone 4.75V < VIN < 32V (40V Absolute Maximum), 1MHz, 2A Programmable Charge
Current, Timer or C/10 Termination, Small and Few External Components 3mm × 3mm DFN-12
Package “-4.1” for 4.1V Float Voltage Batteries, “-4.2” for 4.2V Float Voltage Batteries.
LT3652HV
Power Tracking 2A Battery Charger
Input Supply Voltage Regulation Loop for Peak Power Tracking in (MPPT) Solar Applications,
4.95V < VIN < 34V (40V Absolute Maximum), 1MHz, 2A Charge Current, 3.3V < VOUT < 18V.
Timer or C/10 Termination, 3mm × 3mm DFN-12 Package and MSOP-12 Packages.
LTC4070
Li-Ion/Polymer Shunt Battery Charger
Low 450nA Operating Current, 50mA Internal Shunt Current (500mA with External PFET)
LTC4071
Li-Ion/Polymer Shunt Battery Charger
System with Low Battery Disconnect
Integrated Pack Protection, < 10nA Low Battery Disconnect Protects Battery from
Over-Discharge. Low Operating Current (550nA), 1% Float Voltage Accuracy Over Full
Temperature and Shunt Current Range, 50mA Maximum Internal Shunt Current, Pin Selectable
Float Voltages: 4.0V, 4.1V, 4.2V. Ultralow Power Pulsed NTC Float Conditioning for Li-Ion/
Polymer Protection, 8-Lead (2mm × 3mm) DFN and MSOP.
LTC4065/
LTC4065A
Standalone Li-Ion Battery Charger in
2mm × 2mm DFN
4.2V ±0.6% Float Voltage, Up to 750mA Charge Current; “A” Version Has /ACPR Function.
2mm × 2mm DFN Package.
LTC4079
60V 250mA Multi-Chemistry Linear
Battery Charger
2.7V – 60V Input Voltage range, 1.2V – 60V Adjustable Battery Voltage Range and 10mA
– 250mA Charge Current Range. Low 4µA Quiescent Current. Input Voltage and Thermal
Regulation. 10-pin 3mm x 3mm DFN package.
LTC4015
Multi-Chemistry Buck Battery Charger
Multi-Chemistry Li-Ion/Polymer, LiFePO4, or Lead-Acid Battery Charger with Termination, Digital
Controller with Digital Telemetry System Telemetry System Monitors VBAT, IBAT, RBAT,NTC Ratio (Battery Temperature), VIN, IIN, VSYSTEM,
Die Temperature, Coulomb Counter and Integrated 14-Bit ADC, Wide Charging Input Voltage
Range: 4.5V to 35V, Wide Battery Voltage Range: Up to 35V, 5mm × 7mm QFN-38 Package
LTC4020
55V Buck-Boost Multi-Chemistry Battery Wide Voltage Range: 4.5V to 55V Input, Up to 55V Output (60V Absolute Maximums),
Charger
Synchronous Buck-Boost DC/DC Controller, Li-Ion and Lead-Acid Charge Algorithms, Input
Voltage Regulation for High Impedance Input Supplies and Solar Panel Peak Power Operation,
Low Profile (0.75mm) 38-Pin 5mm × 7mm QFN Package
LTC4001
2A Synchronous Buck Li-Ion Charger
Low Power Dissipation, 2A Maximum Charge Current, No External MOSFETs, Sense Resistor
or Blocking Diode Required, Programmable Charge Termination Timer, Preset 4.2V Float
Voltage with ±0.5% Accuracy, Low Profile 16-Lead (4mm × 4mm) QFN Package
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4121
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC4121
4121fc
LT 0216 REV C • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2014