Cypress CY62167E 16-mbit (1m x 16 / 2m x 8) static ram Datasheet

CY62167E MoBL®
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
•
•
•
•
(CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH).
The input and output pins (IO0 through IO15) are placed in a
high impedance state when:
• The device is deselected (CE1 HIGH or CE2 LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• A write operation is in progress (CE1 LOW, CE2 HIGH, and
WE LOW)
Configurable as 1M x 16 or as 2M x 8 SRAM
Very high speed: 45 ns
Wide voltage range: 4.5V–5.5V
Ultra low standby power
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
• Ultra low active power
•
•
•
•
— Typical active current: 2.2 mA @ f = 1 MHz
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in 48-pin TSOP I package
Functional Description[1]
The CY62167E is a high performance CMOS static RAM
organized as 1M words by 16 bits/2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7), is
written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data
from the IO pins (IO8 through IO15) is written into the location
specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW,
then data from memory appears on IO8 to IO15. See the “Truth
Table” on page 10 for a complete description of read and write
modes.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
1M × 16 / 2M x 8
RAM ARRAY
IO0–IO7
IO8–IO15
COLUMN DECODER
BYTE
BHE
WE
CE2
BHE
OE
CE1
BLE
BLE
CE2
CE1
A11
A12
A13
A14
A15
A16
A17
A18
A19
POWER DOWN
CIRCUIT
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-15607 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 07, 2007
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CY62167E MoBL®
Pin Configuration[2, 3]
48-Pin TSOP I Top View
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
IO15/A20
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE1
A0
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62167ELL
Min
Typ[4]
Max
4.5
5.0
5.5
45
Standby ISB2 (µA)
f = fmax
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
2.2
4.0
25
30
1.5
12
Notes
2. NC pins are not connected on the die.
3. The BYTE pin in the 48-TSOPI package must be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM
by tying the BYTE signal to VSS. In the 2M x 8 configuration, pin 45 is A20, while BHE, BLE and IO8 to IO14 pins are not used.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 001-15607 Rev. *A
Page 2 of 12
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CY62167E MoBL®
DC Input Voltage[5, 6] ........................................–0.5V to 6.0V
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life
of the device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground
Potential ........................................................... –0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State[5, 6] ........................................... –0.5V to 6.0V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Device
CY62167ELL
Range
Ambient
Temperature
VCC[7]
Industrial –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –1.0 mA
VOL
Output LOW Voltage
IOL = 2.1mA
VIH
Input HIGH Voltage
VCC = 4.5V to 5.5V
45 ns
Min
Typ[4]
Unit
Max
2.4
V
0.4
V
2.2
VCC + 0.5V
V
–0.5
0.7[8]
V
VIL
Input LOW Voltage
VCC = 4.5V to 5.5V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
25
30
mA
2.2
4.0
mA
1.5
12
µA
ISB2[9]
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V,
Current—CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
Capacitance[10]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance[10]
Parameter
Description
ΘJA
Thermal Resistance
(junction to ambient)
ΘJC
Thermal Resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
TSOP I
Unit
60
°C/W
4.3
°C/W
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full Device AC operation is based on a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.
8. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V.
9. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be
left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-15607 Rev. *A
Page 3 of 12
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CY62167E MoBL®
AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
GND
30 pF
R2
10%
ALL INPUT PULSES
90%
90%
10%
FALL TIME= 1 V/ns
RISE TIME= 1 V/ns
INCLUDING
JIG AND
SCOPE
EQUIVALENT TO: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Values
Unit
R1
1800
Ω
R2
990
Ω
RTH
639
Ω
VTH
1.77
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR[9]
Data Retention Current
tCDR[10]
Chip Deselect to Data
Retention Time
tR[11]
Operation Recovery
Time
Min
Typ[4]
Max
Unit
12
µA
2.0
V
VCC= VDR
CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
0
ns
tRC
ns
Data Retention Waveform[12]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 2.0 V
VCC(min)
tR
CE1 or
BHE. BLE
or
CE2
Notes
11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
12. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE.
Document #: 001-15607 Rev. *A
Page 4 of 12
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CY62167E MoBL®
Switching Characteristics
Over the Operating Range[13, 14]
Parameter
Description
45 ns
Min
Max
Unit
READ CYCLE
tRC
Read Cycle Time
45
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
45
LOW-Z[15]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[15, 16]
ns
10
ns
ns
5
ns
18
ns
CE1 LOW and CE2 HIGH to
Low-Z[15]
tHZCE
CE1 HIGH and CE2 LOW to
High-Z[15, 16]
tPU
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power Down
45
ns
tDBE
BLE/BHE LOW to Data Valid
45
ns
tLZCE
tLZBE
tHZBE
BLE/BHE LOW to
Low-Z[15]
BLE/BHE HIGH to
HIGH-Z[15, 16]
10
ns
18
0
ns
ns
10
ns
18
ns
WRITE CYCLE[17]
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[15, 16]
WE HIGH to Low-Z
[15]
18
10
ns
ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
Document #: 001-15607 Rev. *A
Page 5 of 12
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CY62167E MoBL®
Switching Waveforms
Figure 1 shows address transition controlled read cycle waveforms.[18, 19]
Figure 1. Read Cycle No. 1
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 2 shows OE controlled read cycle waveforms.[19, 20]
Figure 2. Read Cycle No. 2
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 001-15607 Rev. *A
Page 6 of 12
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 3 shows WE controlled write cycle waveforms.[17, 21, 22]
Figure 3. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 23
VALID DATA
tHZOE
Notes
21. Data IO is high impedance if OE = VIH.
22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
23. During this period the IOs are in output state and input signals must not be applied.
Document #: 001-15607 Rev. *A
Page 7 of 12
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22]
Figure 4. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tHD
tSD
NOTE 23
VALID DATA
tHZOE
Figure 5 shows WE controlled, OE LOW write cycle waveforms.[22]
Figure 5. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
tHA
tPWE
WE
tSD
DATA IO
NOTE 23
VALID DATA
tHZWE
Document #: 001-15607 Rev. *A
tHD
tLZWE
Page 8 of 12
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CY62167E MoBL®
Switching Waveforms (continued)
Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22]
Figure 6. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA IO
NOTE 23
Document #: 001-15607 Rev. *A
tHD
VALID DATA
Page 9 of 12
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CY62167E MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
L
H
L
Inputs Outputs
Mode
Power
High-Z
Deselect/Power Down
Standby (ISB)
X
High-Z
Deselect/Power Down
Standby (ISB)
H
H
High-Z
Deselect/Power Down
Standby (ISB)
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
H
L
H
L
Data Out (IO0–IO7);
High-Z (IO8–IO15)
Read
Active (ICC)
H
H
L
L
H
High-Z (IO0–IO7);
Data Out (IO8–IO15)
Read
Active (ICC)
L
H
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (IO0–IO7);
High-Z (IO8–IO15)
Write
Active (ICC)
L
H
L
X
L
H
High-Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
Ordering Code
CY62167ELL-45ZXI
Document #: 001-15607 Rev. *A
Package
Diagram
51-85183
Package Type
48-pin TSOP I (Pb-free)
Operating
Range
Industrial
Page 10 of 12
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CY62167E MoBL®
Package Diagram
Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
0.037[0.95]
0.041[1.05]
N
1
0.020[0.50]
TYP.
0.472[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.724 [18.40]
0.047[1.20]
MAX.
SEATING PLANE
0.004[0.10]
0.787[20.00]
0.004[0.10]
0.008[0.21]
0.010[0.25]
GAUGE PLANE
0°-5°
0.020[0.50]
0.028[0.70]
Document #: 001-15607 Rev. *A
51-85183-*A
Page 11 of 12
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their
respective holders.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only
in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except
as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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CY62167E MoBL®
Document History Page
Document Title: CY62167E MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM
Document Number: 001-15607
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
1103145
See ECN
VKN
New Data Sheet
*A
1138903
See ECN
VKN
Converted from preliminary to final
Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1MHz
Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax
Changed ICC(max) spec from 25 mA to 30 mA for f=fmax
Added footnote# 8 related to VIL
Changed ICCDR spec from 10 µA to 12 µA
Added footnote# 14 related to AC timing parameters
Document #: 001-15607 Rev. *A
Page 12 of 12
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