ispLSI 5512VA ® In-System Programmable 3.3V SuperWIDE™ High Density PLD — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Features • SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells — Up to 288 I/O Pins — 512 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Input Bus Generic Logic Block Input Bus Generic Logic Block Generic Logic Block Input Bus Global Routing Pool (GRP) Boundary Scan Interface Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE Input Bus Generic Logic Block Input Bus • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging Input Bus Generic Logic Block Generic Logic Block • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 110 MHz Maximum Operating Frequency — tpd = 8.5 ns Propagation Delay — Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization Input Bus Functional Block Diagram ispLSI 5000V Description The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Slew and Skew Programmable I/O (SASPI/O™) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options — Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and five extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 5512va_04 1 September 2000 Specifications ispLSI 5512VA Functional Block Diagram TMS TCK I/O 219 I/O 218 I/O 217 I/O 216 I/O 233 I/O 232 I/O 231 I/O 230 I/O 237 I/O 236 I/O 235 I/O 234 I/O 251 I/O 250 I/O 249 I/O 248 I/O 255 I/O 254 I/O 253 I/O 252 I/O 269 I/O 268 I/O 267 I/O 266 Generic Logic Block Generic Logic Block Input Bus Generic Logic Block Boundary Scan Interface Generic Logic Block Generic Logic Block Input Bus Input Bus Global Routing Pool (GRP) Generic Logic Block Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus 1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is determined by the package type used – see table below. Package Type 388 BGA 272 BGA 208 PQFP I/O 179 / CLK2 I/O 119 / CLK2 I/O 89 / CLK2 Multiplexed Signals I/O 197 / CLK3 I/O 0 / TOE I/O 131 / CLK 3 I/O 0 / TOE I/O 98 / CLK 3 I/O 0 / TOE 2 1CLK 2 1CLK 3 CLK 0 CLK 1 I/O 140 I/O 141 I/O 142 I/O 143 I/O 126 I/O 127 I/O 128 I/O 129 I/O 122 I/O 123 I/O 124 I/O 125 I/O 108 I/O 109 I/O 110 I/O 111 I/O 104 I/O 105 I/O 106 I/O 107 I/O 90 I/O 91 I/O 92 I/O 93 I/O 86 I/O 87 I/O 88 I/O 89 I/O 72 I/O 73 I/O 74 I/O 75 GSET/GRST Input Bus I/O 68 I/O 69 I/O 70 I/O 71 Generic Logic Block Generic Logic Block I/O 54 I/O 55 I/O 56 I/O 57 Generic Logic Block Input Bus I/O 50 I/O 51 I/O 52 I/O 53 Generic Logic Block Generic Logic Block I/O 36 I/O 37 I/O 38 I/O 39 Input Bus Input Bus I/O 32 I/O 33 I/O 34 I/O 35 Input Bus Generic Logic Block I/O 18 I/O 19 I/O 20 I/O 21 Input Bus Input Bus I/O 14 I/O 15 I/O 16 I/O 17 Input Bus Generic Logic Block 1I/O 0 / TOE I/O 1 I/O 2 I/O 3 Input Bus VCCIO I/O 273 I/O 272 I/O 271 I/O 270 I/O 287 I/O 286 I/O 285 I/O 284 GOE1 GOE0 Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option) TDI TDO I/O 215 I/O 214 I/O 213 I/O 212 I/O 201 I/O 200 I/O 199 I/O 198 I/O 197/CLK3 I/O 196 I/O 195 I/O 194 I/O 183 I/O 182 I/O 181 I/O 180 I/O 179/CLK2 I/O 178 I/O 177 I/O 176 I/O 165 I/O 164 I/O 163 I/O 162 I/O 161 I/O 160 I/O 159 I/O 158 I/O 147 I/O 146 I/O 145 I/O 144 Specifications ispLSI 5512VA 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows the output drivers to drive either 3.3V or 2.5V output levels while the device logic and the output current drive is always powered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. ispLSI 5000V Description (Continued) The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The five extra product terms are used for shared GLB controls, set, reset, clock, clock enable and output enable. The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, which can be fed back through the Global Routing Pool. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. The ispLSI 5000V Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term signals. The macrocell register can be programmed to operate as a Dtype register, a D-type latch or a T-type flip flop. ispLSI 5000V Family Members The ispLSI 5000V Family ranges from 256 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000V Family device matrix showing the various bondout options is shown in the table below. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one line from each macrocell output and one line from each I/O pin. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source Table 1. ispLSI 5000VA Family Package Type Device GLBs Macrocells 208 fpBGA 208 PQFP 272 BGA 388 BGA ispLSI 5256VA 8 256 144 I/O 144 I/O 192 I/O — ispLSI 5384VA 12 384 144 I/O 144 I/O 192 I/O 288 I/O ispLSI 5512VA 16 512 — 144 I/O 192 I/O 288 I/O 3 Specifications ispLSI 5512VA Figure 2. ispLSI 5512VA Block Diagram (288 I/O Version) 18 I/O 18 18 32 32 32 18 32 Q 32 D D 160 Global Routing Pool (GRP) 160 18 18 32 32 32 18 32 Q 18 18 32 32 32 32 Q 160 160 Q 18 18 32 32 160 160 Q 18 18 32 32 5 5 18 I/O TOE 32 D D Q 32 18 160 160 5 PT 18 68 32 32 32 5 PT 160 PT 68 18 Q 160 160 PT 18 I/O 18 I/O D 800 160 5 5 32 D 5 PT 18 68 32 32 32 5 PT 160 PT 68 18 Q 160 160 PT 18 I/O 18 I/O D 160 5 5 32 D 5 PT 18 68 68 18 32 5 PT 160 160 CLK3 Q 160 160 PT 160 PT 18 I/O Buffers/Pins 18 I/O D 160 5 5 32 D 5 PT Generic Logic Block (GLB) 18 68 68 CLK2 32 5 PT 160 PT 160 18 I/O Q 160 160 PT 5 PT 5 18 I/O 160 PT 160 PT 160 160 68 68 4 5 PT 5 5512_384 CLK0 CLK1 GOE0 GOE1 SET/RESET Specifications ispLSI 5512VA Figure 3. ispLSI 5000V Generic Logic Block (GLB) From Global Routing Pool 0 1 2 66 67 Global PTOE Bus PTSA Macrocell 0 PT 0 PT 1 From PTSA PTSA bypass PT 2 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 3 PT 4 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 1 PT 9 PT 8 From PTSA PTSA bypass PT 7 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 6 PT 5 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 15 PT 79 PT 78 From PTSA PTSA bypass PT 77 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 76 PT 75 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 31 PT 159 PT 158 From PTSA PTSA bypass PT 157 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 156 PT 155 PT 160 PT 161 Shared PT Clock 0 Shared PT (P)reset 0 PT 162 PT 163 Shared PT Clock 1 Shared PT (P)reset 1 6 PT 164 To GRP Global PTOE 0 ... 5 GLB_5K Programmable AND Array 5 Specifications ispLSI 5512VA Figure 4. ispLSI 5000V Macrocell VCCIO Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 Global PTOE 4 Global PTOE 5 PTOE VCC VCCIO GOE0 GOE1 TOE PTSA bypass I/O Pad Delay D PTSA PT Clock Q D/T Shared PT Clock 0 Shared PT Clock 1 Slew Open rate drain 2.5V/3.3V Output Clk En To GRP R/L CLK0 CLK1 CLK2 CLK3 Clk R P PT Reset D D Q Q SET/RESET PT Preset D/T Clk En Clk Shared PT (P)reset 0 Shared PT (P)reset 1 Programmable Speed/Power Option Register/ Latch R P 6 Specifications ispLSI 5512VA speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but also is available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options. Global Clock Distribution The ispLSI 5000V Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock Figure 5. ispLSI 5000V Global Clock Structure CLK 0 CLK0 CLK 1 CLK1 IO/CLK 2 To GRP CLK2 CLK3 IO/CLK 3 To GRP GSET/GRST SET/RESET 7 Specifications ispLSI 5512VA Figure 6. Boundary Scan Register Circuit for I/O Pins HIGHZ EXTEST SCANIN (from previous cell) BSCAN Registers D Q TOE BSCAN Latches D Normal Function OE Q 0 1 EXTEST PROG_MODE Normal Function Shift DR D Q D Q Clock DR D 0 I/O Pin 1 Q SCANOUT (to next cell) Update DR Reset Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell) D Shift DR Clock DR 8 Q SCANOUT (to next cell) Specifications ispLSI 5512VA Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch Tbth Tbtcl Tbtcp TCK Tbtvo Tbtco TDO Valid Data Tbtcpsu Data to be captured Tbtoz Valid Data Tbtcph Data Captured Tbtuov Tbtuco Data to be driven out Valid Data SYMBOL PARAMETER Tbtuoz Valid Data MIN MAX UNITS tbtcp TCK [BSCAN test] clock pulse width 125 – ns tbtch tbtcl TCK [BSCAN test] pulse width high 62.5 – ns TCK [BSCAN test] pulse width low 62.5 – ns tbtsu TCK [BSCAN test] setup time 25 – ns tbth TCK [BSCAN test] hold time 25 – ns trf TCK [BSCAN test] rise and fall time 50 – mV/ns 25 ns tbtco TAP controller falling edge of clock to valid output – tbtoz TAP controller falling edge of clock to data output disable – 25 ns tbtvo TAP controller falling edge of clock to data output enable – 25 ns tbtcpsu BSCAN test Capture register setup time 25 – ns tbtcph BSCAN test Capture register hold time 25 – ns tbtuco BSCAN test Update reg, falling edge of clock to valid output – 50 ns tbtuoz BSCAN test Update reg, falling edge of clock to output disable – 50 ns tbtuov BSCAN test Update reg, falling edge of clock to output enable – 50 ns 9 Specifications ispLSI 5512VA Absolute Maximum Ratings 1, 2 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL MIN. MAX. UNITS Commercial TA = 0°C to +70°C 3.00 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V 2.3 3.60 PARAMETER VCC Supply Voltage VCCIO I/O Reference Voltage V Table 2 - 0005/5000 Capacitance (TA=25°C,f=1.0 MHz) SYMBOL C1 C2 C3 PARAMETER I/O Capacitance TYPICAL UNITS 10 pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V Clock Capacitance 10 pf VCC = 3.3V, VCK = 2.0V Global Input Capacitance 10 pf VCC = 3.3V, VG = 2.0V Table 2 - 0006/5384 Erase Reprogram Specification PARAMETER ispLSI Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 10000 – Cycles Table 2-0008/3320 10 Specifications ispLSI 5512VA Switching Test Conditions Figure 9. Test Load Input Pulse Levels GND to VCCIOmin ≤ 1.5ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load VCCIO R1 See figure Device Output Table 2 - 0003/5384 3-state levels are measured 0.5V from steady-state active level. Test Point CL* R2 Output Load Conditions (See Figure 8) 3.3V R1 R2 R1 316Ω 348Ω 511Ω 475Ω 35pF Active High ∞ 348Ω ∞ 475Ω 35pF Active Low 316Ω ∞ 511Ω ∞ 35pF Active High to Z at VOH -0.5V ∞ 348Ω ∞ 475Ω 5pF Active Low to Z at VOL+0.5V 316Ω ∞ 511Ω ∞ 5pF ∞ ∞ ∞ ∞ 35pF TEST CONDITION A B C D *CL includes Test Fixture and Probe Capacitance. 2.5V Slow Slew R2 0213D CL Table 2 - 0004A/5384 DC Electrical Characteristics for 3.3V Range1 Over Recommended Operating Conditions SYMBOL VCCIO VIL VIH VOL VOH PARAMETER CONDITION I/O Reference Voltage MIN. TYP. MAX. UNITS 3.0 – 3.6 V Input Low Voltage VOH ≤ VOUT or VOUT ≤ VOL (max) -0.3 – 0.8 V Input High Voltage VOH ≤ VOUT or VOUT ≤ VOL (max) 2.0 – 5.25 V Output Low Voltage IOL = 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V Table 2-0007/5512VA 1. I/O voltage configuration must be set to VCC. 11 Specifications ispLSI 5512VA DC Electrical Characteristics for 2.5V Range1 Over Recommended Operating Conditions SYMBOL VCCIO VIL VIH I/O Reference Voltage VOL Output Low Voltage VOH CONDITION PARAMETER MIN. TYP. MAX. UNITS 2.3 – 2.7 V Input Low Voltage VOH(min) ≤ VOUT or VOUT ≤ VOL(max) -0.3 – 0.7 V Input High Voltage VOH(min) ≤ VOUT or VOUT ≤ VOL(max) 1.7 – 5.25 V VCCIO=min, VIN=VIH or VIL, IOL= 100µA – – 0.2 V VCCIO=min, VIN=VIH or VIL, IOL= 2mA Output High Voltage – – 0.7 V VCCIO=min, VIN=VIH or VIL, IOH= -100µA 2.1 – – V VCCIO=min, VIN=VIH or VIL, IOH= -2mA 1.7 – – V 2.5V/5512VA 1. I/O voltage configuration must be set to VCCIO. DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL IIL IIH 1 IPU IBHL IBHH IBHLO IBHLH IBHT IVCCIO CONDITION PARAMETER MIN. TYP. MAX. UNITS Input or I/O Low Leakage Current 0V ≤ VIN≤ VIL(Max.) – – -10 µA Input or I/O High Leakage Current (VCCIO-0.2)V ≤ VIN ≤ VCCIO – – 10 µA VCCIO ≤ VIN ≤ 5.25V – – 50 µA I/O Active Pullup Current 0V ≤ VIN ≤ VIL – – -150 µA Bus Hold Low Sustaining Current VIN = VIL(max) 40 – – µA Bus Hold High Sustaining Current – – µA Bus Hold Low Overdrive Current VIN = VIH(min) 0V ≤ VIN ≤ VCCIO -40 – – 550 µA Bus Hold High Overdrive Current 0V ≤ VIN ≤ VCCIO Bus Hold Trip Points Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax) 1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions. 12 – – -550 µA VIL – VIH V – – 45 mA DC Char_5512VA Specifications ispLSI 5512VA External Switching Characteristics Over Recommended Operating Conditions -110 3 PARAM. TEST # COND. tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 DESCRIPTION 4,5 -100 -70 MIN. MAX. MIN. MAX. MIN. MAX. — A 1 Data Prop. Delay, 5PT Bypass A 2 Data Propagation Delay — 10 — 13 — 19 ns A 3 Clock Frequency with Internal Feedback1 110 — 100 — 70 — MHz — 4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 91 — 69 — 45 — MHz 2 8.5 — 10 — 15 UNITS ns — 5 Clock Frequency, Max Toggle 143 — 125 — 83 — MHz — 6 GLB Reg. Setup Time before Clk, 5PT bypass 6 — 8 — 12 — ns A 7 GLB Reg. Clock to Output Delay — 4 — 5.5 — 8 ns — 8 GLB Reg. Hold Time after Clock, 5PT bypass 0 — 0 — 0 — ns — 9 GLB Reg. Setup Time before Clock 7 — 9 — 14 — ns — 10 GLB Reg. Hold Time after Clock 0 — 0 — 0 — ns tsu3 (CLK0/1) — 11 GLB Reg. Setup Time before Clock, Input Reg. Path (CLK0/1) 4.5 — 6 — 9 — ns tsu3 (CLK2/3) — 12 GLB Reg. Setup Time before Clock, Input Reg. Path (CLK2/3) 3.5 — 5 — 7 — ns th3 (CLK0/1) — 13 GLB Reg. Hold Time after Clock, Input Reg. Path (CLK0/1) 0 — 0 — 0 — ns th3 (CLK2/3) — 14 GLB Reg. Hold Time after Clock, Input Reg. Path (CLK2/3) 0 — 0 — 0 — ns tr1 trw1 tptoe/dis tgptoe/dis tgoe/dis twh twl A 15 Ext. Reset Pin to Output Delay — 17 — 20 — 30 ns 1. 2. 3. 4. 5. 6. — 16 Ext. Reset Pulse Duration 7.5 — 9 — 14 — ns B/C 17 Local Product Term Output Enable/Disable — 10 — 12 — 18 ns B/C 18 Global Product Term Output Enable/Disable — 20 — 24 — 30 ns B/C 19 Global OE Input to Output Enable/Disable — 6.5 — 8 — 12 ns — 20 Ext. Sync. Clock Pulse Duration, High 3.5 — 4 — 6 — ns — 21 Ext. Sync. Clock Pulse Duration, Low 3.5 — 4 — 6 — ns Standard 32-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, and CLK0. Timing parameters measured using normal active output driver. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Timing Ext.5512VA/4.0.eps 13 Specifications ispLSI 5512VA Internal Timing Parameters1 Over Recommended Operating Conditions PARAM #2 -110 -100 -70 MIN MAX MIN MAX MIN MAX DESCRIPTION UNIT I/O Buffer tidcom tidreg todcom todreg todz tslf tsls tslfd tslsd 22 Input Pad and Buffer, Combinatorial Input – 0.7 – 0.9 – 1.4 ns 23 Input Pad and Buffer, Registered Input – 4.7 – 6.6 – 9.7 ns 24 Output Pad and Buffer, Combinatorial Output – 2.4 – 1.7 – 2.6 ns 25 Output Pad and Buffer, Registered Output – 1.0 – 2.8 – 4.6 ns 26 Output Buffer Enable/Disable – 1.7 – 1.7 – 2.6 ns 27 Slew Rate Adder, Fast Slew – 0 – 0 – 0 ns 28 Slew Rate Adder, Slow Slew – 8.5 – 10 – 15 ns 29 Programmable Delay Adder, Fast Slew – 0.5 – 0.7 – 1 ns 30 Programmable Delay Adder, Slow Slew – 9.5 – 10.7 – 16 ns Macrocell Register/Latch Bypass – 0 – 0 – 0 ns 32 Macrocell Latch Delay – 1 – 1.4 – 2 ns 33 Macrocell Register/Latch Clock to Output – 1.8 – 1 – 1 ns 34 Macrocell Register/Latch Setup Time 1 – 1.1 – 1.7 – ns 35 Macrocell Register/Latch Hold Time 2.5 – 3.9 – 5.3 – ns 36 Macrocell Register/Latch CLKEN Setup Time 1 – 1.4 – 2 – ns 37 Macrocell Register/Latch CLKEN Hold Time 1 – 1.4 – 2 – ns 38 Macrocell Register/Latch Set/Reset Time – 1.8 – 1.4 – 2 ns 39 Toggle Flip-Flop Feedback – 1 – 1.3 – 2 ns 40 AND Array, High Speed Mode – 3 – 4 – 6 ns 41 AND Array, Low Power Mode – 5 – 6.6 – 10 ns 42 5 Product Term Bypass, Combinatorial – 0.7 – 1.4 – 2 ns 43 5 Product Term Bypass, Registered – 1 – 1.7 – 2.3 ns 44 5 Product Term XOR, Combinatorial – 2.5 – 3.6 – 5 ns 45 5 Product Term XOR, Registered – 2.3 – 2.2 – 3.3 ns 46 Product Term Sharing Array, Combinatorial – 3 – 4.1 – 6 ns 47 Product Term Sharing Array, Registered – 2 – 2.7 – 4.3 ns 48 Product Term Clock Delay – 0.5 – 0.7 – 1 ns GLB/Macrocell Delay Register tmbp tmlat tmco tmsu tmh tmsuce tmhce tmrst tftog 31 AND Array tandhs tandlp PTSA t5ptcom t5ptreg t5ptxcom t5pxtreg tptsacom tptsareg PTSA Controls tpck tpcken tscken tsck tptsacken tsrst tprst tpoe tgpoe 49 Product Term CLKEN Delay – 1 – 1.4 – 2 ns 50 Shared Product Term CLKEN Delay – 1 – 1.4 – 2 ns 51 Shared Product Term Clock Delay – 0.5 – 0.7 – 1 ns 52 Product Term Sharing Array CLKEN Delay – 2.0 – 2.4 – 4 ns 53 Shared Product Term Set/Reset Delay – 2.5 – 3.4 – 5 ns 54 Product Term Set/Reset Delay – 1.5 – 2 – 3 ns 55 Product Term Output Enable/Disable – 2.9 – 3.4 – 5 ns 56 Global PT Output Enable/Disable – 13.1 – 15.4 – 17 ns 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 14 Timing Rev 4.0 Specifications ispLSI 5512VA Internal Timing Parameters1 Over Recommended Operating Conditions PARAM #2 -110 -100 -70 MIN MAX MIN MAX MIN MAX DESCRIPTION UNIT GRP tgrpi tgrpm 57 GRP Delay from I/O Pad – 1.5 – 2 – 3 ns 58 GRP Delay from Macrocell – 1.2 – 1.2 – 1.2 ns Global Control Delays tgclk01 tgclk23 tgclken0 tgclken1 tgrst tgoe ttoe 59 Global Clock 0 or 1 Delay – 1.2 – 1.7 – 2.4 ns 60 Global Clock 2 or 3 Delay – 2.2 – 2.7 – 4.4 ns 61 Global CLKEN 0 Delay – 1.7 – 2.4 – 3.4 ns 62 Global CLKEN 1 Delay – 2.7 – 3.4 – 5.4 ns 63 Global Set/Reset Delay – 14.2 – 15.8 – 23.4 ns 64 Global OE Delay – 4.8 – 6.3 – 9.4 ns 65 Test OE Delay – 4.7 – 6.2 – 9.4 ns 1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. Timing Rev 4.0 ispLSI 5512VA Timing Model Input Buffer I/O Pad INPUT #20 tidcom tidreg #56 tgrpm #55 tgrpi PTSA #40 t5ptcom #44 tptsacom #42 t5ptxcom #41 t5ptxreg #45 tptsareg #43 t5ptreg AND Array #31 #35 #34 tandhs tandlp #39 Register #29 tmbp #30 tmlat #32 tmsu #33 tmh #38 Input Pad Buffer Delays #37 tftog #21 Dedicated Input Buffers #57 tgclk0 #58 tgclk123 #59 tgclken0 #60 tgclken1 #61 tgrst #62 tgoe #63 ttoe Output Buffer GLB/Macrocell GRP tmco tmhce tmsuce #36 tmrst PT Controls #49 tsck #46 tpck #50 tptsacken #47 tpcken #48 tscken #51 tsrst #52 tprst #53 tpoe #54 tgpoe 15 #22 #23 #24 todcom todreg todz Slew #28 tslsd #27 tslfd #25 tslf #26 tsls I/O Pad OUTPUT Specifications ispLSI 5512VA Power Consumption Power consumption in the ispLSI 5512VA device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. Each group of four product terms has a single speed/power tradeoff control fuse that acts on the complete group of four. The fast “high-speed” setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower “lowpower” setting will significantly reduce the power dissipation for these product terms. Figure 10 shows the relationship between power and operating speed. Figure 10. Typical Device Power Consumption vs fmax 800 750 ispLSI 5512VA High Speed Mode 700 650 ICC (mA) 600 550 500 450 400 350 ispLSI 5512VA Low Power Mode 300 250 200 0 20 40 60 80 100 120 fmax (MHz) Notes: Configuration of 32 16-bit Counters Typical Current at 3.3V, 25° C ICC can be estimated for the ispLSI 5512VA using the following equation: High Speed Mode: ICC = 70 + (# of PTs * 0.4592) + (# of nets * Max. freq * 0.00391) Low Power Mode: ICC = 70 + (# of PTs * 0.160) + (# of nets * Max. freq * 0.00391) # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/5512va 16 Specifications ispLSI 5512VA Signal Descriptions Signal Name Description TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. TDI Input - This pin is the JTAG Test Data In pin used to load data. TDO Output - This pin is the JTAG Test Data Out pin used to shift data out. TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. GOE0, GOE1 Input - These two pins are the Global Output Enable input pins. GSET/GRST Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be configured as preset, reset or no effect on each register. The global polarity (active high or low input) for this pin is also selectable. I/O Input/Output – These are the general purpose I/O used by the logic array. GND Ground NC1 No connect. VCC Vcc CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. CLK2 / I/O, CLK3 / I/O Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O pin based upon customer's design. Both clocks are muxed before being used as the clock input to all registers in the device. VCCIO Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. 1. NC pins are not to be connected to any active signals, VCC or GND. 17 Specifications ispLSI 5512VA 208-Pin PQFP Signal Locations Signal GOE0, GOE1 Pin 78, 79 TOE / I/O0 32 GSET/GRST 138 TCK 29 TDI 30 TDO 136 TMS 28 CLK0, CLK1 184,185 CLK2 / I/O89 162 CLK3 / I/O98 173 VCCIO 137 GND 3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199 VCC 7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201 NC 49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208 1. NCs are not to be connected to any active signals, VCC or GND. 208-Pin PQFP I/O Locations I/O # 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin 32 33 34 35 36 37 38 40 42 43 44 45 46 47 53 54 55 56 57 59 60 62 63 64 I/O # 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin 65 66 67 68 70 71 72 73 74 75 76 81 82 83 84 85 86 87 89 91 92 93 94 95 I/O # 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 I/O # 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89* 90 91 92 93 94 95 Pin 96 97 98 100 111 112 114 115 116 117 118 119 120 122 124 125 126 127 129 130 131 132 133 134 Pin 140 141 142 143 144 145 146 147 148 149 151 153 154 155 159 160 161 162 163 165 166 167 168 169 I/O # 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Pin 171 172 173 174 175 176 178 180 181 182 183 187 188 189 190 192 193 194 195 196 197 198 200 202 * I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 18 I/O # 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 Pin 203 204 205 206 1 2 4 5 6 8 9 10 11 13 15 16 17 18 20 21 23 24 25 26 Specifications ispLSI 5512VA 388-Ball BGA Signal Locations Signal GOE0, GOE1 Ball AF14, AD13 TOE / I/O0 T1 GSET/GRST L25 TCK T2 TDI R3 TDO N24 TMS R1 CLK0, CLK1 A13, C14 CLK2 / I/O179 A23 CLK3 / I/O197 B17 VCCIO M26 GND A1, A2, A26, B2, B25, B26, C3, C24, D4, D9, D14, D19, D23, H4, J23, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N4, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, P23, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, V4, W23, AC4, AC8, AC13, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26 VCC NC 1 D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, AC11, AC16, AC21 C9, D2, E24, L1, AC25, AF19 1. NCs are not to be connected to any active signals, VCC or GND. 19 Specifications ispLSI 5512VA 388-Ball BGA I/O Locations (Sorted by I/O) I/O # Ball I/O # 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 T1 R4 U2 T3 U1 U4 V2 U3 V1 W2 W1 V3 Y2 W4 Y1 W3 AA2 Y4 AA1 Y3 AB2 AB1 AA3 AC2 AB4 AC1 AB3 AD2 AC3 AD1 AF2 AE3 AF3 AE4 AD4 AF4 AE5 AC5 AD5 AF5 AE6 AC7 AD6 AF6 AE7 AF7 AD7 AE8 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Ball AC9 AF8 AD8 AE9 AF9 AE10 AD9 AF10 AC10 AE11 AD10 AF11 AE12 AF12 AD11 AE13 AC12 AF13 AD12 AE14 AC14 AE15 AD14 AF15 AE16 AD15 AF16 AC15 AE17 AD16 AF17 AC17 AE18 AD17 AF18 AE19 AD18 AE20 AC19 AF20 AD19 AE21 AC20 AF21 AD20 AE22 AF22 AD21 I/O # 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 I/O # Ball 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179* 180 181 182 183 184 185 186 187 188 189 190 191 AE23 AC22 AF23 AD22 AE24 AD23 AF24 AE26 AD25 AD26 AC24 AC26 AB25 AB23 AB24 AB26 AA25 Y23 AA24 AA26 Y25 Y26 Y24 W25 V23 W26 W24 V25 V26 U25 V24 U26 U23 T25 U24 T26 R25 R26 T24 P25 R23 P26 R24 N25 N23 N26 P24 M25 Ball M24 L26 M23 K25 L24 K26 K23 J25 K24 J26 H25 H26 J24 G25 H23 G26 H24 F25 G23 F26 G24 E25 E26 F24 D25 E23 D26 C25 D24 C26 A25 B24 A24 B23 C23 A23 B22 D22 C22 A22 B21 D20 C21 A21 B20 A20 C20 B19 I/O # 192 193 194 195 196 197* 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 Ball I/O # Ball D18 A19 C19 B18 A18 B17 C18 A17 D17 B16 C17 A16 B15 A15 C16 B14 D15 A14 C15 B13 D13 B12 C13 A12 B11 C12 A11 D12 B10 C11 A10 D10 B9 C10 A9 B8 A8 B7 D8 A7 C8 B6 D7 A6 C7 B5 A5 C6 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 B4 D5 A4 C5 B3 C4 A3 B1 C2 C1 D3 D1 E2 E4 E3 E1 F2 G4 F3 F1 G2 G1 G3 H2 J4 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 M2 M1 L3 N2 M4 N1 M3 P2 P4 P1 N3 R2 P3 * I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 20 Specifications ispLSI 5512VA 388-Ball BGA I/O Locations (Sorted by Ball) I/O # 246 242 238 235 231 228 226 222 218 215 209 205 203 199 196 193 189 187 183 179* 176 174 247 244 240 237 233 229 227 224 220 216 213 211 207 204 201 197* 195 191 188 184 180 177 175 249 248 245 Ball I/O # Ball I/O # Ball I/O # A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B01 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C01 C02 C04 243 239 236 232 225 221 217 214 210 206 202 198 194 190 186 182 178 171 173 251 250 241 234 230 223 219 212 208 200 192 185 181 172 168 170 255 252 254 253 169 165 166 259 256 258 167 161 163 C05 C06 C07 C08 C10 C11 C12 C13 C15 C16 C17 C18 C19 C20 C21 C22 C23 C25 C26 D01 D03 D05 D07 D08 D10 D12 D13 D15 D17 D18 D20 D22 D24 D25 D26 E01 E02 E03 E04 E23 E25 E26 F01 F02 F03 F24 F25 F26 261 260 262 257 162 164 157 159 265 263 266 158 160 154 155 268 267 270 264 156 151 153 271 269 274 272 150 152 147 149 273 277 148 145 276 275 281 279 146 144 143 280 278 285 140 139 141 284 G01 G02 G03 G04 G23 G24 G25 G26 H01 H02 H03 H23 H24 H25 H26 J01 J02 J03 J04 J24 J25 J26 K01 K02 K03 K04 K23 K24 K25 K26 L02 L03 L24 L26 M01 M02 M03 M04 M23 M24 M25 N01 N02 N03 N23 N25 N26 P01 282 287 283 142 135 137 286 1 136 138 132 133 0* 3 134 129 131 4 2 7 5 128 130 125 127 8 6 11 120 126 123 124 10 9 15 13 122 119 121 14 12 19 17 113 118 116 117 18 Ball P02 P03 P04 P24 P25 P26 R02 R04 R23 R24 R25 R26 T01 T03 T24 T25 T26 U01 U02 U03 U04 U23 U24 U25 U26 V01 V02 V03 V23 V24 V25 V26 W01 W02 W03 W04 W24 W25 W26 Y01 Y02 Y03 Y04 Y23 Y24 Y25 Y26 AA01 I/O # 16 22 114 112 115 21 20 26 24 109 110 108 111 25 23 28 37 41 48 56 64 68 75 79 86 90 97 106 107 29 27 34 38 42 46 50 54 58 62 66 70 73 77 81 84 88 92 95 Ball I/O # Ball AA02 AA03 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC05 AC07 AC09 AC10 AC12 AC14 AC15 AC17 AC19 AC20 AC22 AC24 AC26 AD01 AD02 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 99 101 104 105 31 33 36 40 44 47 51 53 57 60 63 67 69 72 76 80 83 85 89 93 96 100 103 30 32 35 39 43 45 49 52 55 59 61 65 71 74 78 82 87 91 94 98 102 AD22 AD23 AD25 AD26 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE26 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF15 AF16 AF17 AF18 AF20 AF21 AF22 AF23 AF24 * I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 21 Specifications ispLSI 5512VA Signal Locations (272-Ball BGA) Signal GOE0, GOE1 Ball V11, U11 TOE / I/O 0 M2 GSET/GRST J18 TCK L4 TDI M1 TDO J20 TMS L3 CLK0, CLK1 C10, D10 CLK2 / I/O 119 A18 CLK3 / I/O 131 B13 VCCIO J19 GND A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17, U4, U8, U13, U17 VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 NC1 U1, W1, E2, U2, W2, Y2, B3, C3, D3, U3, C5, W4, T4, Y12, A17, T17, W17, B18, C18, B19, C19, D19, W19, B20, T20, W20, Y20, P19, R3 1. NCs are not to be connected to any active signals, VCC or GND. 22 Specifications ispLSI 5512VA 272-Ball BGA I/O Locations (Sorted by I/O) I/O # Ball I/O # Ball I/O # Ball 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 M2 M3 M4 N1 N2 N3 P1 P2 R1 P3 R2 T1 P4 T2 T3 V1 V2 V3 Y1 W3 V4 U5 Y3 Y4 V5 W5 Y5 V6 U7 W6 Y6 V7 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 W7 Y7 V8 W8 Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 W12 V12 U12 Y13 W13 V13 Y14 W14 Y15 V14 W15 Y16 U14 V15 W16 Y17 V16 Y18 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 U16 V17 W18 Y19 V18 V19 U19 U18 V20 U20 T18 T19 R18 P17 R19 R20 P18 P20 N18 N19 N20 M17 M18 M19 M20 L19 L18 L20 K20 K19 K18 K17 I/O # 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119* 120 121 122 123 124 125 126 127 Ball I/O # Ball I/O # J17 H20 H19 H18 G20 G19 F20 G18 F19 E20 G17 F18 E19 D20 E18 C20 E17 D18 A20 A19 B17 C17 D16 A18 C16 B16 A16 C15 D14 B15 A15 C14 128 129 130 131* 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 A9 B9 C9 D9 A8 B8 C8 A7 B7 A6 C7 B6 A5 D7 C6 B5 A4 B4 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 * I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 23 Ball A3 D5 C4 B2 A2 B1 C2 D2 E4 C1 D1 E3 E1 F3 G4 F2 F1 G3 G2 G1 H3 H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 L2 Specifications ispLSI 5512VA 272-Ball BGA I/O Locations (Sorted by Ball) I/O # 164 160 158 154 151 149 146 142 140 139 136 132 129 126 122 119* 115 114 165 163 159 157 153 150 147 143 141 137 135 131* 128 125 Ball A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A18 A19 A20 B1 B2 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 I/O # 121 116 169 166 162 156 152 148 144 138 134 130 127 123 120 117 111 170 167 161 155 145 133 124 118 113 109 172 171 168 112 110 Ball B16 B17 C1 C2 C4 C6 C7 C8 C9 C11 C12 C13 C14 C15 C16 C17 C20 D1 D2 D5 D7 D9 D12 D14 D16 D18 D20 E1 E3 E4 E17 E18 I/O # 108 105 176 175 173 107 104 102 179 178 177 174 106 103 101 100 182 181 180 99 98 97 186 185 184 183 96 189 187 188 95 94 I/O # 93 92 190 191 90 89 91 0* 1 2 85 86 87 88 3 4 5 82 83 84 6 7 9 12 77 80 81 8 10 76 78 79 Ball E19 E20 F1 F2 F3 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H18 H19 H20 J1 J2 J3 J4 J17 K1 K2 K3 K17 K18 Ball K19 K20 L1 L2 L18 L19 L20 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N18 N19 N20 P1 P2 P3 P4 P17 P18 P20 R1 R2 R18 R19 R20 I/O # 11 13 14 74 75 21 28 37 48 58 64 71 70 73 15 16 17 20 24 27 31 34 38 42 47 51 55 59 62 65 68 69 Ball T1 T2 T3 T18 T19 U5 U7 U9 U12 U14 U16 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V12 V13 V14 V15 V16 V17 V18 V19 * I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 24 I/O # 72 19 25 29 32 35 39 41 45 46 50 53 56 60 66 18 22 23 26 30 33 36 40 43 44 49 52 54 57 61 63 67 Ball V20 W3 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W18 Y1 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Specifications ispLSI 5512VA Pin Configuration 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 NC1 NC1 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 VCC I/O 118 GND I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 GND I/O 110 I/O 109 I/O 108 I/O 107 VCC CLK1 CLK0 I/O 106 I/O 105 I/O 104 I/O 103 GND I/O 102 VCC I/O 101 I/O 100 I/O 99 I/O 98 / CLK32 I/O 97 I/O 96 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 GND I/O 90 I/O 89 / CLK22 I/O 88 I/O 87 I/O 86 NC1 NC1 ispLSI 5512VA 208-pin PQFP (with Heat Spreader) ispLSI 5512VA Top View 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCC I/O 85 I/O 84 I/O 83 VCC I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC GSET/GRST VCCIO TDO GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 GND I/O 65 I/O 64 I/O 63 I/O 62 VCC I/O 61 GND I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 GND I/O 53 I/O 52 VCC NC1 NC1 NC1 NC1 NC1 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 GND I/O 19 I/O 20 VCC I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 GND I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 GND GOE0 GOE1 VCC I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 GND I/O 42 VCC I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 GND I/O 51 1NC 1NC 1NC 1NC I/O 124 I/O 125 GND I/O 126 I/O 127 I/O 128 VCC I/O 129 I/O 130 I/O 131 I/O 132 GND I/O 133 VCC I/O 134 I/O 135 I/O 136 I/O 137 GND I/O 138 I/O 139 VCC I/O 140 I/O 141 I/O 142 I/O 143 GND TMS TCK TDI VCC 2I/O 0 / TOE I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 GND I/O 7 VCC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 GND 1NC 1NC 1NC 1NC 208-PQFP/5512VA 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 25 Specifications ispLSI 5512VA Part Number Description ispLSI 5512VA – XXX X XXXX X Device Family Grade Blank = Commercial I = Industrial Device Number Package B388 = 388-Ball BGA B272 = 272-Ball BGA (Thermally Enhanced) Q208 = 208-Pin PQFP (with Heat Spreader) Speed 110 = 110 MHz fmax 100 = 100 MHz fmax 70 = 70 MHz fmax Power L = Low 0212/5512va Ordering Information COMMERCIAL Family ispLSI fmax tpd Ordering Number Package 110 8.5 ispLSI5512VA-110LB272 272-Ball BGA 110 8.5 ispLSI 5512VA-110LB388 388-Ball BGA 110 8.5 ispLSI 5512VA-110LQ208 208-Pin PQFP 100 10 ispLSI 5512VA-100LB272 272-Ball BGA 100 10 ispLSI 5512VA-100LB388 388-Ball BGA 100 10 ispLSI 5512VA-100LQ208 208-Pin PQFP 70 15 ispLSI 5512VA-70LB272 272-Ball BGA 70 15 ispLSI 5512VA-70LB388 388-Ball BGA 70 15 ispLSI 5512VA-70LQ208 208-Pin PQFP INDUSTRIAL Family fmax tpd Ordering Number Package ispLSI 70 15 ispLSI 5512VA-70LB388I 388-Ball BGA 26