STMicroelectronics M68AF127BM70B6 1mbit 128k x8, 5v asynchronous sram Datasheet

M68AF127B
1Mbit (128K x8), 5V Asynchronous SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
SUPPLY VOLTAGE: 4.5 to 5.5V
128K x 8 bits SRAM with OUTPUT ENABLE
EQUAL CYCLE and ACCESS TIMES: 55ns
LOW STANDBY CURRENT
LOW VCC DATA RETENTION: 2V
TRI-STATE COMMON I/O
LOW ACTIVE and STANDBY POWER
Figure 1. Packages
SO32 (MC)
32
1
PDIP32 (B)
TSOP32 (NK)
8 x 13.4mm
TSOP32 (N)
8 x 20mm
September 2004
1/23
M68AF127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 11
Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 17
Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 18
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . 18
Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline . . . . . . . . 19
2/23
M68AF127B
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline . . . . . . . . . . . 20
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M68AF127B
SUMMARY DESCRIPTION
The M68AF127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal address access and cycle times. It requires a single
4.5 to 5.5V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF127B is available in SO32, PDIP32,
TSOP32 (8x13.4mm) and TSOP32 (8x20mm)
packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1
Chip Enable
E2
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
VCC
17
8
A0-A16
DQ0-DQ7
W
E1
M68AF127B
E2
G
VSS
AI05472B
4/23
M68AF127B
Figure 3. SO Connections
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 5. TSOP Connections
1
32
8
9
M68AF127B
16
25
24
17
VCC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
W
E2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
8
9
16
32
M68AF127B
25
24
17
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
AI05473d
AI07270B
Figure 4. DIP Connections
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
M68AF127B
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
AI07203B
5/23
M68AF127B
Figure 6. Block Diagram
A16
ROW
DECODER
MEMORY
ARRAY
A7
DQ7
I/O CIRCUITS
COLUMN
DECODER
DQ0
E1
Ex
E2
A0
A6
W
G
AI05471
6/23
M68AF127B
OPERATION
The M68AF127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E1 as summarized in the Operating
Modes table (Table 2).
Read Mode
The M68AF127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within t AVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access
will be measured from the limiting parameter
(tELQV or tGLQV) rather than the address. Data out
may be indeterminate at tELQX and tGLQX, but data
lines will always be valid at t AVQV.
Write Mode
The M68AF127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles.
Write begins with the concurrence of E1 being active with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
tAVWL and tAVEH, respectively, and is determined
by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVEH before
the rising edge of E1, whichever occurs first, and
remain valid for tWHDX or tEHDX.
Table 2. Operating Modes
Operation
E1
E2
W
G
DQ0-DQ7
Power
Read
VIL
VIH
VIH
VIH
Hi-Z
Active (ICC)
Read
VIL
VIH
VIH
VIL
Data Output
Active (ICC)
Write
VIL
VIH
VIL
X
Data Input
Active (ICC)
Deselect
VIH
X
X
X
Hi-Z
Standby (ISB)
Deselect
X
VIL
X
X
Hi-Z
Standby (ISB)
Note: X = VIH or VIL.
7/23
M68AF127B
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Symbol
Value
Unit
20
mA
Ambient Operating Temperature
–55 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VCC
Supply Voltage
–0.5 to 6.5
V
–0.5 to VCC +0.5
V
1
W
IO
(1)
TA
VIO
(2)
PD
Parameter
Output Current
Input or Output Voltage
Power Dissipation
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating VCC of 6.0V only.
8/23
M68AF127B
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M68AF127B
VCC Supply Voltage
4.5 to 5.5V
Range 1
0 to 70°C
Range 6
–40 to 85°C
Ambient Operating Temperature
Load Capacitance (CL)
100pF
Output Circuit Protection Resistance (R1)
3.0kΩ
Load Resistance (R2)
3.1kΩ
Input Rise and Fall Times
1ns/V
0 to VCC
Input Pulse Voltages
Input and Output Timing Ref. Voltages
VCC/2
Output Transition Timing Ref. Voltages
VRL = 0.3VCC; VRH = 0.7VCC
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage
R1
VCC
VCC/2
0V
DEVICE
UNDER
TEST
OUT
CL
Output Transition Timing Reference Voltage
VCC
0V
R2
0.7VCC
0.3VCC
AI04831
CL includes JIG capacitance
AI05814
9/23
M68AF127B
Table 5. Capacitance
CIN
COUT
Test
Condition
Parameter (1,2)
Symbol
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Typ
Max
Unit
55
7.5
20
mA
70
6.0
15
mA
2
mA
Input Capacitance on all pins (except DQ)
Output Capacitance
Min
Note: 1. Sampled only, not 100% tested.
2. At TA = 25°C, f = 1MHz, VCC = 3.0V.
Table 6. DC Characteristics
Symbol
ICC1 (1,2)
ICC2 (3)
ILI
Parameter
Supply Current
Operating Supply Current
Input Leakage Current
ILO (4)
Output Leakage Current
Test Condition
VCC = 5.5V, f = 1/tAVAV,
IOUT = 0mA
Min
VCC = 5.5V, f = 1MHz,
IOUT = 0mA
0V ≤VIN ≤VCC
–1
1
µA
0V ≤VOUT ≤VCC
–1
1
µA
15
µA
VCC = 5.5V, E1 ≥ VCC – 0.2V,
E2 ≤0.2V, f = 0
ISB
Standby Supply Current CMOS
VIH
Input High Voltage
2.2
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
VOH
Output High Voltage
IOH = –1mA
VOL
Output Low Voltage
IOL = 2.1mA
Note: 1.
2.
3.
4.
10/23
Average AC current, cycling at tAVAV minimum.
E1 = V IL, E2 = VIH, VIN = VIH or VIL.
E1 ≤0.2V or E2 ≥ V CC –0.2V, VIN ≤0.2V or VIN ≥ VCC –0.2V.
Output disabled.
2.5
2.4
V
0.4
V
M68AF127B
Figure 9. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DATA VALID
DQ0-DQ7
AI05474
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E1
E2
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI05476
Note: Write Enable (W) = High.
11/23
M68AF127B
Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms
E1
E2
ICC
ISB
tPU
tPD
50%
AI05477
12/23
M68AF127B
Table 7. Read and Standby Mode AC Characteristics
M68AF127B
Symbol
Parameter
Unit
55
70
tAVAV
Read Cycle Time
Min
55
70
ns
tAVQV
Address Valid to Output Valid
Max
55
70
ns
tAXQX (1)
Data hold from address change
Min
5
5
ns
tEHQZ (2,3)
Chip Enable High to Output Hi-Z
Max
20
25
ns
tELQV
Chip Enable Low to Output Valid
Max
55
70
ns
Chip Enable Low to Output Transition
Min
5
5
ns
tGHQZ (2,3)
Output Enable High to Output Hi-Z
Max
20
25
ns
tGLQV
Output Enable Low to Output Valid
Max
25
35
ns
Output Enable Low to Output Transition
Min
5
5
ns
tPD
Chip Enable or UB/LB High to Power Down
Max
55
70
ns
tPU
Chip Enable or UB/LB Low to Power Up
Min
0
0
ns
tELQX (1)
tGLQX (2)
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC.
2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than t ELQX for any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
13/23
M68AF127B
Figure 12. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVWH
tELWH
tAVEL
tWHAX
E1
E2
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI05478
Figure 13. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tAVEL
tELEH
tEHAX
E1
E2
tAVWL
tWLEH
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI05479
14/23
M68AF127B
Table 8. Write Mode AC Characteristics
M68AF127B
Symbol
Parameter
Unit
55
70
tAVAV
Write Cycle Time
Min
55
70
ns
tAVEH
Address Valid to Chip Enable High
Min
45
60
ns
tAVEL
Address valid to Chip Enable Low
Min
0
0
ns
tAVWH
Address Valid to Write Enable High
Min
45
60
ns
tAVWL
Address Valid to Write Enable Low
Min
0
0
ns
tDVEH
Input Valid to Chip Enable High
Min
25
30
ns
tDVWH
Input Valid to Write Enable High
Min
25
30
ns
tEHAX
Chip Enable High to Address Transition
Min
0
0
ns
tEHDX
Chip enable High to Input Transition
Min
0
0
ns
tELEH
Chip Enable Low to Chip Enable High
Min
45
60
ns
tELWH
Chip Enable Low to Write Enable High
Min
45
60
ns
tWHAX
Write Enable High to Address Transition
Min
0
0
ns
tWHDX
Write Enable High to Input Transition
Min
0
0
ns
tWHQX (1)
Write Enable High to Output Transition
Min
5
5
ns
tWLEH
Write Enable Low to Chip Enable High
Min
45
60
ns
Write Enable Low to Output Hi-Z
Max
20
20
ns
Write Enable Low to Write Enable High
Min
45
60
ns
tWLQZ (1,2)
tWLWH
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
15/23
M68AF127B
Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE
5.5V
VCC
4.5V
VDR > 2.0V
tCDR
tR
E1 ≥ VDR – 0.2V
E1
AI07204
Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE
5.5V
VCC
4.5V
VDR > 2.0V
tCDR
tR
E2 ≤ 0.2V
E2
AI07205B
Table 9. Low VCC Data Retention Characteristics
Symbol
ICCDR (1)
Parameter
Supply Current (Data Retention)
Test Condition
tCDR (1,2) Chip Deselected to Data Retention Time
tR
(2)
VDR (1)
Operation Recovery Time
Supply Voltage (Data Retention)
Min
VCC = 2.0V, E1 ≥ VCC –0.2V or
E2 ≤0.2V, f = 0
E1 ≥ VCC –0.2V or E2 ≤0.2V, f = 0
Unit
4.5
µA
0
ns
tAVAV
ns
2.0
V
Note: 1. All other Inputs at V IH ≥ VCC –0.2V or VIL ≤0.2V.
2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
16/23
Max
M68AF127B
PACKAGE MECHANICAL
Figure 16. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16
1
E
17
E1
32
A2
B
C
CP
A1
e
A
L1
SO-C
L
Note: Drawing is not to scale.
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters
inches
Symbol
Typ
B
Min
Max
0.36
0.51
A
Typ
Min
Max
0.014
0.020
3.00
0.118
A1
0.10
A2
2.57
2.82
0.101
0.111
C
0.15
0.30
0.006
0.012
CP
0.004
0.10
0.004
D
20.14
20.75
0.793
0.817
E
11.18
11.43
0.440
0.450
E1
13.87
14.38
0.546
0.566
–
–
–
–
L
0.58
0.99
0.023
0.039
L1
1.19
1.60
0.047
0.063
N
32
e
1.27
0.050
32
17/23
M68AF127B
Figure 17. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2
A1
b1
b
A
α
L
e
eA
c
D2
D
S
N
E1
E
1
PDIP-C
Note: Drawing is not to scale.
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
18/23
Typ
Min
4.83
A1
A2
Max
Max
0.190
0.38
0.015
3.81
0.150
b
0.41
0.53
0.016
0.021
b1
1.14
1.65
0.045
0.065
c
0.23
0.38
0.009
0.015
D
41.78
42.29
1.645
1.665
eA
15.24
–
–
0.600
–
–
e
2.54
–
–
0.100
–
–
E
15.24
15.88
0.600
0.625
E1
13.46
13.97
0.530
0.550
L
3.05
3.56
0.120
0.140
S
1.65
2.21
0.065
0.087
α
0°
15°
0°
15°
N
32
32
M68AF127B
Figure 18. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline
A2
N
1
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
Max
0.0472
A1
0.05
0.15
0.0020
0.0059
A2
0.91
1.05
0.0358
0.0413
0.0039
0.0083
B
0.22
C
0.0087
0.10
CP
0.21
0.10
0.0039
D
13.40
–
–
0.5276
–
–
D1
11.80
–
–
0.4646
–
–
E
8.00
–
–
0.3150
–
–
e
0.50
–
–
0.0197
–
–
L
0.40
0.60
0.0157
0.0236
α
0°
5°
0°
5°
N
32
32
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M68AF127B
Figure 19. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline
A2
N
1
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
B
0.170
0.250
0.0067
0.0098
C
0.100
0.210
0.0039
0.0083
CP
0.100
0.0039
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
–
–
–
–
E
7.900
8.100
0.3110
0.3189
L
0.500
0.700
0.0197
0.0276
α
0°
5°
0°
5°
N
32
e
20/23
inches
0.500
0.0197
32
M68AF127B
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M68AF127
B
L 55 MC
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
F = 4.5 to 5.5V
Array Organization
127 = 1Mbit (128K x8)
Option 1
B = 2 Chip Enable
Option 2
L = L-Die
M = M-Die
Speed Class
55 = 55ns
70 = 70ns
Package
MC = SO32
B = PDIP32
NK = TSOP32 8x13.4mm
N = TSOP32 8x20mm
Operative Temperature
1 = 0 to 70°C
6 = –40 to 85°C
Shipping
T = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
21/23
M68AF127B
REVISION HISTORY
Table 15. Document Revision History
Date
Version
August 2001
1.0
First Issue.
18-Oct-2001
2.0
SO32 Package Mechanical and Data added (Figure 1, 3 and 16, Table 10).
29-Nov-2001
3.0
Note removed from Ordering Information Scheme.
06-Mar-2002
4.0
Document status changed to Data Sheet.
17-May-2002
5.0
Document globally revised.
31-May-2002
6.0
PDIP32 Package added (Figure 1, 4 and 17, Table 11).
Chip Enable Low VCC Data Retention clarified (Figure 14 and 15, Table 9).
09-Sep-2002
6.1
TSOP32 8x13.4mm and TSOP32 8x20mm packages added (Figure 1, 5, 18 and 19,
Table 12, 13 and 14).
Commercial code clarified.
02-Oct-2002
6.2
Title and header layout modified.
09-Oct-2002
6.3
Datasheet number simplified.
16-Apr-2003
6.4
Label corrected on “E2 Controlled, Low VCC Data Retention AC Waveforms” figure.
08-Aug-2003
6.5
TSOP Package connections modified (Figure 5).
Test conditions for ICCDR modified in Table 9, Low VCC Data Retention
Characteristics.
21-Aug-2003
6.6
TSOP Package connections modified (Figure 5).
24-Sep-2004
22/23
7
Revision Details
Document structure modified:
– Chapter OPERATION moved before chapter MAXIMUM RATING.
– AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS
section.
tPU ad tPD updated in Table 7.
M68AF127B
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