DS10BR150 www.ti.com SNLS252C – APRIL 2007 – REVISED MAY 2011 DS10BR150 1.0 Gbps LVDS Buffer / Repeater Check for Samples: DS10BR150 FEATURES DESCRIPTION • The DS10BR150 is a single channel 1.0 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. 1 2 • • • DC - 1.0 Gbps Low Jitter, High Noise Immunity, Low Power Operation On-chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count and Minimizes Board Space 7 kV ESD on LVDS I/O Pins Protects Adjoining Components Small 3 mm x 3 mm 8-WSON Space Saving Package APPLICATIONS • • • Clock and Data Buffering OC-12 / STM-4 FireWire 800 Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space. Typical Application CML ASIC / FPGA LVDS LVPECL BR150 LVDS ASIC / FPGA 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2011, Texas Instruments Incorporated DS10BR150 SNLS252C – APRIL 2007 – REVISED MAY 2011 www.ti.com Block Diagram IN+ OUT+ IN- OUT- Pin Diagram NC 1 IN+ 2 IN- 3 NC 4 8 VCC DAP 7 OUT+ GND 6 OUT- 5 NC DS10BR150 See Package Number NGQ0008A PIN DESCRIPTIONS Pin Name Pin Name Pin Type Pin Description NC 1 NA "NO CONNECT" pin. IN+ 2 Input Non-inverting LVDS input pin. IN- 3 Input Inverting LVDS input pin. NC 4 NA "NO CONNECT" pin. NC 5 NA "NO CONNECT" pin. OUT- 6 Output Inverting LVDS output pin. OUT+ 7 Output Non-inverting LVDS Output pin. VCC 8 Power Power supply pin. GND DAP Power Ground pad (DAP - die attach pad) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 DS10BR150 www.ti.com SNLS252C – APRIL 2007 – REVISED MAY 2011 Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) −0.3V to +4V LVDS Input Voltage (IN+, IN−) −0.3V to +4V Differential Input Voltage |VID| 1V −0.3V to (VCC +0.3V) LVDS Output Voltage (OUT+, OUT−) LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1V LVDS Output Short Circuit Current Duration 5 ms Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C Maximum Package Power Dissipation at 25°C NGQ Package 2.08W Derate NGQ Package 16.7 mW/°C above +25°C Package Thermal Resistance θJA +60.0°C/W θJC +12.3°C/W ESD Susceptibility HBM (3) ≥7 kV MM (4) ≥250V CDM (5) (1) (2) (3) (4) (5) ≥1250V “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Supply Voltage (VCC) Receiver Differential Input Voltage (VID) Min Typ Max Units 3.0 3.3 3.6 V 0 −40 Operating Free Air Temperature (TA) +25 1 V +85 °C DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions (1) (2) (3) Min Typ Max Units 250 350 450 mV 35 mV 1.375 V 35 mV LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD Differential Output Voltage ΔVOD Change in Magnitude of VOD for Complimentary Output States VOS Offset Voltage ΔVOS (1) (2) (3) RL = 100Ω -35 1.05 Change in Magnitude of VOS for Complimentary Output States RL = 100Ω -35 1.2 The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 3 DS10BR150 SNLS252C – APRIL 2007 – REVISED MAY 2011 www.ti.com DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3) Symbol IOS Parameter Output Short Circuit Current Conditions (4) Min Typ Max Units OUT to GND -30 -50 mA OUT to VCC 7.5 50 mA COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF ROUT Output Termination Resistor Between OUT+ and OUT- Pins 100 Ω LVDS INPUT DC SPECIFICATIONS (IN+, IN-) VID Input Differential Voltage VTH Differential Input High Threshold 0 VTL Differential Input Low Threshold VCMR Common Mode Voltage Range VID = 100 mV IIN Input Current VIN = 3.6V or 0V VCC = 3.6V or 0V ±1 CIN Input Capacitance 1.7 pF RIN Input Termination Resistor Between IN+ and IN- Pins 100 Ω VCM = +0.05V or VCC-0.05V 0 −100 1 V +100 mV 0 0.05 mV VCC 0.05 V ±10 μA SUPPLY CURRENT ICCD (4) Total Supply Current 16 21 mA Typ Max Units 380 600 ps 410 600 ps 30 150 ps 45 160 ps 165 400 ps 155 400 ps Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. AC Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions (2) (3) Min LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) tPHLD2 Differential Propagation Delay High to Low tPLHD2 Differential Propagation Delay Low to High tSKD1 Pulse Skew |tPLHD − tPHLD| tSKD2 Part to Part Skew tLHT Rise Time tHLT Fall Time RL = 100Ω (4) (5) RL = 100Ω JITTER PERFORMANCE Figure 5 tDJ tRJ tTJ (1) (2) (3) (4) (5) (6) (7) (8) 4 Deterministic Jitter (Peak-to-Peak Value ) (See (6) ) Random Jitter (RMS Value) (7) Total Jitter (Peak to Peak Value) (8) VID = 350 mV VCM = 1.2V K28.5 (NRZ) 622 Mbps 12 39 ps 1.06 Gbps 15 42 ps VID = 350 mV VCM = 1.2V Clock (NRZ) 311 MHz 0.6 1.3 ps 503 MHz 0.6 1.1 ps VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) 622 Mbps 0.02 0.04 UIP-P 1.06 Gbps 0.02 0.05 UIP-P Specification is guaranteed by characterization and is not tested in production. The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted algebraically. Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically. Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted. Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 DS10BR150 www.ti.com SNLS252C – APRIL 2007 – REVISED MAY 2011 DC Test Circuits DS10BR150 Power Supply VOH OUT+ IN+ R D RL Power Supply IN- OUTVOL Figure 1. Differential Driver DC Test Circuit AC Test Circuits and Timing Diagrams DS10BR150 OUT+ IN+ R Signal Generator D IN- RL OUT- Figure 2. Differential Driver AC Test Circuit Figure 3. Propagation Delay Timing Diagram Figure 4. LVDS Output Transition Times Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 5 DS10BR150 SNLS252C – APRIL 2007 – REVISED MAY 2011 www.ti.com CHARACTERIZATION BOARD 50: Microstrip 50: Microstrip DS10BR150 L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 5. Jitter Measurements Test Circuit DEVICE OPERATION INPUT INTERFACING The DS10BR150 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the DS10BR150 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10BR150 inputs are internally terminated with a 100Ω resistor. 100: Differential T-Line IN+ OUT+ LVDS DS10BR150 OUT- IN- Figure 6. Typical LVDS Driver DC-Coupled Interface to DS10BR150 Input CML3.3V or CML2.5V VCC 50: 100: Differential T-Line 50: IN+ OUT+ DS10BR150 OUT- IN- Figure 7. Typical CML Driver DC-Coupled Interface to DS10BR150 Input 6 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 DS10BR150 www.ti.com SNLS252C – APRIL 2007 – REVISED MAY 2011 LVPECL Driver 100: Differential T-Line OUT+ LVDS Receiver IN+ 100: OUT- IN- 150-250: 150-250: Figure 8. Typical LVPECL Driver DC-Coupled Interface to DS10BR150 Input OUTPUT INTERFACING The DS10BR150 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. 100: Differential T-Line OUT+ DS10BR150 IN+ CML or LVPECL or LVDS 100: IN- OUT- Figure 9. Typical DS10BR150 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 7 DS10BR150 SNLS252C – APRIL 2007 – REVISED MAY 2011 www.ti.com Typical Performance Figure 10. A 622 Mbps NRZ PRBS-7 Output Eye Diagram V:100 mV / DIV, H:200 ps / DIV Figure 11. A 1062.5 Mbps NRZ PRBS-7 Output Eye Diagram V:100 mV / DIV, H:150 ps / DIV 90 90 75 60 VICM = 1.0V 45 30 VICM = 2.4V 15 0 0.25 8 VCC = 3.3V TA = 25°C NRZ PRBS-7 622 Mbps TOTAL RESIDUAL JITTER (ps) TOTAL RESIDUAL JITTER (ps) VCC = 3.3V 0.40 0.55 0.70 0.85 1.00 75 TA = 25°C NRZ PRBS-7 1062.5 Mbps 60 45 VICM = 1.0V 30 VICM = 2.4V 15 0 0.25 0.40 0.55 0.70 0.85 1.00 DIFFERENTIAL INPUT VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) Figure 12. Total Jitter as a Function of Input Amplitude Figure 13. Total Jitter as a Function of Input Amplitude Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Links: DS10BR150 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS10BR150TSD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 1R150 DS10BR150TSDX/NOPB ACTIVE WSON NGQ 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 1R150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS10BR150TSD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 DS10BR150TSDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS10BR150TSD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS10BR150TSDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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