HI-8591
ARINC 429
Line Receiver
March 2013
DESCRIPTION
PIN CONFIGURATIONS
VCC - 1
TESTA - 2
7 - ROUTB
RINB - 3
6 - ROUTA
RINA - 4
5 - GND
HI-8591PSI, HI-8591PST & HI-8591PSM
HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM-40
NC
VCC
TESTB
NC
8 - PIN PLASTIC NARROW BODY SOIC
The typical 10 volt differential ARINC 429 signal is translated and input to a window comparator and latch. The
comparator levels are set just below the standard 6.5 volt
minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold.
See Holt Application Note AN-300 for more information on
lightning protection.
1
2
3
4
12
11
10
9
ROUTB
NC
ROUTA
NC
5
6
7
8
TESTA
RINB
RINA
NC
NC
GND
NC
NC
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. Also if TESTA and TESTB are both taken
high, the digital outputs are forced to zero.
8 - TESTB
16
15
14
13
The HI-8591 is an ARINC 429 bus interface receiver
designed to operate from a single 3.3 V or 5 V supply. The
part is designed with high-impedance inputs to minimize
bus loading, and has an exceptional input common-mode
performance in excess of +/- 30V, making it immune to
ground offsets around the aircraft. The RINA and RINB
inputs of the standard HI-8591 may be connected directly
to the ARINC 429 bus. To enable external lightning protection circuitry to be added, the HI-8591-40 variant is available. The HI-8591-40 requires only the addition of external
40 KW, ¼ watt resistors in series with RINA and RINB to
allow the part to meet the lightning protection requirements
of DO-160D level 3.
HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40
16- pin 4mm x 4mm Chip-scale package
SUPPLY VOLTAGES
vcc = 3.3V ± 10%, 5.0V ± 10%
FEATURES
!
!
!
!
!
!
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FUNCTION TABLE
ARINC 429 line receiver interface in a
small outline package
3.3V single rail supply voltage
RINA
RINB
TESTA
TESTB
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
-3.25V to -6.5V
3.25V to 6.5V
0
0
0
1
3.25V to 6.5V
-3.25V to -6.5V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
0
0
+/-30 V common-mode performance
>140 KOhm input impedance
Lightning protection simplified with the
ability to add 40 KOhm external series
resistors
Receiver input hysteresis at least 2 volt
Test inputs bypass analog inputs and
force digital outputs to a one, zero or
null state
(DS8591, Rev. H)
ROUTA ROUTB
PIN DESCRIPTION TABLE
SYMBOL
FUNCTION
DESCRIPTION
VCC
SUPPLY
3.3V or 5V SUPPLY
TESTA
LOGIC INPUT
CMOS
RINB
ARINC INPUT
RECEIVER B INPUT
RINA
ARINC INPUT
RECEIVER A INPUT
GND
POWER
GROUND
ROUTA
LOGIC OUTPUT
RECEIVER CMOS OUTPUT A
ROUTB
LOGIC OUTPUT
RECEIVER CMOS OUTPUT B
TESTB
LOGIC INPUT
CMOS
HOLT INTEGRATED CIRCUITS
www.holtic.com
03/13
HI-8591
FUNCTIONAL DESCRIPTION
RECEIVER
spond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 140KW of resistance between the ARINC bus and comparator. This resistance is completely on-chip for the HI-8591. In contrast,
the HI-8591-40 has 100 KW on-chip and requires an external 40KW, ¼ watt resistor on each of the ARINC 429 input
pins. The HI-8591-40 device is typically chosen for applications where lightning protection is a requirement.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, the HI8591 outputs are pulled low. This allows the digital outputs of a transmitter to be connected to the test inputs
through control logic for system self-test purposes.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider
between VCC and Ground. The nominal settings corre-
TEST
ONE
S
Q
ROUTA
LATCH
TESTA
R
TESTB
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
Q
ROUTB
LATCH
TESTA
R
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
3.3V
1
HARDWIRE
OR
DRIVE FROM LOGIC
{
2
8
VCC
TESTA
TESTB
ARINC
Channel
Figure 2 shows a possible application of the
HI-8591 interfacing an ARINC 429 bus input
to a 3.3V ASIC or FPGA. In this example a
HI-8586 ARINC 429 line driver is used to
take 3.3V logic outputs and generate the necessary 10V differential signal for driving an
ARINC 429 bus.
ROUTB
6
7
RXD1
RXD0
HI-8591
4
APPLICATION INFORMATION
ROUTA
RINA
3
FPGA
RINB GND
5
15V
1
6
ARINC
Channel
7
8
SLP1.5
V+
TXAOUT
TX1IN
HI-8586
TX0IN
TXBOUT
GND
4
V-
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
3
2
TXD1
TXD0
HI-8591
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Voltages referenced to Ground
Supply voltages
VCC......................................-0.3V to +7V
Supply Voltages
VCC..............................3.3V to 5V ± 10%
ARINC input - pins 3 & 4
Voltage at either pin.........+120V to -120V
Operating Temperature Range
Industrial ...................... -40°C to +85°C
Hi-Temp ...................... -55°C to +125°C
DC current per input pin.................... ±10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
Solder Temperature (Reflow)
NOTE: Stresses above absolute maximum
ratings or outside recommended operating conditions may cause permanent damage to the
device. These are stress ratings only. Operation at the limits is not recommended.
260°C
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 3.3V ± 10% or 5.0V ± 10% UNLESS OTHERWISE STATED
PARAMETERS
ARINC input voltage
one or zero
null
common mode
logic input voltage
high
low
ARINC input resistance
RINA to RINB
RINA or RINB to GND
RINA or RINB to VCC
logic input current
source
sink
logic output drive voltage
one
zero
Current drain
operating
SYMBOL
VDIN
VNIN
VCOM
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Differential volt., pins 3 & 4
6.5
-30.0
10
-
13
2.5
+30.0
volts
volts
volts
75% VCC
-
-
25% VCC
volts
volts
-
300
150
150
-
KW
KW
KW
-
-
20.0
20.0
μA
μA
"
"
"
with respect to ground
VIH
VIL
Includes external 40KΩ for HI-8591-40
R DIFF
R GND
R VCC
IIH
IIL
Supplies floating
"
"
"
"
VIN = 2.0V
VIN = 0.8V
VOH1
VCC = 5V ± 10% IOH = 5mA
2.4
-
-
V
VOH2
VCC= 3.3V ± 10% IOH = 1.5mA
2.4
-
-
V
VOL1
VOL2
VCC = 5V ± 10% IOH = 5mA
-
-
0.5
V
VCC = 3.3V ± 10% IOH = 1.5mA
-
-
0.4
V
ICC1
pins 2, 8 = 0V; pins 3, 4 open
-
1.5
5.0
mA
HOLT INTEGRATED CIRCUITS
3
HI-8591
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 3.3V ± 10% or 5.0V ± 10% UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL
Receiver propagation delay
Output high to low
t phlr
Output low to high
t plhr
TEST pin propagation delay
Output high to low
t pth
Output low to high
t ptl
Receiver output transition times
Output high to low
Output low to high
t fr
t rr
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
CAD
CAS
C IN
TEST CONDITIONS
MIN
TYP
MAX
UNITS
defined in Figure 3, C L= 50pF
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
-
600
600
600
600
1000
900
1000
900
ns
ns
ns
ns
defined in Figure 4, C L= 50pF
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
-
-
100
60
100
60
ns
ns
ns
ns
-
15
15
50
50
ns
ns
-
5
-
10
10
10
pF
pF
pF
VCC = 3.3V or 5.0V ± 10%
Notes: 1. Guaranteed but not tested
10V
0V
-10V
VDIFF
pin 4 - pin 3
t plhr
t rr
t phlr
VCC
0V
90%
pin 6
10%
t plhr
t phlr
t fr
VCC
0V
pin 7
FIGURE 3 - RECEIVER TIMING
VCC
0V
TESTA or B
pin 2 or pin 8
t pth
t ptl
pin 6 or pin 7
FIGURE 4 - TEST PIN TIMING
HOLT INTEGRATED CIRCUITS
4
VCC
0V
HI-8591
HEAT SINK - CHIP-SCALE PACKAGE ONLY
The HI-8591PCI and HI-8591PCT use a 16-pin plastic
chip-scale (QFN) package. This package has a metal heat
sink pad on its bottom surface. This heat sink should be
soldered down to the printed circuit board for optimum
thermal dissipation. The heat sink is electrically isolated
from the chip and can be soldered to any ground or power
plane. However, since the chip’s substrate is at V+,
connecting the heat sink to this power plane is
recommended to avoid coupling noise into the circuit.
ORDERING INFORMATION
HI - 8591 xx x x - xx
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
140 Kohm
0
-40
100 Kohm
40 Kohm
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
M
-55°C TO +125°C
M
YES
PART
NUMBER
PACKAGE
DESCRIPTION
PC
16 PIN PLASTIC 4 x 4 mm CHIP SCALE (16PCS) not available with “M” flow
PD
8 PIN PLASTIC DIP (8P) not available with “M” flow
PS
8 PIN PLASTIC NARROW BODY SOIC (8HN)
CR
8 PIN CERDIP (8D) not available Pb-free
HOLT INTEGRATED CIRCUITS
5
HI-8591
REVISION HISTORY
P/N
DS8591
Rev
Date
F
06/21/11
G
H
08/03/12
03/13/13
Description of Change
Updated pad & heat-sink dimensions on 16-pin plastic chip-scale (QFN) package to reflect
current package vendor's dimensions.
Updated VIL/VIH specification, Solder Temperature, and package dimensions (8PS, 16PC).
Clarify ARINC input resistance and correct error in RDIFF. Clarify solder temperature in
Absolute Maximum Ratings. Clarify operating temperature range in Recommended
Operating Conditions.
HOLT INTEGRATED CIRCUITS
6
HI-8591 PACKAGE DIMENSIONS
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
inches (millimeters)
Package Type: 8HN
.193
BSC
(4.90)
.007 ± .003
(.175 ± .075)
.236
BSC
(6.00)
PIN 1
.154
BSC
(3.90)
See Detail A
.016 ± .004
(.410 ± .100)
.056 ± .006
(1.413 ± .163)
0° to 8°
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.050 BSC
(1.27)
.007 ± .003
(.175 ± .075)
.033 ± .017
(.835 ± .435)
8-PIN CERDIP
Detail A
inches (millimeters)
Package Type: 8D
.380 ±.004
(9.652 ±.102)
.005 min
(.127 min)
.248 ±.003
(6.299 ±.076)
.039 ±.006
(.991 ±.154)
.100
BSC
(2.54)
.015 min
(.381min)
.200 max
(5.080 max)
.314 ±.003
(7.976 ±.076)
Base Plane
.010 ±.006
(.254 ±.152)
Seating Plane
.163 ±.037
(4.140 ±.940)
.056 ±.006
(1.422 ±.152)
.018 ±.006
(.457 ±.152)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
7
.350 ±.030
(8.890 ±.762)
HI-8591 PACKAGE DIMENSIONS
8-PIN PLASTIC DIP
inches (millimeters)
Package Type: 8P
.385 ±.015
(9.799 ±.381)
.250 ± .010
(6.350 ±.254)
.100
BSC
(2.54)
.300 ±.010
(7.620 ±.254)
.025 ±.010
(.635 ± .254)
.135 ±.015
(3.429 ±.381)
.1375 ±.0125
(3.493 ±.318)
.0115 ±.0035
(.292 ±.089)
.055 ±.010
(1.397 ±.254)
.019 ±.002
(.483 ±.102)
.335 ±.035
(8.509 ±.889)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
16-PIN PLASTIC CHIP-SCALE PACKAGE
inches (millimeters)
Package Type: 16PCS
.157
BSC
(4.000)
.157
BSC
(4.000)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.102 ± .002
(2.600 ± .050)
.102 ± .002
(2.600 ± .050)
Top View
Bottom
View
.016 ± .002
(.400 ± .050)
.039
(1.000)max.
.008
(.200) typ.
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
8
.026
BSC
(.650)
.012 ± .002
(.300 ± .050)