DSC557-05 Crystal-less™ Four Output PCIe Clock Generator General Description The DSC557-05 is a Crystal-less™, four output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The clock generator uses proven silicon MEMS technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures. By eliminating the external quartz crystal, MEMS clock generators significantly enhance reliability and accelerate product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. DSC557-05 has an Output Enable / Disable feature allowing it to disable all outputs when OE1 and OE2 are low. Each output enable pin controls two banks of synchronous PCIe clocks. See the OE function diagram for more detail. The device is available in a 20 pin QFN. Additional output formats are in any combination of LVPECL, LVDS, and HCSL. Features Meets PCIe Gen1, Gen2 & Gen3 specs Available Output Formats: o o HCSL, LVPECL, or LVDS Mixed Outputs: LVPECL/HCSL/LVDS Wide Temperature Range o Ext. Industrial: -40° to 105° C o Industrial: -40° to 85° C o Ext. commercial: -20° to 70° C Supply Range of 2.25 to 3.6 V Low Power Consumption o 30% lower than competing devices Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 Available Footprints: o 20 QFN Lead Free & RoHS Compliant Short Lead Time: 2 Weeks Block Diagram Applications Communications/Networking o o o o o * Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are 100 MHz as per PCIe standards. For other frequencies, please contact the factory. Ethernet 1G, 10GBASE-T/KR/LR/SR, and FcoE Routers and Switches Gateways, VoIP, Wireless AP’s Passive Optical Networks Storage o SAN, NAS, SSD, JBOD Embedded Applications o Industrial, Medical, and Avionics o Security Systems and Office Automation o Digital Signage, POS and others Consumer Electronics o Smart TV, Bluray, STB _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 1 DSC557-05 Crystal-less Four Output PCIe Clock Generator Specifications (Unless specified otherwise: T=25° C, VDD =3.3V) Parameter Supply Voltage 1 Condition VDD Supply Current IDD Supply Current2 (Four HCSL Outputs) IDD Frequency Stability Δf Startup Time3 Input Logic Levels Input logic high Input logic low tSU VIH VIL Output Disable Time4 Output Enable Time Min. Typ. 2.25 EN pin low – outputs are disabled EN pin high – outputs are enabled RL=50 Ω, FO1=FO2=FO3= FO4=100 MHz Includes frequency variations due to initial tolerance, temp. and power supply voltage T=25°C 42 Max. Unit 3.6 V 46 mA 120 mA ±100 ±50 ppm 5 ms 0.25xVDD V tDA 5 ns tEN 20 ns 2 Pull-Up Resistor 0.75xVDD - Pull-up on OE pin 40 kΩ HCSL Outputs6 Parameter Output Logic Levels Output logic high Output logic low VOH VOL Pk to Pk Output Swing tR tF Frequency 5 Period Jitter Jitter, Phase (Common Clock Architecture) RL=50Ω 0.725 - Typ. Max. Unit 0.1 V 750 mV 20% to 80% RL=50Ω, CL= 2pF 200 f0 Single Frequency 2.3 SYM Differential 48 JPER FO1=FO2= FO3 = FO4 =100 MHz 2.5 TJ PCIe Gen 1.1 22.7 86.08 psp-p JRMS-CCHF PCIe Gen 2.1, 1.5MHz to Nyquist 2.20 3.18 psRMS 0.08 3.0 8 psRMS 8 psRMS JRMS-CCLF JRMS-CC Integrated Phase Noise (Data Clock Architecture) Min. Single-Ended Output Transition time4 Rise Time Fall Time Output Duty Cycle Condition JRMS-DCHF JRMS-DCLF JRMS-DC PCIe Gen 2.1, 10 kHz to 1.5 MHz 1007 400 ps 460 MHz 52 % psRMS PCIe Gen 3.0 0.37 1.0 PCIe Gen 2.1, 1.5MHz to Nyquist 2.15 4.08 psRMS 0.06 0.32 8 psRMS psRMS PCIe Gen 2.1, 10 kHz to 1.5 MHz PCIe Gen 3.0 7.5 1.08 Notes: 1. Each VDD pin should be filtered with 0.01uf capacitor. 2. Output is enabled if OE pin is floated or not connected. 3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled. 4. Output Waveform and Connection Diagram define the parameters. 5. Period Jitter includes crosstalk from adjacent output. 6. Contact [email protected] for alternate output options (LVPECL, LVDS, LVCMOS). 7. Contact [email protected] for alternative frequency options 8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 2 DSC557-05 Crystal-less Four Output PCIe Clock Generator Absolute Maximum Ratings Item Min Max Unit Supply Voltage -0.3 +4.0 V Input Voltage -0.3 VDD+0.3 V Junction Temp - +150 °C Storage Temp -55 +150 °C Soldering Temp - +260 °C ESD HBM MM CDM - Condition 40sec max. V 4000 400 1500 Solder Reflow Profile Se 3C / 217°C 200°C 60-150 Sec S 6C/ ax cM 3C /S e 25°C 60-180 Sec Pre heat 8 min max Reflow x. 150°C Ma . ec Temperature (°C) cM ax . 260°C 20-40 Sec Cool Time 20 QFN MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max. Preheat Time 150°C to 200°C 60-180 Sec Time maintained above 217°C 60-150 Sec Peak Temperature 255-260°C Time within 5°C of actual Peak 20-40 Sec Ramp-Down Rate 6°C/Sec Max. Time 25°C to Peak Temperature 8 min Max. _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 3 DSC557-05 Crystal-less Four Output PCIe Clock Generator Pin Description (20 QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name OE1 NC VSS VSS CLK0CLK0+ CLK1CLK1+ VDD NC OE2 NC VSS VSS CLK2CLK2+ CLK3CLK3+ VDD NC Pin Type I NA Power Power O O O O Power NA I NA Power Power O O O O Power NA Pin Diagram (20 QFN) Description Output Enable; active high Leave unconnected or grounded Ground Ground Complement output of differential True output of differential pair Complement output of differential True output of differential pair Power Supply Leave unconnected or grounded Output Enable; active high Leave unconnected or grounded Ground Ground Complement output of differential True output of differential pair Complement output of differential True output of differential pair Power Supply Leave unconnected or grounded pair pair pair pair Connection Diagram NC VDD CLK3+ CLK3- CLK2+ CLK2- (20 QFN Four HCSL Outputs) 20 19 18 17 16 15 OE1 1 14 VSS VSS 4 11 OE2 CLK0- 5 6 7 8 9 10 NC NC VDD VSS 12 CLK1+ 13 3 CLK1- 2 CLK0+ NC VSS 20 QFN 5.0 x 3.2mm _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 4 DSC557-05 Crystal-less Four Output PCIe Clock Generator OE Function and Output Waveform: HCSL tR tF CLK+ 80% 50% 675mV 20% CLK- 1/f0 tDA tEN VIH OE VIL CLK1/CLK2 Synchronous OE1 0 0 1 1 OE2 0 1 0 1 CLK0 Hi-Z Hi-Z EN EN CLK1 Hi-Z EN Hi-Z EN CLK2 Hi-Z EN Hi-Z EN CLK3 Hi-Z Hi-Z EN EN CLK0/CLK3 Synchronous Ordering Information DSC557-05 4 4 4 4 K I 0 T 4 T 4 CLK 3 Output Format 1: LVCMOS 4 2: LVPECL 4 3: LVDS 4 4: HCSL 4 CLK 2 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL CLK 1 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL Packing T: Tape & Reel Stability 0: ±100ppm 1: ±50ppm Temp Range E: -20 to 70 I: -40 to 85 L: -40 to 105 Package K: 20 QFN CLK 0 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 5 DSC557-05 Crystal-less Four Output PCIe Clock Generator Package Dimensions 20 QFN, 5.0 x 3.2 mm Top View units: mm[inches] Bottom View units: mm[inches]± _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 6 DSC557-05 Crystal-less Four Output PCIe Clock Generator Side View units: mm[inches] Recommended Solder Pad Layout units: mm[inches] *Connect the center pad to VSS for best thermal performance Disclaimer: Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. MICREL, Inc. Phone: +1 (408) 944-0800 ● ● 2180 Fortune Drive, Fax: +1 (408) 474-1000 San Jose, California 95131 ● Email: [email protected] ● ● USA www.micrel.com _____________________________________________________________________________________________________________________________ _________________ DSC557-05 Page 7