Ramtron FM24C64C-G 64kb serial 5v f-ram memory Datasheet

Preliminary
FM24C64C
64Kb Serial 5V F-RAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
 Organized as 8,192 x 8 bits
 High Endurance 1 Trillion (1012) Read/Writes
 36 Year Data Retention at +75C
 NoDelay™ Writes
 Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
 Up to 1 MHz maximum bus frequency
 Direct hardware replacement for EEPROM
 Supports legacy timing for 100 kHz & 400 kHz
Description
The FM24C64C is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 36 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24C64C performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24C64C is capable of
supporting 1012 read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24C64C ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writes with less overhead for the system.
The FM24C64C provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The FM24C64C is
available in an industry standard 8-pin SOIC package
and uses a familiar two-wire protocol. The
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.1
June 2011
Low Power Operation
 5V operation
 100 A Active Current (100 kHz)
 4 A (typ.) Standby Current
Industry Standard Configuration
 Industrial Temperature -40 C to +85 C
 8-pin “Green”/RoHS SOIC (-G)
Pin Configuration
A0
A1
A2
1
8
2
7
3
6
VSS
4
5
Pin Names
A0-A2
SDA
SCL
WP
VSS
VDD
VDD
WP
SCL
SDA
Function
Device Select Address
Serial Data/address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24C64C-G
FM24C64C-GTR
“Green”/RoHS 8-pin SOIC
“Green”/RoHS 8-pin SOIC,
Tape & Reel
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 12
FM24C64C
Counter
Address
Latch
1,024 x 64
FRAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
Control Logic
A0-A2
Figure 1. FM24C64C Block Diagram
Pin Description
Pin Name
A0-A2
I/O
Input
SDA
I/O
SCL
Input
WP
Input
VDD
VSS
Rev. 1.1
June 2011
Supply
Supply
Pin Description
Address 2-0: These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
Serial Data Address: This is a bi-directional pin used to shift serial data and addresses
for the two-wire interface. It employs an open-drain output and is intended to be wireOR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt
trigger for noise immunity and the output driver includes slope control for falling
edges. A pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Write Protect: When WP is high, addresses in the upper quadrant of the logical
memory map will be write-protected. Write access is permitted to the lower threequarters of the address space. When WP is low, all addresses may be written. This pin
is pulled down internally.
Supply Voltage: 5V
Ground
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FM24C64C
Overview
Two-wire Interface
The FM24C64C is a serial FRAM memory. The
memory array is logically organized as a 8,192 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24C64C and a serial
EEPROM with the same pinout relates to its superior
write performance.
The FM24C64C employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24C64C in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
Memory Architecture
When accessing the FM24C64C, the user addresses
8,192 locations each with 8 data bits. These data bits
are shifted serially. The 8,192 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), and an extended 16-bit address. Only the
lower 13 bits are used by the decoder for accessing
the memory. The upper three address bits should be
set to 0 for compatibility with larger devices in the
future.
The memory is read or written at the speed of the
two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation is complete. This is explained in more
detail in the interface section below.
Users can expect several obvious system benefits
from the FM24C64C due to its fast write cycle and
high endurance as compared with EEPROM.
However there are less obvious benefits as well. For
example in a high noise environment, the fast-write
operation is less susceptible to corruption than an
EEPROM since it is completed quickly. By contrast,
an EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C64C always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. Figure 3
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
Electrical Specifications section.
VDD
Rmin = 1.8 Kohm
Rmax = tR/Cbus
Microcontroller
SDA
SCL
SDA
SCL
FM24C64C
FM24C64C
A0 A1 A2
A0 A1 A2
Figure 2. Typical System Configuration
Note that the FM24C64C contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within datasheet tolerances to
prevent incorrect operation.
Rev. 1.1
June 2011
3 of 12
FM24C64C
Figure 3. Data Transfer Protocol
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
If an operation is pending when a stop is asserted, the
operation will be aborted. The master must have
control of SDA (not a memory read) in order to assert
a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C64C for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8th data bit
has been transferred in any transaction. During this
state the transmitter should release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the condition
is a No-Acknowledge and the operation is aborted.
Rev. 1.1
June 2011
The receiver could fail to acknowledge for two
distinct reasons. First, if a byte transfer fails, the NoAcknowledge ends the current operation so that the
device can be addressed again. This allows the last
byte to be recovered in the event of a
communication error. Second and most common,
the receiver does not acknowledge the data to
deliberately end an operation. For example, during a
read operation, the FM24C64C will continue to
place data onto the bus as long as the receiver sends
acknowledges (and clocks). When a read operation
is complete and no more data is needed, the receiver
must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the
FM24C64C to attempt to drive the bus on the next
clock while the master is sending a new command
such as a Stop command.
Slave Address
The first byte that the FM24C64C expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the Slave ID
(device type), the device select address bits, and a
bit that specifies if the transaction is a read or a
write. Bits 7-4 define the device type and must be
set to 1010b for the FM24C64C. These bits allow
other types of function types to reside on the 2-wire
bus within an identical address range. Bits 3-1 are
the select bits which are equivalent to chip select
bits. They must match the corresponding value on
the external address pins to select the device. Up to
eight FM24C64Cs can reside on the same two-wire
bus by assigning a different address to each. Bit 0 is
the read/write bit. A 1 indicates a read operation,
and a 0 indicates a write.
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FM24C64C
Memory Operation
Device
Select
Slave
ID
1
0
1
0
A2
A1 A0 R/W
7
6
5
4
3
2
1
0
Figure 4. Slave Address
Addressing Overview
After the FM24C64C (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB (upper byte).
Since the device uses only 13 address bits, the value
of the upper three bits are don’t care. Following the
MSB is the LSB (lower byte) with the remaining
eight address bits. The address value is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch, either a
newly written value or the address following the last
access. The current address will be held as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte and just prior to
the acknowledge, the FM24C64C increments the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing
externally. After the last address (1FFFh) is reached,
the address latch will roll over to 0000h. There is no
limit to the number of bytes that can be accessed with
a single read or write operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24C64C can begin. For a read operation, the
FM24C64C will place 8 data bits on the bus then
wait for an Acknowledge from the master. If the
Acknowledge occurs, the FM24C64C will transfer
the next sequential byte. If the Acknowledge is not
sent, the FM24C64C will end the read operation. For
a write operation, the FM24C64C will accept 8 data
bits from the master and then send an Acknowledge.
All data transfer occurs MSB (most significant bit)
first.
Rev. 1.1
June 2011
The FM24C64C is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C64C and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is no write delay with FRAM. The entire
memory cycle occurs in less time than a single bus
clock. Therefore, any operation including a read or
write can occur immediately following a write.
Acknowledge polling, a technique used with
EEPROMs to determine if a write is complete is
unnecessary and will always return a ready
condition.
Internally, the actual memory write occurs after the
8th data bit is transferred. It will be complete before
the Acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using a Start or Stop
condition prior to the 8th data bit. The FM24C64C
uses no page buffering.
Portions of the memory array can be write protected
using the WP pin. Pulling the WP pin high (VDD)
will write-protect addresses in the upper quadrant
from 1800h to 1FFFh. The FM24C64C will not
acknowledge data bytes that are written to protected
addresses. In addition, the address counter will not
increment if writes are attempted to these addresses.
Pulling WP low (VSS) will deactivate this feature.
WP should not be left floating.
Figures 5 and 6 illustrate both a single-byte and
multiple-byte write cases.
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FM24C64C
Start
By Master
S
Stop
Address & Data
Slave Address
0 A
Address MSB
By F-RAM
A
Address LSB
A
Data Byte
A
P
Acknowledge
Figure 5. Byte Write
Start
S
By F-RAM
Stop
Address & Data
By Master
Slave Address
0 A
Address MSB
A
Address LSB
A
Data Byte
A
Data Byte
A
P
Acknowledge
Figure 6. Multiple-Byte Write
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24C64C uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
The FM24C64C uses an internal latch to supply the
address for a read operation. A current address read
uses the existing value in the address latch as a
starting place for the read operation. The system
reads from the address immediately following that of
the last operation.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the
FM24C64C will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte, this
indicates that the FM24C64C should read out the
next sequential byte.
Rev. 1.1
June 2011
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
likely create a bus contention as the FM24C64C
attempts to read out additional data onto the bus. The
four valid methods are:
1.
2.
3.
4.
The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in Figures 7-9. This is the
preferred method.
The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
The bus master issues a stop in the 9th clock
cycle.
The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the device address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the address bytes
that are loaded into the internal address latch. After
the FM24C64C acknowledges the address, the bus
master issues a start condition. This simultaneously
6 of 12
FM24C64C
aborts the write operation and allows the read
command to be issued with the device address LSB
By Master
Start
set to a 1. The operation is now a current address
read.
No
Acknowledge
Address
Stop
S
Slave Address
By F-RAM
1 A
Data Byte
Acknowledge
1
P
Data
Figure 7. Current Address Read
By Master
Start
Address
No
Acknowledge
Acknowledge
Stop
S
Slave Address
By F-RAM
1 A
Data Byte
A
Acknowledge
Data Byte
1 P
Data
Figure 8. Sequential Read
Start
Address
By Master
Start
No
Acknowledge
Address
Stop
S
By F-RAM
Slave Address
0 A X
Address MSB
A
Address LSB
A
S
Slave Address
1 A
Data Byte
1 P
Data
Acknowledge
Figure 9. Selective (Random) Read
Endurance
The FM24C64C internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C64C,
a row is 64 bits wide. Every 8-byte boundary marks
Rev. 1.1
June 2011
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, FRAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same segment, 10 years time will
elapse before 1 trillion endurance cycles occur.
7 of 12
FM24C64C
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any signal pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V *
-55C to + 125C
260 C
2.5kV
1.25kV
100V
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of
this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device
reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Main Power Supply
4.5
5.0
5.5
V
IDD
VDD Supply Current
@ SCL = 100 kHz
100
A
@ SCL = 400 kHz
200
A
@ SCL = 1 MHz
400
A
ISB
Standby Current
4
10
A
ILI
Input Leakage Current
±1
A
ILO
Output Leakage Current
±1
A
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VOL
Output Low Voltage
0.4
V
@ IOL = 3 mA
RIN
Input Resistance (WP, A2-A0)
For VIN = VIL (max)
40
K
For VIN = VIH (min)
1
M
VHYS
Input Hysteresis
0.05 VDD
V
Notes
1
2
3
3
5
4
Notes
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is strong (40K) when the input voltage is below V IL and much weaker (1M)
when the input voltage is above VIH.
Rev. 1.1
June 2011
8 of 12
FM24C64C
AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified)
Symbol Parameter
Min Max Min Max Min Max
fSCL
SCL Clock Frequency
0
100
0
400
0
1000
tLOW
Clock Low Period
4.7
1.3
0.6
tHIGH
Clock High Period
4.0
0.6
0.4
tAA
SCL Low to SDA Data Out Valid
3
0.9
0.55
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
tSP
Bus Free Before New
Transmission
Start Condition Hold Time
Start Condition Setup for Repeated
Start
Data In Hold
Data In Setup
Input Rise Time
Input Fall Time
Stop Condition Setup
Data Output Hold
(from SCL @ VIL)
Noise Suppression Time Constant
on SCL, SDA
Units
kHz
s
s
s
4.7
1.3
0.5
s
4.0
4.7
0.6
0.6
0.25
0.25
s
s
0
250
0
100
0
100
300
100
ns
ns
ns
ns
s
ns
50
ns
1000
300
4.0
0
300
300
0.6
0
50
0.25
0
50
Notes
1
1
Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.
1 This parameter is periodically sampled and not 100% tested.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V)
Symbol
Parameter
CI/O
Input/output capacitance (SDA)
CIN
Input capacitance
Max
8
6
Units
pF
pF
Notes
1
1
Notes
1 This parameter is periodically sampled and not 100% tested.
Power Cycle Timing
VDD
VDD min.
tVR
tVF
tPU
tPD
SDA,SCL
Power Cycle Timing (TA = -40C to +85C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol Parameter
Min
Max
tPU
Power Up (VDD min) to First Access (Start condition)
1
tPD
Last Access (Stop condition) to Power Down (VDD min)
0
tVR
VDD Rise Time
30
tVF
VDD Fall Time
100
Notes
1. Slope measured at any point on VDD waveform.
Rev. 1.1
June 2011
Units
Notes
ms
s
s/V
s/V
1
1
9 of 12
FM24C64C
AC Test Conditions
Equivalent AC Load Circuit
Input Pulse Levels
Input rise and fall times
Input and output timing levels
5.5V
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
1700 
Diagram Notes
All start and stop timing parameters apply to both read and write
cycles. Clock specifications are identical for read and write cycles.
Write timing parameters apply to slave address, word address, and
write data bits. Functional relationships are illustrated in the relevant
data sheet sections. These diagrams illustrate the timing parameters
only.
Output
100 pF
Read Bus Timing
tR
tF
t HIGH
t SP
t LOW
t SP
SCL
t SU:SDA
1/fSCL
t BUF
t HD:DAT
t SU:DAT
SDA
Start
t DH
t AA
Stop Start
Acknowledge
Write Bus Timing
t HD:DAT
SCL
t HD:STA
t SU:STO
t SU:DAT
t AA
SDA
Start
Data Retention
Symbol
Parameter
TDR
@ +85ºC
@ +80ºC
@ +75ºC
Rev. 1.1
June 2011
Stop Start
Acknowledge
Min
10
18
36
Max
-
Units
Years
Years
Years
Notes
10 of 12
FM24C64C
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
0.65
1.27
Pin 1
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.19
0.25
45
0.10 mm
0-8
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXX-P
LLLLLLL
RICYYWW
Legend:
XXXXXX= part number, P= package type
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM24C64C, “Green” SOIC package, Year 2010, Work Week 47
FM24C64C-G
A00002G1
RIC1047
Rev. 1.1
June 2011
11 of 12
FM24C64C
Revision History
Revision
1.0
1.1
Rev. 1.1
June 2011
Date
3/22/2011
6/30/2011
Summary
Initial Release
Added ESD ratings.
12 of 12
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