IRF IRMCK371TR Sensorless motor control ic for appliance Datasheet

Data Sheet No. PD60336
IRMCK371
Sensorless Motor Control IC for Appliances
Features
Product Summary
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TM
MCE (Motion Control Engine) - Hardware based
computation engine for high efficiency sinusoidal
sensorless control of permanent magnet AC motor
Support Induction motor sensorless FOC control
Supports both interior and surface permanent
magnet motors
Built-in hardware peripheral for single shunt
current feedback reconstruction
No external current or voltage sensing operational
amplifier required
Three/two-phase Space Vector PWM
Analog output (PWM)
Embedded 8-bit high speed microcontroller (8051)
for flexible I/O and man-machine control
JTAG programming port for emulation/debugger
Serial communication interface (UART)
I2C/SPI serial interface
Watchdog timer with independent analog clock
Three general purpose timers/counters
Two special timers: periodic timer, capture timer
Internal ‘One-Time Programmable’ (OTP) memory
and internal RAM for final production usage
Pin compatible with IRMCF371, RAM version
60 MHz
Maximum internal clock (SYSCLK) frequency
128 MHz
Maximum 8051 clock frequency
33 MHz
Sensorless control computation time
TM
MCE
computation data range
11 μsec typ
16 bit signed
8051 OTP Program memory
64K bytes
MCE program and Data RAM
8K bytes
GateKill latency (digital filtered)
2 μsec
PWM carrier frequency counter
16 bits/ SYSCLK
A/D input channels
4
A/D converter resolution
12 bits
A/D converter conversion speed
2 μsec
8051 instruction execution speed
Analog output (PWM) resolution
UART baud rate (typ)
2 SYSCLK
8 bits
57.6K bps
Number of I/O (max)
Package (lead-free)
Operating temperature
85°C
13
QFP48
-40°C ~
1.8V/3.3V CMOS
Description
IRMCK371 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK371 is
designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control.
IRMCK371 contains two computation engines. One is Motion Control Engine (MCETM) for sensorless control of permanent
magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one
monolithic chip. The MCETM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle
estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by
connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the
Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit
and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle
instruction execution (16MIPS at 33MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process
signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the
MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments.
IRMCK371 comes with a small QFP48 pin lead-free package..
Rev 1.0
IRMCK371
TABLE OF CONTENTS
1
2
3
4
Overview ....................................................................................................................................5
IRMCK371 Block Diagram and Main Functions.........................................................................6
Pinout.........................................................................................................................................8
Input/Output of IRMCK371.........................................................................................................9
4.1 8051 Peripheral Interface Group .......................................................................................10
4.2 Motion Peripheral Interface Group ....................................................................................10
4.3 Analog Interface Group .....................................................................................................11
4.4 Power Interface Group ......................................................................................................11
4.5 Test Interface Group .........................................................................................................11
5 Application Connections ..........................................................................................................12
6 DC Characteristics ...................................................................................................................13
6.1 Absolute Maximum Ratings...............................................................................................13
6.2 System Clock Frequency and Power Consumption ..........................................................13
6.3 Digital I/O DC Characteristics............................................................................................14
6.4 PLL and Oscillator DC characteristics...............................................................................14
6.5 Analog I/O DC Characteristics ..........................................................................................15
6.6 Under Voltage Lockout DC characteristics........................................................................15
6.7 AREF Characteristics ........................................................................................................15
7 AC Characteristics ...................................................................................................................16
7.1 PLL AC Characteristics .....................................................................................................16
7.2 Analog to Digital Converter AC Characteristics.................................................................17
7.3 Op Amp AC Characteristics ..............................................................................................17
7.4 SYNC to SVPWM and A/D Conversion AC Timing ...........................................................18
7.5 GATEKILL to SVPWM AC Timing .....................................................................................19
7.6 Interrupt AC Timing ...........................................................................................................19
7.7 I2C AC Timing....................................................................................................................20
7.8 SPI AC Timing...................................................................................................................21
7.8.1 SPI Write AC timing ....................................................................................................21
7.8.2 SPI Read AC Timing...................................................................................................22
7.9 UART AC Timing...............................................................................................................23
7.10
CAPTURE Input AC Timing ...........................................................................................24
7.11
JTAG AC Timing ............................................................................................................25
7.12
OTP Programming Timing .............................................................................................26
8 I/O Structure.............................................................................................................................27
9 Pin List .....................................................................................................................................30
10
Package Dimensions ............................................................................................................32
11
Part Marking Information ......................................................................................................33
12
Order Information .................................................................................................................33
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IRMCK371
TABLE OF FIGURES
Figure 1. Typical Application Block Diagram Using IRMCK371.....................................................5
Figure 2. IRMCK371 Internal Block Diagram.................................................................................6
Figure 3. IRMCK371 Pin Configuration..........................................................................................8
Figure 4. Input/Output of IRMCK371 .............................................................................................9
Figure 5. Application Connection of IRMCK371 ..........................................................................12
Figure 6. Clock Frequency vs. Power Consumption....................................................................13
Figure 7 Crystal oscillator circuit..................................................................................................16
Figure 8 Voltage droop of sample and hold .................................................................................17
Figure 9 SYNC to SVPWM and A/D Conversion AC Timing .......................................................18
Figure 10 GATEKILL to SVPWM AC Timing ...............................................................................19
Figure 11 Interrupt AC Timing .....................................................................................................19
Figure 12 I2C AC Timing ..............................................................................................................20
Figure 13 SPI write AC Timing.....................................................................................................21
Figure 14 SPI read AC Timing .....................................................................................................22
Figure 15 UART AC Timing .........................................................................................................23
Figure 16 CAPTURE Input AC Timing.........................................................................................24
Figure 17 JTAG AC Timing..........................................................................................................25
Figure 18 OTP Programming Timing ...........................................................................................26
Figure 19 All digital I/O except motor PWM output.........................................................................27
Figure 20 RESET, GATEKILL I/O ..................................................................................................27
Figure 21 Analog input ...................................................................................................................28
Figure 22 Analog operational amplifier output and AREF I/O structure.......................................28
Figure 23 VPP programming pin I/O structure ..........................................................................28
Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................29
Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................29
Figure 26 XTAL0/XTAL1 pins structure .......................................................................................29
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IRMCK371
TABLE OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Absolute Maximum Ratings ...........................................................................................13
System Clock Frequency ...............................................................................................13
Digital I/O DC Characteristics ........................................................................................14
PLL DC Characteristics .................................................................................................14
Analog I/O DC Characteristics .......................................................................................15
UVcc DC Characteristics ...............................................................................................15
AREF DC Characteristics ..............................................................................................15
PLL AC Characteristics..................................................................................................16
A/D Converter AC Characteristics .................................................................................17
Current Sensing OP amp Amp AC Characteristics......................................................17
SYNC AC Characteristics ............................................................................................18
GATEKILL to SVPWM AC Timing ...............................................................................19
Interrupt AC Timing......................................................................................................19
I2C AC Timing ..............................................................................................................20
SPI Write AC Timing ....................................................................................................21
SPI Read AC Timing....................................................................................................22
UART AC Timing .........................................................................................................23
CAPTURE AC Timing ..................................................................................................24
JTAG AC Timing ..........................................................................................................25
OTP Programming Timing ...........................................................................................26
Pin List .........................................................................................................................31
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IRMCK371
1 Overview
IRMCK371 is a new International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled appliance motor control applications. Unlike a
traditional microcontroller or DSP, the IRMCK371 provides a built-in closed loop sensorless
control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet motors.
The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion
control sequencer and dual port RAM to map internal signal nodes. IRMCK371 also employs a
unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and
enables a direct shunt resistor interface to the IC. Motion control programming is achieved using
a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment.
Sequencing, user interface, host communication, and upper layer control tasks can be
implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped
with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application
schematic using the IRMCK371.
IRMCF371 is intended for development purpose and contains 48K bytes of RAM, which can be
loaded from external EEPROM for 8051 program execution. For high volume production,
IRMCK371 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCK371 and
IRMCK371 come in the same 48-pin QFP package with identical pin configuration to facilitate PC
board layout and transition to mass production
Figure 1.
Typical Application Block Diagram Using IRMCK371
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IRMCK371
2 IRMCK371 Block Diagram and Main Functions
Figure 2.
Motion Control Bus
8bit uP Address/Data bus
IRMCK371 block diagram is shown in Figure 2.
IRMCK371 Internal Block Diagram
IRMCK371 contains the following functions for sensorless AC motor control applications:
•
Motion Control Engine (MCETM)
o Proportional plus Integral block
o Low pass filter
o Differentiator and lag (high pass filter)
o Ramp
o Limit
o Angle estimate (sensorless control)
o Inverse Clark transformation
o Vector rotator
o Bit latch
o Peak detect
o Transition
o Multiply-divide (signed and unsigned)
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IRMCK371
o
o
o
o
o
o
o
o
o
o
o
o
o
•
Divide (signed and unsigned)
Adder
Subtractor
Comparator
Counter
Accumulator
Switch
Shift
ATAN (arc tangent)
Function block (any curve fitting, nonlinear function)
16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)
MCETM program and data memory (6K byte). Note 1
MCETM control sequencer
8051 microcontroller
o Three 16-bit timer/counters
o 16-bit periodic timer
o 16-bit analog watchdog timer
o 16-bit capture timer
o Up to 13 discrete I/Os
o Four-channel 12-bit A/D
ƒ One buffered channel for current sensing (0 – 1.2V input)
ƒ Three unbuffered channels (0 – 1.2V input)
o JTAG port (4 pins)
o One channel of analog output (8-bit PWM)
o UART
o I2C/SPI port
o 64K byte program OTP
o 2K byte data RAM. Note 1
Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051
data. Different sizes can be allocated depending on applications.
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IRMCK371
P3.2/INT0
VSS
SCL/SO-SI/VPP
SDA/CS0
P5.1/TMS
P5.2/TDO
P5.3/TDI
TCK
NC
RESET
PLLVDD
PLLVSS
3 Pinout
48 47 46 45 44 43 42 41 40 39 38 37
XTAL0
1
36
P3.0/INT2/CS1
XTAL1
2
35
PWMUH
P1.0/T2
3
34
PWMUL
P1.1/RXD
4
33
PWMVH
P1.2/TXD
5
32
PWMVL
P1.3/SYNC/SCK
6
31
PWMWH
P1.4/CAP
7
30
PWMWL
VDD2
8
29
GATEKILL
VSS
9
28
VDD1
VDD1
10
27
VSS
P2.0/NMI
11
26
VDD2
P2.1
12
25
AIN2
(Top View)
Figure 3.
IFBO
IFB+
IFB-
AREF
CMEXT
AIN1
AVSS
AVDD
AIN0
VSS
VDD2
P2.6/AOPWM
13 14 15 16 17 18 19 20 21 22 23 24
IRMCK371 Pin Configuration
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IRMCK371
4 Input/Output of IRMCK371
All I/O signals of IRMCK371 are shown in Figure 4. All I/O pins are 3.3V logic interface except
A/D interface pins.
XTAL0
XTAL1
Crystal
RS232C
Interface
P1.2/TXD
P1.1/RXD
I2C
Interface
Discrete I/O
SDA/CS0
SCL/SO-S/VPPI
P1.0/T2
P1.3/SYNC/SCK
P1.4/CAP
P2.0/NMI
P2.1
P3.0/INT2/CS1
P3.2/INT0
System Reset
D/A Interface
(PWM output)
PWM gate signal
Interface
AVDD
AVSS
AREF
CMEXT
RESET
P5.3/TDI
TCK
P5.1/TSM
P5.2/TDO
JTAG port
OTP programming
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
P2.6/AOPWM
SCL/SO-S/VPPI
Figure 4.
IFB+
IFBIFBO
AIN0
AIN1
AIN2
A/D Interface
VDD1
VDD2
VSS
Digital power/
ground
PLLVDD
PLLVSS
PLL power/
ground
Input/Output of IRMCK371
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4.1
8051 Peripheral Interface Group
UART Interface
P1.2/TXD
P1.1/RXD
Output, Transmit data from IRMCK371, can be configured as P1.2
Input, Receive data to IRMCK371, can be configured as P1.1
Discrete I/O Interface
P1.0/T2
Input/output port 1.0, can be configured as Timer 2 input
P1.1/RXD
Input/output port 1.1, can be configured as RXD input
P1.2/TXD
Input/output port 1.2, can be configured as TXD output
P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock
P1.4/CAP
Input/output port 1.4, can be configured as Capture Timer input
P2.0/NMI
Input/output port 2.0, can be configured as non-maskable interrupt input
P2.1
Input/output port 2.1
P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select
1
P3.2/INT0
Input/output port 3.2, can be configured as INT0 input
Analog Output Interface
AOPWM
Output, PWM output 0, 8-bit resolution, configurable carrier frequency
Crystal Interface
XTAL0
XTAL1
Reset Interface
RESET
I2C/SPI Interface
SCL/SO-SI
SDA/CS0
P3.0/INT2/CS1
P1.3/SYNC/SCK
4.2
Input, connected to crystal
Output, connected to crystal
Inout, system reset, needs to be pulled up to VDD1 but doesn’t require
external RC time constant
Input/output, I2C clock output or SPI data
Input/output, I2C Data line or SPI chip select 0
Input/output, INT2 or SPI chip select 1
Input/output, SYNC output or SPI clock, needs to be pulled up to VDD1
in order to boot from I2C EEPROM
Motion Peripheral Interface Group
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Fault
GATEKILL
Rev 1.0
Output, PWM phase U high side gate signal
Output, PWM phase U low side gate signal
Output, PWM phase V high side gate signal
Output, PWM phase V low side gate signal
Output, PWM phase W high side gate signal
Output, PWM phase W low side gate signal
Input, upon assertion, this negates all six PWM signals, programmable
logic sense
IRMCK371
4.3
Analog Interface Group
AVDD
AVSS
AREF
CMEXT
IFB+
IFBIFBO
AIN0
AIN1
AIN2
4.4
Power Interface Group
VDD1
VDD2
VSS
PLLVDD
PLLVSS
4.5
Analog power (1.8V)
Analog power return
0.6V buffered output
Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be
connected.
Input, Operational amplifier positive input for shunt resistor current
sensing
Input, Operational amplifier negative input for shunt resistor current
sensing
Output, Operational amplifier output for shunt resistor current sensing
Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus
voltage input
Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to
AVSS if unused
Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to
AVSS if unused
Digital power for I/O (3.3V)
Digital power for core logic (1.8V)
Digital common
PLL power (1.8V)
PLL ground return
Test Interface Group
TSTMOD
P5.1/TSM
P5.2/TDO
P5.3/TDI
TCK
Must be tied to VSS, used only for factory testing.
Input/output port 5.1, configured as JTAG port by default
Input/output port 5.2, configured as JTAG port by default
Input/output port 5.3, configured as JTAG port by default
Input, JTAG test clock
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IRMCK371
5 Application Connections
Typical application connection is shown in Figure 5. All components necessary to implement a
complete sensorless drive control algorithm are shown connected to IRMCK371.
System
Clock
XTAL0
XTAL1
4MHz
Crystal
1.8V
Host
Microcontroller
(RS232C)
PLLVDD
PLLVSS
P1.2/TXD
P1.1/RXD
SDA/CS0
SCL/SO-SI
Other Communication
(I2C or SPI)
P1.0/T2
P1.3/SYNC/SCK
Digital I/O
Control
PLL
Logic
Motion
Control
Modules
RS232C
Dual
Port
Memory
(1Kbyte)
&
MCE
Memory
(3kByte)
I2C/SPI
P1.4/CAP
PORT1
P2.0/NMI
P2.1
PORT2
P3.0/INT2/CS1
P3.2/INT0
System
clock
Low Loss
Space
Vector
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
GATEKILL
Motion
Control
Sequencer
PORT3
0.6V
IFBC+
P2.6/AOPWM0
Analog Output
S/H
PWM0
Timers
P5.3/TDI
P5.1/TSM
JTAG
Control
P5.2/TDO
RESET
Power
OTP Programming
6.5V
3.3V
1.8V
IFBCO
Watchdog
Timer
TCLK
JTAG Port
Interface 5
RESET
12bit
A/D
&
MUX
Local
RAM
4kByte
System
Reset
Motor
DC bus shunt
resistor
IFBC-
AIN0
DC bus
voltage
AIN1
AIN2
AREF
Other analog input (0-1.2V)
Optional External Voltage
Reference (0.6V)
CMEXT
Program
OTP ROM
(64kByte)
SCL/SO-SI
VDD1
VDD2
AVDD
1.8V
AVSS
VSS
8051
CPU
Figure 5.
Clock
divider
System
clock
Application Connection of IRMCK371
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IRMCK371
6 DC Characteristics
6.1
Absolute Maximum Ratings
Symbol
VDD1
VDD2
VIA
VID
TA
TS
Parameter
Supply Voltage
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Ambient Temperature
Storage Temperature
Table 1.
Min
Typ
Max
-0.3 V
3.6 V
-0.3 V
1.98 V
-0.3 V
1.98 V
-0.3 V
3.65 V
-40 ˚C
85 ˚C
-65 ˚C
150 ˚C
Absolute Maximum Ratings
Condition
Respect to VSS
Respect to VSS
Respect to AVSS
Respect to VSS
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only and function of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications are not
implied.
6.2
System Clock Frequency and Power Consumption
Symbol
SYSCLK
8051CLK
Parameter
System Clock
8051 Clock
Table 2.
Min
Typ
Max
32
128
32
System Clock Frequency
Unit
MHz
MHz
Power Consumption
180
160
140
Power (mW)
120
100
80
1.8V
3.3V
60
Total Power
40
20
0
0
Figure 6.
20
40
60
80
100
120
140
MCE Frequency (MHz)
Clock Frequency vs. Power Consumption
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IRMCK371
6.3
Digital I/O DC Characteristics
Symbol
VDD1
VDD2
VIL
VIH
CIN
IL
IOL1(2)
IOH1(2)
IOL2(3)
IOH2(3)
Parameter
Supply Voltage
Supply Voltage
Input Low Voltage
Input High Voltage
Input capacitance
Input leakage current
Low level output
current
High level output
current
Low level output
current
High level output
current
Table 3.
Min
3.0 V
1.62 V
-0.3 V
2.0 V
-
Typ
3.3 V
1.8 V
-
8.9 mA
3.6 pF
±10 nA
13.2 mA
Max
3.6 V
1.98 V
0.8 V
3.6 V
±1 μA
15.2 mA
Condition
Recommended
Recommended
Recommended
Recommended
12.4 mA
24.8 mA
38 mA
VOH
(1)
= 2.4 V
17.9 mA
26.3 mA
33.4 mA
VOL
(1)
= 0.4 V
24.6 mA
49.5 mA
81 mA
VOH
(1)
= 2.4 V
(1)
VO = 3.3 V or 0 V
VOL = 0.4 V
(1)
Digital I/O DC Characteristics
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P2.0/NMI, P2.1,
P2.6/AOPWM0, P3.0/INT2/CS1, P3.2/INT0, P5.1/TMS, P5.2/TDO, P5.3/TDI, GATEKILL,
PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, PWMWH pins.
6.4
PLL and Oscillator DC characteristics
Symbol
VPLLVDD
VIL OSC
VIH OSC
Parameter
Min
Typ
Max
Supply Voltage
1.62 V
1.8 V
1.92 V
Oscillator Input Low
VPLLVSS
0.2*
Voltage
VPLLVDD
Oscillator Input High
0.8*
VPLLVDD
Voltage
VPLLVDD
Table 4. PLL DC Characteristics
Condition
Recommended
VPLLVDD = 1.8 V
(1)
VPLLVDD
(1)
= 1.8 V
Note:
(1) Data guaranteed by design.
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IRMCK371
6.5
Analog I/O DC Characteristics
- OP amp for current sensing (IFB+, IFB-, IFBO)
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
VAVDD
Supply Voltage
1.71 V
1.8 V
VOFFSET
Input Offset Voltage
VI
Input Voltage Range
0V
VOUTSW
OP amp output
50 mV
(1)
operating range
CIN
Input capacitance
3.6 pF
RFDBK
OP amp feedback
5 kΩ
resistor
OP GAINCL
CMRR
ISRC
ISNK
Operating Close loop
Gain
Common Mode
Rejection Ratio
Op amp output
source current
Op amp output sink
current
Table 5.
Max
1.89 V
26 mV
1.2 V
1.2 V
Condition
Recommended
VAVDD = 1.8 V
Recommended
VAVDD = 1.8 V
20 kΩ
(1)
Requested
between IFBO
and IFB-
80 db
-
-
(1)
-
80 db
-
(1)
-
1 mA
-
VOUT
(1)
= 0.6 V
-
100 μA
-
VOUT
(1)
= 0.6 V
Analog I/O DC Characteristics
Note:
(1) Data guaranteed by design.
6.6
Under Voltage Lockout DC characteristics
Unless specified, Ta = 25˚C, AVDD (1.8V)
Symbol
Parameter
Min
Typ
Max
UVCC+
UVcc positive going
1.53 V
1.66 V
1.71 V
Threshold1)
UVCCUVcc negative going
1.52 V
1.62 V
1.71 V
Threshold
UVCCH
UVcc Hysteresys
40 mV
Table 6. UVcc DC Characteristics
Note:
(1) Data guaranteed by design.
6.7
Condition
VDD1 = 3.3 V
VDD1 = 3.3 V
AREF Characteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
VAREF
AREF Output Voltage
495 mV
600 mV
700 mV
Load regulation (VDC-0.6)
1 mV
ΔVo
PSRR
Power Supply Rejection
75 db
Ratio
Table 7. AREF DC Characteristics
Note: (1) Data guaranteed by design.
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Condition
VAVDD = 1.8 V
(1)
(1)
© 2007 International Rectifier
15
IRMCK371
7 AC Characteristics
7.1
PLL AC Characteristics
Symbol
FCLKIN
FPLL
FLWPW
JS
D
TLOCK
Parameter
Min
Typ
Max
Crystal input
3.2 MHz
4 MHz
60 MHz
frequency
Internal clock
32 MHz
50 MHz
128 MHz
frequency
Sleep mode output FCLKIN ÷ 256
frequency
Short time jitter
200 psec
Duty cycle
50 %
PLL lock time
500 μsec
Table 8. PLL AC Characteristics
Condition
(1)
(see figure below)
(1)
(1)
(1)
(1)
(1)
Note:
(1) Data guaranteed by design.
R1=1M
R2=10
Xtal
C1=30PF
C2=30PF
Figure 7
Crystal oscillator circuit
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© 2007 International Rectifier
16
IRMCK371
7.2
Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
TCONV
Conversion time
THOLD
Sample/Hold
maximum hold time
Min
-
Typ
-
Max
2.05 μsec
10 μsec
Condition
(1)
Voltage droop ≤
15 LSB
(see figure below)
Table 9. A/D Converter AC Characteristics
Note:
(1) Data guaranteed by design.
Input Voltage
Voltage droop
S/H Voltage
tSAMPLE
THOLD
Figure 8
7.3
Voltage droop of sample and hold
Op Amp AC Characteristics
- OP amps for current sensing (IFB+, IFB-, IFBO)
Unless specified, Ta = 25˚C.
Symbol
Parameter
OPSR
OP amp slew rate
OPIMP
TSET
OP input impedance
Settling time
Table 10.
Min
-
Typ
10 V/μsec
Max
-
-
108 Ω
400 ns
-
Condition
VAVDD = 1.8 V, CL
= 33 pF (1)
(1)
VAVDD = 1.8 V, CL
= 33 pF (1)
Current Sensing OP amp Amp AC Characteristics
Note:
(1) Data guaranteed by design.
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© 2007 International Rectifier
17
IRMCK371
7.4
SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Figure 9
SYNC to SVPWM and A/D Conversion AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
twSYNC
SYNC pulse width
tdSYNC1
SYNC to current
feedback conversion
time
tdSYNC2
SYNC to AIN0-6
analog input
conversion time
tdSYNC3
SYNC to PWM output
delay time
Table 11.
Min
-
Typ
32
-
Max
100
Unit
SYSCLK
SYSCLK
-
-
200
SYSCLK
-
-
2
SYSCLK
(1)
SYNC AC Characteristics
Note:
(1) AIN1 through AIN6 channels are converted once every 6 SYNC events
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© 2007 International Rectifier
18
IRMCK371
7.5
GATEKILL to SVPWM AC Timing
Figure 10
GATEKILL to SVPWM AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twGK
GATEKILL pulse width
32
tdGK
GATEKILL to PWM
100
output delay
Table 12. GATEKILL to SVPWM AC Timing
7.6
Unit
SYSCLK
SYSCLK
Interrupt AC Timing
Figure 11
Interrupt AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twINT
INT0, INT1 Interrupt
4
Assertion Time
tdINT
INT0, INT1 latency
4
Table 13. Interrupt AC Timing
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Unit
SYSCLK
SYSCLK
© 2007 International Rectifier
19
IRMCK371
7.7
I2C AC Timing
TI2CLK
TI2CLK
SCL
tI2ST1
tI2WSETUP
tI2WHOLD
tI2RSETUP
tI2EN1
tI2RHOLD
tI2ST2
tI2EN2
SDA
Figure 12
Unless specified, Ta = 25˚C.
Symbol
Parameter
2
TI2CLK
I C clock period
tI2ST1
I2C SDA start time
tI2ST2
I2C SCL start time
tI2WSETUP
I2C write setup time
tI2WHOLD
I2C write hold time
tI2RSETUP
I2C read setup time
tI2RHOLD
I2C read hold time
I2C AC Timing
Min
Typ
10
0.25
0.25
0.25
0.25
2
(1)
I C filter time
1
Table 14. I2C AC Timing
Max
8192
-
Unit
SYSCLK
TI2CLK
TI2CLK
TI2CLK
TI2CLK
SYSCLK
SYSCLK
Note:
(1) I2C read setup time is determined by the programmable filter time applied to I2C
communication.
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© 2007 International Rectifier
20
IRMCK371
7.8
SPI AC Timing
7.8.1 SPI Write AC timing
Figure 13
Unless specified, Ta = 25˚C.
Symbol
Parameter
TSPICLK
SPI clock period
tSPICLKHT
SPI clock high time
tSPICLKLT
SPI clock low time
tCSDELAY
CS to data delay time
tWRDELAY
CLK falling edge to data
delay time
tCSHIGH
CS high time between two
consecutive byte transfer
tCSHOLD
CS hold time
Table 15.
SPI write AC Timing
Min
4
-
Typ
1/2
1/2
-
Max
10
10
Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
1
-
-
TSPICLK
1
SPI Write AC Timing
TSPICLK
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© 2007 International Rectifier
21
IRMCK371
7.8.2 SPI Read AC Timing
Figure 14
Unless specified, Ta = 25˚C.
Symbol
Parameter
TSPICLK
SPI clock period
tSPICLKHT
SPI clock high time
tSPICLKLT
SPI clock low time
tCSRD
CS to data delay time
tRDSU
SPI read data setup time
tRDHOLD
SPI read data hold time
tCSHIGH
CS high time between two
consecutive byte transfer
tCSHOLD
CS hold time
Table 16.
SPI read AC Timing
Min
4
10
10
1
Typ
1/2
1/2
-
Max
10
-
1
SPI Read AC Timing
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Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
nsec
TSPICLK
TSPICLK
© 2007 International Rectifier
22
IRMCK371
7.9
UART AC Timing
TBAUD
TXD
Start Bit
Data and Parity Bit
Stop Bit
RXD
TUARTFIL
Figure 15
UART AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
TBAUD
Baud Rate Period
57600
TUARTFIL
UART sampling filter
1/16
period (1)
Table 17. UART AC Timing
Max
-
Unit
bit/sec
TBAUD
Note:
(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval
of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated.
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© 2007 International Rectifier
23
IRMCK371
7.10 CAPTURE Input AC Timing
Figure 16
CAPTURE Input AC Timing
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TCAPCLK
CAPTURE input period
8
tCAPHIGH
CAPTURE input high
4
time
tCAPLOW
CAPTURE input low
4
time
4
tCRDELAY
CAPTURE falling edge
to capture register latch
time
4
tCLDELAY
CAPTURE rising edge
to capture register latch
time
tINTDELAY
CAPTURE input
4
interrupt latency time
Table 18. CAPTURE AC Timing
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Unit
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
© 2007 International Rectifier
24
IRMCK371
7.11 JTAG AC Timing
TJCLK
TCK
tJHIGH
tJLOW
tCO
TDO
tJSETUP
tJHOLD
TDI/TMS
Figure 17
Unless specified, Ta = 25˚C.
Symbol
Parameter
TJCLK
TCK Period
tJHIGH
TCK High Period
tJLOW
TCK Low Period
tCO
TCK to TDO propagation
delay time
tJSETUP
TDI/TMS setup time
tJHOLD
TDI/TMS hold time
Table 19.
JTAG AC Timing
Min
10
10
0
Typ
-
4
0
JTAG AC Timing
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Max
50
5
Unit
MHz
nsec
nsec
nsec
-
nsec
nsec
© 2007 International Rectifier
25
7.12 OTP Programming Timing
Figure 18
Unless specified, Ta = 25˚C.
Symbol
Parameter
TVPS
VPP Setup Time
TVPH
VPP Hold Time
Table 20.
Rev 1.0
OTP Programming Timing
Min
Typ
Max
10
15
OTP Programming Timing
Unit
nsec
nsec
IRMCK371
8 I/O Structure
The following figure shows the motor PWM and digital I/O structure
VDD1
(3.3V)
Internal digital circuit
Low true logic
70k
6.0V
PIN
100
6.0V
VSS
Figure 19 All digital I/O except motor PWM output
The following figure shows RESET and GATEKILL I/O structure.
VDD1
(3.3V)
RESET
GATEKILL
I/O
70k
6.0V
PIN
100
6.0V
VSS
Figure 20 RESET, GATEKILL I/O
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© 2007 International Rectifier
27
IRMCK371
The following figure shows the analog input structure.
AVDD
Analog input
6.0V
PIN
100
Analog Circuit
6.0V
AVSS
Figure 21 Analog input
The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.
1.8V
Analog output
6.0V
PIN
Analog Circuit
6.0V
AVSS
Figure 22
Analog operational amplifier output and AREF I/O structure
The following figure shows the VPP pin I/O structure
VPP input
PIN
100
Analog Circuit
8.0V
VSS
Figure 23 VPP programming pin I/O structure
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© 2007 International Rectifier
28
The following figure shows the VSS, AVSS and PLLVSS pin structure
Figure 24 VSS, AVSS and PLLVSS pin structure
The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure
Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure
The following figure shows the XTAL0 and XTAL1 pins structure
VDD1
6.0V
PIN
6.0V
VSS
Figure 26
Rev 1.0
XTAL0/XTAL1 pins structure
IRMCK371
9 Pin List
Pin
Number
Pin Name
Internal
Pull-up
/Pull-down
Pin
Type
1
2
3
XTAL0
XTAL1
P1.0/T2
I
O
I/O
4
5
P1.1/RXD
P1.2/TXD
I/O
I/O
6
I/O
14
15
16
P1.3/SYNC/
SCK
P1.4/CAP
VDD2
VSS
VDD1
P2.0/NMI
P2.1
P2.6/AOPW
M
VDD2
VSS
AIN0
17
18
19
AVDD
AVSS
AIN1
P
P
I
20
CMEXT
O
21
22
23
24
25
AREF
IFBIFB+
IFBO
AIN2
O
I
I
O
I
26
27
28
29
VDD2
VSS
VDD1
GATEKILL
P
P
P
I
30
PWMWL
31
PWMWH
7
8
9
10
11
12
13
I/O
P
P
P
I/O
I/O
I/O
P
P
I
70 kΩ Pull
up
70 kΩ Pull
up
O
O
Description
Crystal input
Crystal output
Discrete programmable I/O or Timer/Counter 2
input
Discrete programmable I/O or UART receive input
Discrete programmable I/O or UART transmit
output
Discrete programmable I/O or SYNC output or SPI
clock output
Discrete programmable I/O or Capture Timer input
1.8V digital power
Digital common
3.3V digital power
Discrete I/O or Non Maskable Interrupt
Discrete I/O
Discrete I/O or PWM digital output
1.8V digital power
Digital common
Analog input channel 0, 0-1.2V range, needs to be
pulled down to AVSS if unused
1.8V analog power
Analog common
Analog input channel 1, 0-1.2V range, needs to be
pulled down to AVSS if unused
Unbuffered 0.6V output. Capacitor needs to be
connected.
Analog reference voltage output (0.6V)
Single shunt current sensing OP amp input (-)
Single shunt current sensing OP amp input (+)
Single shunt current sensing OP amp output
Analog input channel 2, 0-1.2V range, needs to be
pulled down to AVSS if unused
1.8V digital power
Digital common
3.3V digital power
PWM shutdown input, 2-μsec digital filter,
configurable either high or low true.
PWM gate drive for phase W low side, configurable
either high or low true
PWM gate drive for phase W high side,
configurable either high or low true
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© 2007 International Rectifier
30
IRMCK371
Pin
Number
Pin Name
Internal
Pull-up
/Pull-down
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
Pin
Type
32
PWMVL
O
33
PWMVH
34
PWMUL
35
PWMUH
36
I/O
37
P3.0/INT2/C
S1
P3.2/NINT0
38
39
40
41
42
43
44
45
VSS
SCL/SO-SI
SDA/CS0
P5.1/TMS
P5.2/TDO
P5.3/TDI
TCK
TSTMOD
P
I/O
I/O
I/O
I/O
I/O
I
I
46
47
48
RESET
PLLVDD
PLLVSS
O
O
O
I/O
58 kΩ pull
down
Description
PWM gate drive for phase V low side, configurable
either high or low true
PWM gate drive for phase V high side, configurable
either high or low true
PWM gate drive for phase U low side, configurable
either high or low true
PWM gate drive for phase U high side, configurable
either high or low true
Discrete programmable I/O or external interrupt 2
input or SPI chip select 1
Discrete programmable I/O or external interrupt 0
input
Digital common
I2C clock or SPI data
I2C data or SPI chip select 0
Discrete I/O or JTAG test mode select
Discrete I/O or JTAG test data output
Discrete I/O or JTAG test data input
JTAG test clock input
Test mode input, must be tied to VSS
I/O
Reset, low true, Schmitt trigger input
P
1.8V PLL power
P
PLL ground
Table 21. Pin List
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© 2007 International Rectifier
31
IRMCK371
10 Package Dimensions
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© 2007 International Rectifier
32
IRMCK371
11 Part Marking Information
12 Order Information
Lead-Free Part in 48-lead QFP
Moisture Sensitivity Rating – MSL3
Part number
IRMCK371TR
IRMCK371TY
Order quantities
2000 parts on tape and reel in dry pack
2500 parts on trays (160 parts per tray) in dry pack
The LQFP-48 is MSL3 qualified
This product has been designed and qualified for the industrial level
Qualification standards can be found at www.irf.com <http://www.irf.com>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/25/2007
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© 2007 International Rectifier
33
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