MC74VHC244 Octal Bus Buffer The MC74VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. The MC74VHC244 is a noninverting 3--state buffer, and has two active--low output enables. This device is designed to be used with 3--state memory address drivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. • High Speed: tPD = 3.9 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2 V to 5.5 V Operating Range • Low Noise: VOLP = 0.9 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: Human Body Model > 2000 V Machine Model > 200 V • Chip Complexity: 136 FETs • Pb--Free Packages are Available* A1 A2 A3 DATA INPUTS A4 B1 B2 B3 B4 OUTPUT ENABLES 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 YA3 YA4 NONINVERTING OUTPUTS YB2 YB3 YB4 Figure 1. Logic Diagram *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. March, 2006 -- Rev. 7 20 VHC244 AWLYYWWG 20 1 1 SOIC--20 WB DW SUFFIX CASE 751D 20 VHC 244 ALYW 20 1 1 TSSOP--20 DT SUFFIX CASE 948E 20 74VHC244 AWLYWW 20 1 A WL, L YY, Y WW, W YA2 1 OEA 19 OEB © Semiconductor Components Industries, LLC, 2006 MARKING DIAGRAM 1 SOIC EIAJ--20 M SUFFIX CASE 967 YA1 YB1 http://onsemi.com 1 = Assembly Location = Wafer Lot = Year = Work Week PIN ASSIGNMENT OEA 1 20 VCC A1 2 19 OEB YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 ORDERING INFORMATION See detailed ordering and shipping information in the Ordering Information Table on page 2 of this data sheet. Publication Order Number: MC74VHC244/D MC74VHC244 FUNCTION TABLE INPUTS OUTPUTS OEA, OEB A, B YA, YB L L L L H H H X Z ORDERING INFORMATION Device Shipping† Package MC74VHC244DW -- OBSOLETE* SOIC--20 WB 38 Units/Rail MC74VHC244DWR2 SOIC--20 WB 1000/Tape & Reel MC74VHC244DT TSSOP--20 (Pb--Free) 75 Units/Rail MC74VHC244DTR2 TSSOP--20 (Pb--Free) 2500/Tape & Reel MC74VHC244M -- OBSOLETE* SOIC EIAJ--20 (Pb--Free) 1600 Units/Box MC74VHC244MEL SOIC EIAJ--20 (Pb--Free) 2000/Tape & Reel *This device is obsolete, information available for reference. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit VCC Positive DC Supply Voltage --0.5 to +7.0 V VIN Digital Input Voltage --0.5 to +7.0 V VOUT DC Output Voltage --0.5 to VCC +0.5 V IIK Input Diode Current --20 mA IOK Output Diode Current ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air 500 450 mW TSTG Storage Temperature Range VESD ESD Withstand Voltage ILATCHUP Latchup Performance θJA Thermal Resistance, Junction--to--Ambient SOIC TSSOP --65 to +150 °C Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) >2000 >200 >2000 V Above VCC and Below GND at 125°C (Note 5) ±300 mA 96 128 °C/W SOIC TSSOP Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Vin and Vout should be constrained to the range GND ≤ (Vin or Vout) ≤ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2. Tested to EIA/JESD22--A114--A 3. Tested to EIA/JESD22--A115--A 4. Tested to JESD22--C101--A 5. Tested to EIA/JESD78 http://onsemi.com 2 MC74VHC244 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit 2.0 5.5 V DC Input Voltage 0 5.5 V VOUT DC Output Voltage 0 VCC V TA Operating Temperature Range, all Package Types --55 125 °C tr, tf Input Rise or Fall Time 0 100 20 ns/V VCC DC Supply Voltage VIN VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80 ° C 117.8 TJ = 90 ° C 1,032,200 TJ = 100 ° C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110° C Time, Years TJ = 120° C Time, Hours TJ = 130 ° C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 2. Failure Rate vs. Time Junction Temperature DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH VIL VOH Parameter Condition Minimum High--Level Input Voltage Maximum Low--Level Input Voltage Maximum High--Level Output Voltage VIN = VIH or VIL IOH = --50 mA VIN = VIH or VIL IOH = --4 mA IOH = --8 mA VOL Maximum Low--Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 4 mA IOH = 8 mA (V) TA = 25°C Min Typ TA ≤ 85°C Max Min Max --55°C ≤ TA ≤ 125°C Min 2.0 1.5 1.5 1.5 1.5 3.0 to 5.5 VCCX 0.7 VCCX 0.7 VCCX 0.7 VCCX 0.7 Max V 2.0 0.5 0.5 0.5 3.0 to 5.5 VCCX 0.3 VCCX 0.3 VCCX 0.3 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 2.0 3.0 4.5 2.0 3.0 4.5 0.0 0.0 0.0 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.8 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA IOZ Maximum 3--State Leakage Current VIN = VIH or VIL 5.5 ±0.25 ±2.5 ±2.5 mA Maximum Quiescent Supply Current (per package) VIN = VCC or GND 5.5 4.0 40.0 40.0 mA ICC VOUT = VCC or GND http://onsemi.com 3 MC74VHC244 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25°C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Parameter Min Test Conditions --55°C ≤ TA ≤ 125°C TA ≤ 85°C Typ Max Min Max Min Max Unit ns Maximum Propagation Delay, A to YA or B to YB VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 5.8 8.3 8.4 11.9 1.0 1.0 10.0 13.5 1.0 1.0 11.0 14.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 3.9 5.4 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 7.5 9.5 Output Enable Time OEA to YA or OEB to YB VCC = 3.3 ± 0.3 V RL = 1 kΩ CL = 15 pF CL = 50 pF 6.6 9.1 10.6 14.1 1.0 1.0 12.5 16.0 1.0 1.0 13.5 17.0 VCC = 5.0 ± 0.5 V RL = 1 kΩ CL = 15 pF CL = 50 pF 4.7 6.2 7.3 9.3 1.0 1.0 8.5 10.5 1.0 1.0 9.5 11.5 Output Disable Time OEA to YA or OEB to YB VCC = 3.3 ± 0.3 V RL = 1 kΩ CL = 50 pF 10.3 14.0 1.0 16.0 1.0 17.0 VCC = 5.0 ± 0.5 V RL = 1 kΩ CL = 50 pF 6.7 9.2 1.0 10.5 1.0 11.5 Output to Output Skew VCC = 3.3 ± 0.3 V (Note 6) CL = 50 pF 1.5 1.5 1.5 VCC = 5.0 ± 0.5 V (Note 6) CL = 50 pF 1.0 1.0 1.5 10 10 10 Cin Maximum Input Capacitance 4 Cout Maximum Three--State Output Capacitance (Output in High--Impedance State) 6 ns ns ns pF pF Typical @ 25°C, VCC = 5.0V CPD 19 Power Dissipation Capacitance (Note 7) pF 6. Parameter guaranteed by design. tOSLH = |tPLHm -- tPLHn|, tOSHL = |tPHLm -- tPHLn|. 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC/8 (per bit). CPD is used to determine the no--load dynamic power consumption; PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Typ Parameter Symbol Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.6 0.9 V VOLV Quiet Output Minimum Dynamic VOL --0.6 --0.9 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 4 MC74VHC244 SWITCHING WAVEFORMS VCC A or B 50% tPLH YA or YB tPHL OEA or OEB VCC 50% GND tPZL tPZH YA or YB Figure 3. Switching Waveform HIGH IMPEDANCE 50% VCC YA or YB 50% VCC GND tPLZ VOL +0.3V tPHZ VOH --0.3V 50% VCC HIGH IMPEDANCE Figure 4. Switching Waveform TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* 1 kΩ CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit INPUT Figure 7. Input Equivalent Circuit http://onsemi.com 5 MC74VHC244 OUTLINE DIMENSIONS SOIC--20 WB DW SUFFIX CASE 751D--05 ISSUE G A 20 θ X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B DIM A A1 B C D E e H h L θ S L A 18X e SEATING PLANE A1 C T MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ TSSOP--20 DT SUFFIX CASE 948E--02 ISSUE B 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 11 J J1 B --U-- PIN 1 IDENT SECTION N--N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A --V-N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. F DETAIL E --W-- C D G H DETAIL E 0.100 (0.004) --T-- SEATING PLANE http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC244 OUTLINE DIMENSIONS SOIC EIAJ--20 M SUFFIX CASE 967--01 ISSUE O 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) http://onsemi.com 7 DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.81 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.032 MC74VHC244 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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