MOTOROLA MPC958 Low voltage pll clock driver Datasheet

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SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
MPC958
The MPC958 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree designs. With output frequencies
of up to 200MHz and output skews of 200ps the MPC958 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
LOW VOLTAGE
PLL CLOCK DRIVER
• Fully Integrated PLL
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• Output Frequency up to 200MHz
• Outputs Disable in High Impedance
• LQFP Packaging
• 100ps Cycle–to–Cycle Jitter
The MPC958 has a differential LVPECL reference input along with an
external feedback input. These features make the MPC958 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will tristate the output buffers when driven “high”.
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
The MPC958 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50Ω transmission lines. For series terminated
50Ω lines, each of the MPC958 outputs can drive two traces giving the
device an effective fanout of 1:22. The device is packaged in a 7x7mm
32–lead LQFP package to provide the optimum combination of board
density and performance.
QFB
(Int pull up)
PECL_CLK (Int pull down)
PECL_CLK
FB_CLK
(Int pull up)
0
0
Phase
Detector
LPF
VCO
200–400MHz
0
1
÷2
1
÷2
9
Q0:8
1
Q9
VCO_SEL
BYPASS
MR/OE
PLL_EN
(Int pull up)
(Int pull up)
(Int pull down)
(Int pull up)
Figure 1. Logic Diagram
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GNDO
Q5
VCCO
Q4
GNDO
Q3
VCCO
Q2
MPC958
FUNCTION TABLES
24
23
22
21
20
19
18
BYPASS
17
GNDO
25
16
Q6
Q1
26
15
VCCO
VCCO
27
14
Q7
Q0
28
13
GNDO
GNDO
29
12
Q8
QFB
30
11
VCCO
VCCO
31
10
Q9
VCO_SEL
32
9
1
0
MR/OE
1
0
Function
PLL Enabled
PLL Bypass
Function
Outputs Disabled
Outputs Enabled
4
5
FB_CLK
BYPASS
PLLEN
MR/OE
6
7
8
GNDI
3
PECL_CLK
2
PECL_CLK
1
VCCA
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MPC958
VCO_SEL
1
0
PLL_EN
GNDO
1
0
Function
÷2
÷1
Function
Select VCO
Select PECL_CLK
Figure 2. 32–Lead Pinout (Top View)
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VCC + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
125
°C
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application
note AN1545.
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DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
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Symbol
Characteristic
Min
Typ
2.0
Max
Unit
3.6
V
0.8
V
Condition
VIH
Input HIGH Voltage LVCMOS Inputs
VIL
Input LOW Voltage LVCMOS Inputs
VPP
Peak–to–Peak Input Voltage PECL_CLK
300
1000
mV
VCMR
Common Mode Range
1.0
3.0
V
Note 1.
VOH
Output HIGH Voltage
V
IOH = –20mA, Note 2.
VOL
Output LOW Voltage
0.5
V
IOL = 20mA, Note 2.
IIN
Input Current
±120
µA
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
ICC
Maximum Quiescent Supply Current
PECL_CLK
2.4
25
75
pF
Per Output
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
1. VCMR is the center of the differential input signal. Normal operation is obtained when the input crosspoint is within the VCMR range and the input
swing lies within the VPP specification.
2. The MPC958 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
fref
Characteristic
Reference Input Frequency
Min
Max
Unit
Note 3.
Note 3.
MHz
frefDC
Reference Input Duty Cycle
25
75
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Condition
%
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
tr, tf
Output Rise/Fall Time
tpw
Output Duty Cycle
tsk(O)
Output–to–Output Skews (Relative to QFB)
fVCO
PLL VCO Lock Range
fmax
Maximum Output Frequency
(Note 4.)
PLL Mode
Typ
Max
Unit
Condition
0.10
1.0
ns
0.8 to 2.0V
Note 4.
tcycle/2 –
400
tcycle/2 +
400
ps
Note 4.
Note 4.
200
ps
200
400
MHz
PLL Mode
PLL Mode
Bypass Mode
50
100
100
200
200
MHz
tpd(lock)
Input to Ext_FB Delay (with PLL Locked @ 100MHz)
–70
130
ps
Note 4.
tpd(bypass)
Input to Q Delay
3.0
7.0
ns
PLL Bypassed
tPLZ,HZ
Output Disable Time
7
ns
tPZL
Output Enable Time
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
tlock
Maximum PLL Lock Time
4. Termination of 50 to VCC/2.
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6
ns
100
ps
10
ms
VCO_SEL = ‘1’
VCO_SEL = ‘0’
Note 4.
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MPC958
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Power Supply Filtering
The MPC958 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC958 provides a separate
power supply for the phase–locked loop (VCCA) of the
device. The purpose of this design technique is to try and
isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase–locked loop. In a
controlled environment such as an evaluation board this level
of isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
VCCA pin for the MPC958.
Figure 3 illustrates a typical power supply filter scheme.
The MPC958 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC958. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
with an 8–10Ω resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Driving Transmission Lines
The MPC958 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 20Ω
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC958 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC958 clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC958
OUTPUT
BUFFER
IN
14Ω
MPC958
OUTPUT
BUFFER
RS = 36Ω
ZO = 50Ω
OutA
RS = 36Ω
ZO = 50Ω
OutB0
3.3V
IN
RS=5–15Ω
14Ω
RS = 36Ω
ZO = 50Ω
OutB1
VCCA
22µF
MPC958
0.01µF
Figure 4. Single versus Dual Transmission Lines
VCC
0.01µF
Figure 3. Power Supply Filter
Although the MPC958 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
MOTOROLA
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC958 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC958. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
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MPC958
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
MPC958
OUTPUT
BUFFER
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
3.0
2.5
VOLTAGE (V)
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Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
OutA
tD = 3.8956
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
OutB
tD = 3.9386
Figure 6. Optimized Dual Line Termination
2.0
In
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
1.5
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
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MPC958
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
D
SECTION AE–AE
H
W
K
X
DETAIL AD
Q_
0.250 (0.010)
C E
MOTOROLA
M
N
0.20 (0.008)
SEATING
PLANE
GAUGE PLANE
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P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
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INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
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MPC958
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