MC74LVXT4066 Quad Analog Switch/ Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS The MC74LVXT4066 utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF−channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full power−supply range (from VCC to GND). The LVXT4066 is identical in pinout to the metal−gate CMOS MC14066 and the high−speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal−gate CMOS analog switches. The ON/OFF control inputs are compatible with standard LSTTL outputs. The input protection circuitry on this device allows overvoltage tolerance on the ON/OFF control inputs, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the higher−voltage power supply. The MC74LVXT4066 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74LVXT4066 to be used to interface 5.0 V circuits to 3.0 V circuits. http://onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 14 1 LVXT4066 AWLYWW 1 14 14 1 TSSOP−14 DT SUFFIX CASE 948G LVXT 4066 ALYW 1 Features • • • • • • • • • Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 6.0 V Analog Input Voltage Range (VCC − GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 Low Noise Pb−Free Packages are Available* 14 SOEIAJ−14 M SUFFIX CASE 965 14 1 74LVXT4066 ALYW 1 A WL or L Y WW or W = = = = Assembly Location Wafer Lot Year Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 2 1 Publication Order Number: MC74LVXT4066/D MC74LVXT4066 LOGIC DIAGRAM XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL 1 2 PIN CONNECTION (Top View) YA 13 4 3 YB 5 8 9 ANALOG OUTPUTS/INPUTS YC 6 11 10 XA 1 14 YA 2 13 YB 3 12 XB B ON/OFF CONTROL C ON/OFF CONTROL GND 4 11 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD 5 10 YD 6 9 YC 7 8 XC YD 12 ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND FUNCTION TABLE On/Off Control Input State of Analog Switch L H Off On ORDERING INFORMATION Package Shipping† MC74LVXT4066DR2 SOIC−14 2500 Tape & Reel MC74LVXT4066DR2G SOIC−14 (Pb−Free) 2500 Tape & Reel MC74LVXT4066DTR2 TSSOP−14* 2500 Tape & Reel MC74LVXT4066M SOEIAJ−14 50 Units / Rail MC74LVXT4066MG SOEIAJ−14 (Pb−Free) 50 Units / Rail MC74LVXT4066MEL SOEIAJ−14 2000 Tape & Reel MC74LVXT4066MELG SOEIAJ−14 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74LVXT4066 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V −20 mA 500 450 mW – 65 to + 150 C 260 C VCC Positive DC Supply Voltage (Referenced to GND) VIS Vin I DC Current Into or Out of Any Pin PD Power Dissipation in Still Air, SOIC Package† TSSOP Package† Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating − SOIC Package: – 7 mW/C from 65 to 125C TSSOP Package: − 6.1 mW/C from 65 to 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V VCC Positive DC Supply Voltage (Referenced to GND) VIS Analog Input Voltage (Referenced to GND) GND VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V − 1.2 V – 55 + 85 C 0 0 100 20 ns/V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) VCC V Guaranteed Limit – 55 to 25C 85C 125C Unit VIH Minimum High−Level Voltage ON/OFF Control Inputs (Note 1) Ron = Per Spec 3.0 4.5 5.5 1.2 2.0 2.0 1.2 2.0 2.0 1.2 2.0 2.0 V VIL Maximum Low−Level Voltage ON/OFF Control Inputs (Note 1) Ron = Per Spec 3.0 4.5 5.5 0.53 0.8 0.8 0.53 0.8 0.8 0.53 0.8 0.8 V Iin Maximum Input Leakage Current ON/OFF Control Inputs Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V 5.5 4.0 40 160 A Symbol Parameter Test Conditions 1. Specifications are for design target only. Not final specification limits. http://onsemi.com 3 MC74LVXT4066 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Guaranteed Limit Symbol Ron VCC V – 55 to 25C 85C 125C Unit Vin = VIH VIS = VCC to GND IS 2.0 mA (Figures 1, 2) 2.0† 3.0 4.5 5.5 — 40 25 20 — 45 28 25 — 50 35 30 Vin = VIH VIS = VCC or GND (Endpoints) IS 2.0 mA (Figures 1, 2) 2.0 3.0 4.5 5.5 — 30 25 20 — 35 28 25 — 40 35 30 Parameter Test Conditions Maximum “ON” Resistance Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC − GND) IS 2.0 mA 3.0 4.5 5.5 15 10 10 20 12 12 25 15 15 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or GND Switch Off (Figure 3) 5.5 0.1 0.5 1.0 A Ion Maximum On−Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or GND (Figure 4) 5.5 0.1 0.5 1.0 A †At supply voltage (VCC) approaching 2 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage operation, it is recommended that these devices only be used to control digital signals. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V – 55 to 25C 85C 125C Unit tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) 2.0 3.0 4.5 5.5 4.0 3.0 1.0 1.0 6.0 5.0 2.0 2.0 8.0 6.0 2.0 2.0 ns tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 2.0 3.0 4.5 5.5 20 12 8.0 8.0 25 14 10 10 30 15 12 12 ns Maximum Capacitance ON/OFF Control Input — 10 10 10 pF Control Input = GND Analog I/O Feedthrough — — 35 1.0 35 1.0 35 1.0 C Typical @ 25°C, VCC = 5.0 V CPD 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . http://onsemi.com 4 pF MC74LVXT4066 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Symbol BW − − − THD Parameter Test Conditions VCC V Limit* 25C Unit Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 5) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 , CL = 10 pF 4.5 5.5 150 160 MHz Off−Channel Feedthrough Isolation (Figure 6) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF 4.5 5.5 − 50 − 50 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 5.5 − 37 − 37 Vin 1 MHz Square Wave (tr = tf = 3 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF 4.5 5.5 100 200 RL = 10 k, CL = 10 pF 4.5 5.5 50 100 fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF 4.5 5.5 – 70 – 70 fin = 1.0 MHz, RL = 50 , CL = 10 pF 4.5 5.5 – 80 – 80 Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured − THDSource VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave *Guaranteed limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 mVPP dB % 4.5 5.5 0.10 0.06 MC74LVXT4066 400 250 −55°C 300 Ron (Ohms) Ron (Ohms) 350 Is = 1mA 200 150 Is = 5mA 100 Is = 9mA 25°C 250 200 85°C 150 125°C 100 50 50 0 Is = 15mA 0 0.5 1 1.5 2 0 2.5 0 0.5 1.5 1 Vin (Volts) 2 2.5 Vin (Volts) Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C Figure 1b. Typical On Resistance, VCC = 2.0 V 35 25 30 20 20 Ron (Ohms) Ron (Ohms) 25 125°C 85°C 25°C −55°C 15 10 10 5 5 0 125°C 85°C 25°C −55°C 15 0 2 1 0 4 3 0 1 Vin (Volts) 4 Vin (Volts) Figure 1c. Typical On Resistance, VCC = 3.0 V Figure 1d. Typical On Resistance, VCC = 4.5 V 18 PLOTTER 16 125°C 85°C 25°C 14 Ron (Ohms) 3 2 12 10 −55°C 8 PROGRAMMABLE POWER SUPPLY − MINI COMPUTER + DC ANALYZER VCC DEVICE UNDER TEST 6 4 2 ANALOG IN COMMON OUT 0 0 1 2 3 4 5 6 GND Vin (Volts) Figure 2. On Resistance Test Set−Up Figure 1e. Typical On Resistance, VCC = 5.5 V http://onsemi.com 6 5 MC74LVXT4066 VCC VCC VCC VCC 14 GND 14 A A VCC OFF 7 SELECTED CONTROL INPUT VIL 7 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up VOS VCC VCC VIS VIH VOS 14 ON 0.1F CL* 7 SELECTED CONTROL INPUT Figure 4. Maximum On Channel Leakage Current, Test Set−Up 14 fin N/C ON GND SELECTED CONTROL INPUT fin dB METER OFF 0.1F CL* RL dB METER SELECTED CONTROL INPUT VCC 7 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On−Channel Bandwidth Test Set−Up VCC VCC/2 Figure 6. Off−Channel Feedthrough Isolation, Test Set−Up VCC/2 14 RL RL OFF/ON VOS IS VCC CL* VIH VIL Vin ≤ 1 MHz tr = tf = 3 ns 7 ANALOG IN SELECTED CONTROL INPUT 50% GND tPHL tPLH CONTROL ANALOG OUT 50% *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set−Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74LVXT4066 VCC tr 14 ANALOG IN ANALOG OUT ON TEST POINT VCC 90% 50% 10% CONTROL GND CL* 7 SELECTED CONTROL INPUT tf tPZL tPLZ HIGH IMPEDANCE 50% VIH ANALOG OUT tPZH 10% VOL 90% VOH tPHZ 50% HIGH IMPEDANCE *Includes all probe and jig capacitance. Figure 9. Propagation Delay Test Set−Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS 1 POSITIONWHEN TESTING tPHZ AND tPZH VCC 2 POSITIONWHEN TESTING tPLZ AND tPZL 1 2 VCC VCC 0.1 F TEST POINT ON/OFF OFF VIH OR VIL CL* RL RL VIH VIL VOS ON 1 k 1 2 RL fin 14 14 SELECTED CONTROL INPUT SELECTED CONTROL INPUT CL* VCC/2 RL CL* VCC/2 7 7 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set−Up Figure 12. Crosstalk Between Any Two Switches, Test Set−Up VCC A VIS VCC 14 N/C OFF/ON VOS 0.1 F N/C fin ON RL 7 VIH VIL CL* TO DISTORTION METER VCC/2 SELECTED CONTROL INPUT 7 SELECTED CONTROL INPUT VIH ON/OFF CONTROL *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set−Up Figure 14. Total Harmonic Distortion, Test Set−Up http://onsemi.com 8 MC74LVXT4066 0 −10 FUNDAMENTAL FREQUENCY −20 dBm −30 −40 −50 DEVICE −60 SOURCE −70 −80 −90 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at VIH or VIL logic levels, VIH being recognized as logic high and VIL being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked−up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is six volts. Therefore, using the configuration in Figure 16, a maximum analog signal of six volts peak−to−peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn−on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb is an acronym for high current surge protectors). Mosorbs are fast turn−on devices ideally suited for precise DC protection with no inherent wear out mechanism. VCC VCC = 6.0 V + 6.0 V 14 ANALOG I/O ON ANALOG O/I Dx + 6.0 V VIH SELECTED CONTROL INPUT 7 16 Dx ON 0V 0V VCC Dx VIH OTHER CONTROL INPUTS (VIH OR VIL) Dx SELECTED CONTROL INPUT 7 Figure 16. 6.0 V Application OTHER CONTROL INPUTS (VIH OR VIL) Figure 17. Transient Suppressor Application http://onsemi.com 9 MC74LVXT4066 +3 V +3V GND +5 V 14 ANALOG SIGNALS +3V ANALOG SIGNALS GND LVXT4066 6 14 15 CONTROL INPUTS ANALOG SIGNALS LVXT4066 LSTTL/ NMOS/ ABT/ ALS 5 1.8 − 2.5V CIRCUITRY 14 ANALOG SIGNALS 5 6 CONTROL INPUTS 14 15 7 7 R* = 2 TO 10 k a. Low Voltage Logic Level Shifting Control b. Using LVXT4066 Figure 18. Low Voltage CMOS Interface CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O − INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 F 1 2 3 4 CONTROL INPUTS Figure 19. 4−Input Multiplexer Figure 20. Sample/Hold Amplifier http://onsemi.com 10 MC74LVXT4066 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE G −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 7 1 G F R X 45 C −T− D 14 PL 0.25 (0.010) SEATING PLANE M T B A S DIM A B C D F G J K M P R J M K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 TSSOP−14 DT SUFFIX CASE 948G−01 ISSUE A 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E http://onsemi.com 11 DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0 8 0 8 MC74LVXT4066 PACKAGE DIMENSIONS SOEIAJ−14 M SUFFIX CASE 965−01 ISSUE O 14 LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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