MPS MP28115 4a, 1.5mhz synchronous step-down converter Datasheet

MP28115
4A, 1.5MHz Synchronous
Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP28115 is an internally compensated
1.5MHz fixed frequency PWM synchronous
step-down regulator. MP28115 operates from a
2.7V to 6V input and generates an adjustable
output voltage from 0.8V to 0.9xVIN at up to 4A
load current.
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•
•
•
•
•
•
•
•
•
•
•
•
•
The MP28115 integrates a 60mΩ high-side
switch and a 60mΩ synchronous rectifier for
high efficiency without an external Schottky
diode. With peak current mode control and
internal compensation, the MP28115 based
solution achieves minimum footprint and
component count. Fault condition protection
includes Hiccup short-circuit protection, cycleby-cycle current limiting and thermal shutdown.
Other
features
include
frequency
synchronization input, internal soft-start and
power good output.
4A Output Current
Input Operation Range: 2.7V to 6V
1.5% Output Accuracy
60mΩ Internal Power MOSFET Switches
All Ceramic Capacitor Design
Up to 95% Efficiency
1.5MHz Fixed Switching Frequency
Internal Soft-Start
Frequency Synchronization Input
Power Good Output
Cycle-by-Cycle Current Limiting
Hiccup Short Circuit Protection
Thermal Shutdown
3mm x 3mm 10-lead QFN Package
APPLICATIONS
•
•
•
•
The MP28115 is available in a small 3mm x
3mm 10-lead QFN package.
µP/ASIC/DSP/FPGA Core and I/O Supplies
Printers and LCD TVs
Network and Telecom Equipment
Point of Load Regulators
“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs
Output Current
C1
10uF
C2
10uF
6
R4
100k
R3
100k
4,7
C4
100nF
5
IN
BS
SW
POK
3,8
MP28115
10
EN/SYNC
FB
GND
2,9
1
D1
B0530
R2
316k
L1
1uH
R1
400k
Vout
1.8V/4A
C3
47uF
EFFICIENCY (%)
95
Vin
2.7V to 6V
90
5V to 1.8V
85
5V to 3.3V
5V to 2.5V
80
75
70
0
MP28115 Rev. 0.92
8/23/2010
1
2
3
OUTPUT CURRENT (A)
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1
MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
PACKAGE REFERENCE
TOP VIEW
FB
1
10
EN/SYNC
GND
2
9
GND
SW
3
8
SW
IN
4
7
IN
BS
5
6
POK
EXPOSED PAD
ON BACKSIDE
IN to GND ....................................-0.3V to +6.5V
SW to GND ........................... -0.3V to VIN + 0.3V
SW to GND ............ -2.5V to VIN+2.5V for <50nS
FB, EN/SYNC, POK to GND...........-0.3V to +6.5V
BS to SW .....................................-0.3V to +6.5V
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature ...............-65°C to +150°C
Recommended Operating Conditions (2)
Supply Voltage VIN ............................. 2.7V to 6V
Output Voltage VOUT ................. 0.8V to 0.9 x VIN
Operating Temperature ..............-40°C to +85°C
Thermal Resistance (3)
Part Number*
MP28115DQ
*
Package
QFN10
(3mm x 3mm)
Temperature
–40°C to +85°C
For Tape & Reel, add suffix –Z (e.g. MP28115DQ–Z)
For RoHS Compliant Packaging, add suffix –LF
(e.g. MP28115DQ–LF–Z)
θJA
θJC
QFN10 (3mm x 3mm) ............. 50 ...... 12... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS (4)
VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted.
Parameters
Supply Current
Shutdown Current
IN Undervoltage Lockout
Threshold
IN Undervoltage Lockout
Hysteresis
Regulated FB Voltage
Condition
VEN = VIN
VFB = 0.85V
VEN = 0V, VIN = 6V
Rising Edge
Typ
Max
TA = +25°C
–40°C ≤ TA ≤ +85°C
VFB = 0.85V
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
μA
1
μA
2.59
0.788
0.780
0.800
0.800
±50
2.69
0.812
0.820
0.4
120
60
60
–10
10
1.8
V
mV
1.6
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Units
750
210
FB Input Current
EN High Threshold
EN Low Threshold
Internal Soft-Start Time
High-Side Switch On-Resistance ISW = 300mA
Low-Side Switch On-Resistance ISW = –300mA
VEN = 0V; VIN = 6V
SW Leakage Current
VSW = 0V or 6V
BS Under Voltage Lockout
Threshold
MP28115 Rev. 0.92
8/23/2010
Min
V
V
nA
V
V
µs
mΩ
mΩ
μA
V
2
MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (4) (continued)
VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted.
Parameters
High-Side Switch Current Limit
Low-Side Switch Current Limit
Oscillator Frequency
Maximum Synch Frequency
Minimum Synch Frequency
Minimum On Time
Maximum Duty Cycle
POK Upper Trip Threshold
POK Lower Trip Threshold
POK Output Voltage Low
POK Deglitch Timer
Thermal Shutdown Threshold
Condition
Sourcing
Sinking
Min
TBD
1.2
FB respect to the nominal value
FB respect to the nominal value
ISINK = 5mA
Hysteresis = 20°C
Typ
6.5
3.5
1.5
2
1
50
90
10
-10
Max
1.8
0.4
30
150
Units
A
A
MHz
MHz
MHz
ns
%
%
%
V
μs
°C
Note:
4) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
PIN FUNCTIONS
Pin #
6
4, 7
3, 8
2, 9
5
1
10
Name
Description
Open Drain Power Good Output. “HIGH” output indicates VOUT is within ±10% window.
POK
“LOW” output indicates VOUT is out of ±10% window. POK is pulled down in shutdown.
Input Supply. A decoupling capacitor to ground is required close to these pins to reduce
IN
switching spikes.
Switch Node Connection to the Inductor. These pins connect to the internal high and lowSW
side power MOSFET switches. All SW pins must be connected together externally.
Ground. Connect these pins with larger copper areas to the negative terminals of the input
GND
and output capacitors.
Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side
BS
gate driver.
Feedback. This is the input to the error amplifier. An external resistive divider connects this
FB
pin between the output and GND. The voltage on the FB pin to the internal 0.8V reference
to set the regulation voltage.
Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down
EN/SYNC the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock
signal to this pin synchronizes the internal oscillator frequency to the external clock.
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VO = 1.8V, L1 = 10µH, C2 = 47µF, TA = +25°C, unless otherwise noted.
Steady State Operation
Steady State Operation
No Load
Half Load
VOUT
10mV/div.
VOUT
10mV/div.
I INDUCTOR
1A/div.
I INDUCTOR
1A/div.
VSW
5V/div.
VSW
5V/div.
400ns/div.
400ns/div.
Steady State Operation
Load Transient
Full Load
1A-4A Step Resistive Load
VOUT
10mV/div.
VOUT
200mV/div.
I INDUCTOR
1A/div.
VSW
5V/div.
I INDUCTOR
1A/div.
400ns/div.
VOUT
1V/div.
VPOK
2V/div.
VEN
2V/div.
MP28115 Rev. 0.92
8/23/2010
Start-up through Enable
Start-up through Enable
No Load
Full Load
VOUT
1V/div.
VPOK
2V/div.
VEN
2V/div.
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VO = 1.8V, L1 = 10µH, C2 = 47µF, TA = +25°C, unless otherwise noted.
Shut-down through Enable
Shut-down through Enable
No Load
Full Load
VOUT
2V/div.
VOUT
1V/div.
VEN
5V/div.
VEN
2V/div.
VPOK
2V/div.
VPOK
2V/div.
1ms/div.
400ms/div.
Short Circuit Protection
Short Circuit Recovery
VIN =5V, VOUT =1.8V
VIN =5V, VOUT =1.8V
VOUT
1V/div.
VOUT
1V/div.
Vsw
5V/div.
Vsw
5V/div.
I INDUCTOR
2A/div.
I INDUCTOR
2A/div.
1ms/div.
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
POK
0.88V
IN
+
--
EN
IN
+
--
0.72V
BS
EN
EXCLK
LOGIC
CLK
OSC
+
--
EN/SYNC
LOGIC
EN/SYNC
PWM
CURRENT
COMPARATOR
SW
SLOPE
SW
0.5pF
1.2 MEG 17pF
FB
0.8V
-+
+
COMP
SLOPE
COMPENSATION
AND PEAK
CURRENT LIMIT
SOFT
-START
GND
GND
Figure 1—Functional Block Diagram
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL DESCRIPTION
PWM Control
The MP28115 is a constant frequency peakcurrent-mode control PWM switching regulator.
Refer to the functional block diagram, The high
side N-Channel DMOS power switch is turns on
at the beginning of each clock cycle. The current
in the inductor increases until the PWM current
comparator trips to turn off the high side DMOS
switch. The peak inductor current at which the
current comparator shuts off the high side power
switch is controlled by the COMP voltage at the
output of feedback error amplifier. The
transconductance from the COMP voltage to the
output current is set at 11.25A/V.
This current-mode control greatly simplifies the
feedback compensation design by approximating
the switching converter as a single-pole system.
Only Type II compensation network is needed,
which is integrated into the MP28115. The loop
bandwidth is adjusted by changing the upper
resistor value of the resistor divider at the FB pin.
The internal compensation in the MP28115
simplifies the compensation design, minimizes
external component counts, and keeps the
flexibility of external compensation for optimal
stability and transient response.
Enable and Frequency Synchronization
(EN/SYNC PIN)
This is a dual function input pin. Forcing this pin
below 0.4V for longer than 4μs shuts down the
part; forcing this pin above 1.6V for longer than
4µs turns on the part. Applying a 1MHz to 2MHz
clock signal to this pin also synchronizes the
internal oscillator frequency to the external clock.
When the external clock is used, the part turns
on after detecting the first few clocks regardless
of duty cycles. If any ON or OFF period of the
clock is longer than 4µs, the signal will be
intercepted as an enable input and disables the
synchronization.
At this point the reference voltage takes over at
the non-inverting error amplifier input. The softstart time is internally set at 120µs. If the output
of the MP28115 is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal soft-start capacitor
exceeds the sensed output voltage at the FB pin.
Over current Protection
The MP28115 offers cycle-to-cycle current
limiting for both high-side and low-side switches.
The high-side current limit is relatively constant
regardless of duty cycles. When the output is
shorted to ground, causing the output voltage to
drop below 70% of its nominal output, the IC is
shut down momentarily and begins discharging
the soft start capacitor. It will restart with a full
soft-start when the soft- start capacitor is fully
discharged. This hiccup process is repeated until
the fault is removed.
Power Good Output (POK PIN)
The MP28115 includes an open-drain Power
Good output that indicates whether the regulator
output is within ±10% of its nominal output. When
the output voltage moves outside this range, the
POK output is pulled to ground. There is a 30µs
deglitch time when the POK output change its
state.
Bootstrap (BST PIN)
The gatedriver voltage for the high-side Nchannel DMOS power switch is supplied by a
bootstrap capacitor connected between the BS
and SW pins. When the low-side switch is on, the
capacitor is charged through an internal boost
diode. When the high-side switch is off and the
low-side switch turns on, the voltage on the
bootstrap capacitor is boosted above the input
voltage and the internal bootstrap diode prevents
the capacitor from discharging.
.
Soft-Start and Output Pre-Bias Startup
When the soft-start period starts, an internal
current source begins charging an internal softstart capacitor. During soft-start the voltage on
the soft-start capacitor is connected to the noninverting input of the error amplifier. The soft-start
period lasts until the voltage on the soft-start
capacitor exceeds the reference voltage of 0.8V.
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Output Voltage Setting
The external resistor divider sets the output
voltage (see Page 1). The feedback resistor R1
also sets the feedback loop bandwidth with the
internal compensation (refer to description
function). The relation between R1 and feedback
loop bandwidth (fC), output capacitance (CO) is as
following:
1.24 × 106
R1(KΩ) =
fC (KHz) × CO (uF)
The feedback loop bandwidth (fC) is no higher
than 1/10 of switching frequency of MP2119. In
the case of ceramic capacitor as CO, it’s usually
set to be in the range of 50 kHz and 150 kHz for
optimal transient performance and good phase
margin. If electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4 of the ESR zero
frequency (fESR). fESR is given by:
1
fESR =
2π × RESR × CO
For example, choose fC=70 kHz with ceramic
capacitor, CO=47uF, R1 is estimated to be 400kΩ.
R2 is then given by:
R1
R2 =
VOUT
-1
0.8V
Table 1—Resistor Selection vs. Output
Voltage Setting
VOUT
(V)
R1
(kΩ)
R2
(kΩ)
L
(μH)
COUT
(ceramic)
1.2
1.5
1.8
2.5
3.3
400
400
400
400
400
806
453
316
187
127
0.47μH-1μH
0.47μH-1μH
0.47μH-1μH
0.47μH-1μH
0.47μH-1μH
47μF
47μF
47μF
47μF
47μF
Inductor Selection
A 0.47µH to 1µH inductor with DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For best efficiency, the inductor DC resistance
shall be <10mΩ. See Table 2 for recommended
inductors and manufacturers. For most designs,
the inductance value can be derived from the
following equation:
L=
VOUTx(VIN - VOUT)
VINxΔILxfOSC
where ∆IL is Inductor Ripple Current. Choose
inductor ripple current approximately 30% of the
maximum load current, 4A.
The maximum inductor peak current is:
IL(MAX) = ILOAD +
ΔIL
2
Under light load conditions, larger inductance is
recommended for improved efficiency.
Input Capacitor Selection
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. The input capacitor impedance
at the switching frequency shall be less than
input source impedance to prevent high
frequency switching current passing to the input
source. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of
their low ESR and small temperature coefficients.
For most applications, a 47µF capacitor is
sufficient.
Table 2—Suggested Surface Mount Inductors
Part
Number
Inductan
ce
(μH)
Max DCR
(mΩ)
Current Rating
(A)
Dimensions
L x W x H (mm3)
744310055
744310095
0.55
0.95
4.5
7.4
14
11
7×6.9×3
7×6.9×3
B1015AS-1R0N
1
11
6.9
8.4×8.3×4
Manufacturer
Wurth Electronics
TOKO
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
Output Capacitor Selection
The output capacitor keeps output voltage ripple
small and ensures a stable regulation loop. The
output capacitor impedance shall be low at the
switching frequency. Ceramic capacitors with
X5R or X7R dielectrics are recommended. The
output ripple ∆VOUT is approximately:
ΔVOUT ≤
VOUTx(VIN - VOUT)
1
x(ESR +
)
VINxfOSCxL
8xfOSCxC3
PCB Layout Guide
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance. If change
is necessary, please follow these guidelines as
follows. Here, the typical application circuit is
taken as an example to illustrate the key layout
rules should be followed.
1) For MP28115, a PCB layout with more than
(or) four layers is recommended.
External Schottky Diode
For this part, an external schottky diode is
recommended to be placed close to "SW" and
"GND" pins, especially when the output current is
larger than 2A.
2) The high current paths (GND, IN and SW)
should be placed very close to the device with
short, direct and wide traces.
With the external schottky diode, the voltage
spike and negative kick on "SW" pin can be
minimized; moreover, the conversion efficiency
can also be improved a little.
(2 x (10μF~22μF)) are strongly recommended to
be placed on both sides of the MP28115
package and keep them as close as possible to
the “IN” and “GND” pins. If this placement is not
possible, a ceramic cap (10μF~47μF) must be
placed across PIN7-“IN”and PIN9-“GND” since
the internal Vcc supply is powered from PIN7,
and good decoupling is needed to avoid any
interference issues.
For the external schottky diode selection, it's
noteworthy that the maximum reverse voltage
rating of the external diode should be larger than
the maximum input voltage. As for the current
rating of this diode, 0.5A rating should be
sufficient.
3) For MP28115, two input ceramic capacitors
4) The external feedback resistors shall be
placed next to the FB pin. Keep the FB trace as
short as possible. Don’t place test points on FB
trace if possible.
5) Keep the switching node SW short and away
from the feedback network.
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
Top Layer
Inner Layer-1
Inner Layer-2
Bottom Layer
Figure2― Recommended PCB Layout of MP28115
TYPICAL APPLICTION CIRCUIT
Vin
2.7V to 6V
C1
10uF
C2
10uF
6
R4
100k
R3
100k
4,7
C4
100nF
5
IN
BS
SW
POK
3,8
MP28115
10
EN/SYNC
FB
GND
2,9
1
D1
B0530
L1
1uH
R1
400k
R2
316k
Vout
1.8V/4A
C3
47uF
Figure 3—Typical Application Circuit of MP28115
MP28115 Rev. 0.92
8/23/2010
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MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
3mm x 3mm QFN10
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.18
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
10
1
2.25
2.55
0.50
BSC
5
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28115 Rev. 0.92
8/23/2010
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© 2010 MPS. All Rights Reserved.
11