MC74LVX139 Dual 2-to-4 Decoder/ Demultiplexer The MC74LVX139 is an advanced high speed CMOS 2−to−4 decoder/demultiplexer fabricated with silicon gate CMOS technology. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com Features • • • • • • • • • • • • SOIC−16 D SUFFIX CASE 751B High Speed: tPD = 6.0 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mΑ (Max) at TA = 25°C TSSOP−16 DT SUFFIX CASE 948F PIN ASSIGNMENT High Noise Immunity: VNIH = VNIL = 28% VCC VCC Eb A0b A1b Y0b Y1b Y2b Y3b Power Down Protection Provided on Inputs 16 15 14 13 12 11 10 9 1 2 4 6 7 8 Balanced Propagation Delays Designed for 2 V to 3.6 V Operating Range Low Noise: VOLP = 0.5 V (Max) 3 5 Pin and Function Compatible with Other Standard Logic Families Ea A0a A1a Y0a Y1a Y2aY3a GND Latchup Performance Exceeds 300 mA Chip Complexity: 100 FETs or 25 Equivalent Gates MARKING DIAGRAMS ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V These Devices are Pb−Free and are RoHS Compliant 16 16 LVX 139 ALYWG G LVX139G AWLYWW 1 ADDRESS INPUTS A0a A1a 2 4 3 5 6 7 A0b A1b Y2a ACTIVE−LOW OUTPUTS Y3a 1 Ea ADDRESS INPUTS Y1a 1 SOIC−16 Y0a LVX139 A WL, L Y WW, W G or G TSSOP−16 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) 14 12 13 11 10 9 FUNCTION TABLE Y0b Y1b Y2b ACTIVE−LOW OUTPUTS Y3b 15 Eb Inputs Outputs E A1 A0 Y0 Y1 Y2 Y3 H L L L L X L L H H X L H L H H L H H H H H L H H H H H H L H H H L H Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 4 1 Publication Order Number: MC74LVX139/D MC74LVX139 En Y0 Y1 A0 Y2 Y3 A1 Figure 2. Expanded Logic Diagram (1/2 of Device) A1a 3 A0a Ea X/Y 1 0 2 2 1 1 EN 2 3 4 Y0a A1a 3 5 Y1a A0a 2 6 Y2a Ea 1 7 Y3a 0 1 DMUX 0 0 G 3 1 12 Y0b A1b 13 A0b 14 Eb 15 2 3 4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b A1b 13 10 Y2b A0b 14 10 Y2b Eb 15 9 Y3b 9 Y3b Figure 3. IEC Logic Diagram INPUT Figure 4. Input Equivalent Circuit http://onsemi.com 2 11 Y1b MC74LVX139 MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive DC Supply Voltage −0.5 to +7.0 V VIN Digital Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range −65 to +150 °C VESD ESD Withstand Voltage > 2000 > 200 > 2000 V Above VCC and Below GND at 125°C (Note 4) ±300 mA SOIC Package TSSOP 143 164 °C/W ILATCHUP qJA SOIC Package TSSOP Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Latchup Performance Thermal Resistance, Junction−to−Ambient Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage Output in 3−State High or Low State TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time VCC = 5.0 V ± 0.5 V Min Max Unit 2.0 3.6 V 0 5.5 V 0 VCC V −40 85 °C 0 100 ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 3 MC74LVX139 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition −40°C ≤ TA ≤ 85°C TA = 25°C (V) Min Typ Max Min Max Unit VIH Minimum High−Level Input Voltage 2.0 3.0 3.6 0.75 VCC 0.7 VCC 0.7 VCC − − − − − − 0.75 VCC 0.7 VCC 0.7 VCC − − − V VIL Maximum Low−Level Input Voltage 2.0 3.0 3.6 − − − − − − 0.25 VCC 0.3 VCC 0.3 VCC − − − 0.25 VCC 0.3 VCC 0.3 VCC V VOH High−Level Output Voltage IOH = −50 mA IOH = −50 mA IOH = −4 mA 2.0 3.0 3.0 1.9 2.9 2.58 2.0 3.0 3.0 − − − 1.9 2.9 2.48 − − − V VOL Low−Level Output Voltage IOL = 50 mA IOH = 50 mA IOH = 4 mA 2.0 3.0 3.0 − − − 0.0 0.1 0.1 0.36 − − − 0.1 0.1 0.44 V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 3.6 − − ±0.1 − ±1.0 mA ICC Maximum Quiescent Supply Current (per package) VIN = VCC or GND 3.6 1.0 1.0 2.0 − − mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns −40°C ≤ TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPLH, tPHL CIN Parameter Maximum Propagation Delay, A to Y Maximum Propagation Delay, E to Y Test Conditions Min Typ Max Min Max Unit ns VCC = 2.7 V CL = 15 pF CL = 50 pF − − 8.5 11.0 15.0 16.5 1.0 1.0 17.8 18.0 VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF − − 6.0 8.5 10.0 13.0 1.0 1.0 12.0 15.0 VCC = 2.7 V CL = 15 pF CL = 50 pF − − 8.0 10.0 13.0 16.5 1.0 1.0 15.5 18.0 VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF − − 5.5 7.5 8.2 13.0 1.0 1.0 10.0 15.0 − 4 10 − 10 Maximum Input Capacitance ns pF Typical @ 25°C, VCC = 3.3 V CPD 26 Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. VCC A VCC E 50% 50% GND tPHL tPLH Y GND tPHL 50% VCC Y Figure 5. Switching Waveform tPLH 50% VCC Figure 6. Switching Waveform http://onsemi.com 4 MC74LVX139 TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 7. Test Circuit ORDERING INFORMATION Package Shipping† MC74LVX139DR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74LVX139DTR2G TSSOP−16 (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7) Tape Size B1 Max 8 mm 4.35 mm (0.179”) 12 mm 8.2 mm (0.323”) 16 mm 24 mm D D1 E F K P P0 P2 R T W 1.5 mm + 0.1 −0.0 (0.059” +0.004 −0.0) 1.0 mm Min (0.179”) 1.75 mm ±0.1 (0.069 ±0.004”) 3.5 mm ±0.5 (1.38 ±0.002”) 2.4 mm Max (0.094”) 4.0 mm ±0.10 (0.157 ±0.004”) 4.0 mm ±0.1 (0.157 ±0.004”) 2.0 mm ±0.1 (0.079 ±0.004”) 25 mm (0.98”) 0.6 mm (0.024) 8.3 mm (0.327) 5.5 mm ±0.5 (0.217 ±0.002”) 6.4 mm Max (0.252”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.1 mm (0.476”) 7.5 mm ±0.10 (0.295 ±0.004”) 7.9 mm Max (0.311”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.0 mm ±0.10 (0.472 ±0.004”) 16.3 mm (0.642) 20.1 mm (0.791”) 11.5 mm ±0.10 (0.453 ±0.004”) 11.9 mm Max (0.468”) 16.0 mm ±0.10 (0.63 ±0.004”) 24.3 mm (0.957) 1.5 mm Min (0.060) 30 mm (1.18”) 12.0 mm ±0.3 (0.470 ±0.012”) 6. Metric Dimensions Govern−English are in parentheses for reference only. 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity http://onsemi.com 5 MC74LVX139 PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74LVX139 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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