FUJITSU MICROELECTRONICS DATA SHEET DS07-13751-2E 16-bit Microcontroller CMOS F2MC-16LX MB90820B Series MB90822B/823B/F822B/F823B/F828B/V820B ■ DESCRIPTION The MB90820B series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC family, the instruction set for the F2MC-16LX CPU core of the MB90820B series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90820B series has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90820B series include : an 8/10-bit A/D converter, 8-bit D/A converters, UARTs (SCI) 0, 1, multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 to 5, 16-bit PPG timer 0, waveform generator), 16-bit PPG timer 1, 2, PWC 0, 1, 16-bit reload timer 0, 1 and DTP/external interrupt. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Minimum execution time of instruction : 42 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum multiplier = 6 • Maximum memory space 16 M bytes, Linear/bank access • Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division instructions and enhanced RETI instructions (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.1 MB90820B Series (Continued) • Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions • Program patch function (for two address pointers) • Increased execution speed : 4-byte instruction queue • Powerful interrupt function Up to eight priority levels programmable External interrupt inputs : 8 channels • Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 channels • Internal ROM Flash memory : 64 K/128 K bytes with flash security MASK ROM : 64 K/128 K bytes • Internal RAM Evaluation product : 16 K bytes Flash memory : 4 K/8 K bytes MASK ROM : 4 K bytes • General-purpose ports Up to 66 channels (ports where pull-up resistor can be configured : 32 channels) • A/D Converter (RC) : 16 channels 8/10-bit resolution selectable Conversion time : Min 3 µs (24 MHz operation, including sampling time) • 8-bit D/A Converter : 2 channels • UART : 2 channels • 16-bit PPG timer : 3 channels Mode switching function provided (PWM mode or one-shot mode) ch.0 can be worked with multi-functional timer or independently • 16-bit reload timer : 2 channels • 16-bit PWC timer : 2 channels • Clock supervisor • Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-run timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit PPG timer : 1 channel Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) • Time-base timer/watchdog timer : 18-bit • Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode • Package : LQFP-80 (FPT-80P-M21 : 0.50 mm pitch) LQFP-80 (FPT-80P-M22 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) • CMOS technology 2 DS07-13751-2E MB90820B Series ■ PRODUCT LINEUP Part number Item Classification MB90V820B MB90F822B Evaluation product ROM size — RAM size 16 K bytes MB90F823B MB90F828B MB90822B Flash memory product with flash security 64 K bytes 128 K bytes 4 K bytes MASK ROM product 128 K bytes 64 K bytes 8 K bytes CPU function Number of instruction : 351 Minimum execution time : 42 ns / 4 MHz (PLL × 6) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space: 16 M bytes I/O port I/O port (CMOS) : 66 MB90823B 128 K bytes 4 K bytes Pulse width counter timer : 2 channels PWC Timer function (select the counter timer from three internal clocks) Various pulse width measuring function (“H” pulse width, “L” pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selected and used. Transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave communication). 16-bit reload timer Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable 16-bit PPG timer PPG timer : 3 channels PWM mode or single-shot mode selectable Ch.0 can be worked with multi-functional timer or independently. Multi-functional timer (for AC/DC motor control) 16-bit free-run timer with up or up-down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 8/10-bit A/D converter 8/10-bit resolution (16 channels) Conversion time : Min 3 µs (24 MHz internal clock, including sampling time) 8-bit D/A converter 8-bit resolution (2 channels) DTP/External interrupt 8 independent channels Interrupt trigger : Rising edge, falling edge, “L” level or “H” level Clock supervisor Low-power consumption No Yes No Stop mode / Sleep mode / CPU intermittent operation mode (Continued) DS07-13751-2E 3 MB90820B Series (Continued) Part number MB90V820B Item Package Power supply voltage for operation MB90F822B MB90822B MB90823B 3.5 V to 5.5 V : Normal operation when A/D converter and D/A converter are not used 4.0 V to 5.5 V : Normal operation when D/A converter is not used 4.5 V to 5.5 V : Normal operation when A/D converter and D/A converter are used Process Emulator power supply*2 MB90F828B LQFP-80 (FPT-80P-M21 : 0.50 mm pitch) LQFP-80 (FPT-80P-M22 : 0.65 mm pitch) QFP-80 (FPT-80P-M06 : 0.80 mm pitch) PGA-299 4.5 V to 5.5 V*1 MB90F823B CMOS ⎯ Included *1 : MB90V820B is operating guaranteed temperature 0 °C to + 25 °C. *2 : Configured by a jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB90V820B PGA-299 FPT-80P-M21 X FPT-80P-M22 X FPT-80P-M06 X MB90F822B MB90F823B MB90F828B MB90822B MB90823B X X X X X : Available X : Not available Note: For more information about each package, refer to “■ PACKAGE DIMENSIONS”. 4 DS07-13751-2E MB90820B Series ■ DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V820B does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V820B, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. (This setting can be changed by configuring the development tool.) • In the MB90822B/F822B/F828B, images from FF8000H to FFFFFFH are mapped to bank 00, and FF0000H to FF7FFFH are mapped to bank FF only. In the MB90823B/F823B/F828B, images from FF8000H to FFFFFFH are mapped to bank 00, and FE0000H to FF7FFFH are mapped to bank FE and bank FF only. Clock Supervisor Function The clock supervisor is built-in in MB90F828B only. Note that the evaluation products and products actually used are different when evaluating evaluation products. Please contact the sales representatives for more information on evaluation of this function. Modify ROM data The registers include this function between 001FF0H and 001FF5H which overlap the RAM area of MB90F828B. Do not access to the RAM when using this function in MB90F282B. DS07-13751-2E 5 MB90820B Series ■ PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 QFP-80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 C Vss Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22 Vcc P23 MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AVR AVcc AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss X0 X1 (FPT-80P-M06) * : High current pin. (Continued) 6 DS07-13751-2E MB90820B Series (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVcc AVR P70/DA0/AN8 P71/DA1/AN9 P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 P75/FRCK/AN13 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 P82/RTO0(U) * P83/RTO1(X) * P84/RTO2(V) * P85/RTO3(Y) * P86/RTO4(W) * P87/RTO5(Z) * C Vss (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LQFP-80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Vcc P00 * P01 * P02 * P03 * P04 * P05 * P06/PWI0 * P07/PWO0 * P10/INT0/DTTI P11/INT1 P12/INT2 P13/INT3 P14/INT4 P15/INT5 P16/INT6 P17 P20/TIN1 P21/TO1 P22 X0 X1 MD0 MD1 MD2 P40/PPG1 P37/PPG0 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 Vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AVss P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P51/INT7 P50/PPG2 P47/PWO1 P46/PWI1 P45/SIN0 P44/SOT0 P43/SCK0 RST P42/TO0 P41/TIN0 Vss (FPT-80P-M22) (FPT-80P-M21) * : High current pin. DS07-13751-2E 7 MB90820B Series ■ PIN DESCRIPTION Pin no. Pin name I/O circuit *3 LQFP *1 QFP *2 21, 22 23, 24 X0,X1 A 17 19 RST B 59 to 54 61 to 56 P00 to P05 C 53 55 52 54 P06 PWI0 P07 PWO0 Pin status during reset Oscillating Oscillation pins. Reset input General-purpose I/O port. C PWC ch.0 signal input pin. General-purpose I/O port. C PWC ch.0 signal output pin. General-purpose I/O port. INT0 53 External interrupt request input ch.0 pin. D RTO0 to RTO5 pins for fixed-level input. This function is enabled when the waveform generator specifies its input bits. DTTI P11 to P16 External reset input pin. General-purpose I/O ports. P10 51 Function General-purpose I/O ports. 50 to 45 52 to 47 44 46 43 45 42 44 41, 39 to 35 43, 41 to 37 P22 to P27 D General-purpose I/O ports. 34 to 28 36 to 30 P30 to P36 E General-purpose I/O ports. 27 29 26 28 19 21 18 20 INT1 to INT6 P17 P20 TIN1 P21 TO1 P37 PPG0 P40 PPG1 P41 TIN0 P42 TO0 D External interrupt request input ch.1 to ch.6 pins. D D D E F F F General-purpose I/O port. General-purpose I/O port. Port input External clock input pin for reload timer ch.1. General-purpose I/O port. Event output pin for reload timer ch.1. General-purpose I/O port. Output pin for PPG timer ch.0. General-purpose I/O port. Output pin for PPG timer ch.1. General-purpose I/O port. External clock input pin for reload timer ch.0. General-purpose I/O port. Event output pin for reload timer ch.0. (Continued) 8 DS07-13751-2E MB90820B Series Pin no. LQFP *1 QFP *2 16 18 15 17 14 16 13 15 12 14 11 13 10 12 9 to 2 11 to 4 Pin name P43 SCK0 P44 SOT0 P45 SIN0 P46 PWI1 P47 PWO1 P50 PPG2 P51 INT7 P60 to P67 AN0 to AN7 I/O circuit *3 Pin status during reset General-purpose I/O port. F Serial clock I/O pin for UART ch.0. General-purpose I/O port. F Serial data output pin for UART ch.0. General-purpose I/O port. G F Serial data input pin for UART ch.0. Port Input 80, 79 DA0, DA1 General-purpose I/O port. F Output pin for PPG timer ch.2. General-purpose I/O port. F External interrupt request input ch.7 pin. General-purpose I/O ports. H A/D converter analog input pins. General-purpose I/O ports. I D/A converter analog output pins. A/D converter analog input pins. P72 78 SIN1 General-purpose I/O port. J Serial data input pin for UART ch.1. AN10 A/D converter analog input pin. Analog input P73 75 77 SOT1 K AN11 76 SCK1 K FRCK AN13 Serial clock I/O pin for UART ch.1. A/D converter analog input pin. P75 75 Serial data output pin for UART ch.1. General-purpose I/O port. AN12 73 General-purpose I/O port. A/D converter analog input pin. P74 74 PWC ch.1 signal input pin. PWC ch.1 signal output pin. AN8, AN9 76 General-purpose I/O port. General-purpose I/O port. F P70, P71 78, 77 Function General-purpose I/O port. K External clock input pin for free-run timer. A/D converter analog input pin. (Continued) DS07-13751-2E 9 MB90820B Series (Continued) Pin no. LQFP *1 QFP *2 Pin name I/O circuit *3 Pin status during reset K Analog input P76, P77 72, 71 74, 73 IN0, IN1 General-purpose I/O ports. AN14, AN15 70, 69 72, 71 P80, P81 IN2, IN3 Function Trigger input pins for input capture ch.0, ch.1. A/D converter analog input pins. F P82 to P87 General-purpose I/O ports. Trigger input pins for input capture ch.2, ch.3. Port input General-purpose I/O ports. 68 to 63 70 to 65 RTO0 (U) to RTO5 (Z) L 25 27 MD2 M 24, 23 26, 25 MD1, MD0 N 80 2 AVCC ⎯ Analog power supply pin. 79 1 AVR ⎯ Vref + pin for the A/D converter. Vref - is fixed to AVss internally. 1 3 AVSS ⎯ 20, 61 22, 63 Vss ⎯ 40, 60 42, 62 Vcc ⎯ Power pins. 62 64 C ⎯ Connect pin for smoothing capacitor to stabilize internal power supply. Waveform generator output pins. (U) to (Z) represent the coils for controlling a 3-phase motor. Mode input ⎯ Input pin for operation mode specification. Input pins for operation mode specification. Analog power supply (Ground) pin. Power (Ground) pins. *1 : FPT-80P-M21, FPT-80P-M22 *2 : FPT-80P-M06 *3 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types. 10 DS07-13751-2E MB90820B Series ■ I/O CIRCUIT TYPE Classification A Type Remarks Oscillation feedback resistor : approx. 1 MΩ X1 P-ch Clock input N-ch X0 Standby control signal B • Hysteresis input • Pull-up resistor : approx. 50 kΩ R C R P-ch Pull-up control P-ch Digital output • CMOS output • Hysteresis input • Selectable pull-up resistor : approx. 50 kΩ • IOL = 12 mA Digital output N-ch Hysteresis input Standby mode control D R P-ch Pull-up control P-ch Digital output • CMOS output • Hysteresis input • Selectable pull-up resistor : approx. 50 kΩ • IOL = 4 mA Digital output N-ch Hysteresis input Standby mode control E R P-ch Pull-up control P-ch N-ch Digital output • • • • CMOS output CMOS input With pull-up control IOL = 4 mA Digital output CMOS input Standby mode control (Continued) DS07-13751-2E 11 MB90820B Series Classification Type Remarks F P-ch N-ch Digital output • CMOS output • Hysteresis input • IOL = 4 mA Digital output Hysteresis input Standby mode control G P-ch N-ch Digital output Digital output • CMOS output • Hysteresis input • CMOS input (selectable for UART ch.0 data input pin) • IOL = 4 mA Hysteresis input CMOS input Standby mode control H P-ch N-ch Digital output Digital output • • • • CMOS output CMOS input Analog input IOL = 4 mA • • • • • CMOS output Hysteresis input Analog output Analog input IOL = 4 mA CMOS input Analog input control Analog input I P-ch N-ch Digital output Digital output Hysteresis input Analog I/O control Analog output Analog input (Continued) 12 DS07-13751-2E MB90820B Series (Continued) Classification Type Remarks J P-ch N-ch Digital output Digital output • CMOS output • Hysteresis input • CMOS input (selectable for UART ch.1 data input pin) • IOL = 4 mA Hysteresis input CMOS input Analog input control Analog input K P-ch N-ch Digital output Digital output • • • • CMOS output Hysteresis input Analog input IOL = 4 mA Hysteresis input Analog input control Analog input L P-ch N-ch Digital output • CMOS output • Hysteresis input • IOL = 12 mA Digital output Hysteresis input Standby mode control M R N DS07-13751-2E MASK ROM / evaluation product • Hysteresis input • Pull-down resistor : approx. 50 kΩ Flash memory product • CMOS input • No pull-down resistor MASK ROM / evaluation product • Hysteresis input Flash memory product • CMOS input 13 MB90820B Series ■ HANDLING DEVICES Special care is required for the following when handling the device : • Preventing latch-up • Stabilization of supply voltage • Treatment of unused pins • Using external clock • Power supply pins (VCC /VSS ) • Pull-up/pull-down resistors • Crystal Oscillator Circuit • Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs • Connection of Unused Pins of A/D Converter • Notes on turning the power on • Notes on During Operation of PLL Clock Mode 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. In using the devices, take sufficient care to avoid exceeding maximum ratings. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage. 2. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operation range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 3. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 4. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90820B series X0 Open 14 X1 DS07-13751-2E MB90820B Series 5. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS pins to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS pins in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VSS VCC MB90820B Series VCC VSS VSS VCC 6. Pull-up/pull-down resistors The MB90820B series does not support internal pull-up/pull-down resistors option (Port 0 to Port 3 : built-in pullup resistors) . Use external components where needed. 7. Crystal oscillator circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you design a printed circuit board. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. 8. Turning-on sequence of power supply to A/D converter and D/A converter, and analog inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter power supply, D/A converter power supply, and analog inputs. In this case, make sure that the voltage not exceed AVR or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 9. Pin connections when A/D converter and D/A converter are unused When the A/D converter and D/A converter are not used, connect AVCC = VCC, AVSS = AVRH = AVRL = VSS. DS07-13751-2E 15 MB90820B Series 10. Notes on turning the power on To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power on at 50 µs or more (0.2 V to 2.7 V) . 11. Notes on During Operation of PLL Clock Mode If the PLL clock mode is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit within the PLL even if the external oscillator is disconnected or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 12. Internal CR Oscillation Circuit Parameter Oscillation frequency Oscillation stabilization waiting time 16 Symbol Rating Unit Min Typ Max fRC 50 100 200 kHz tstab ⎯ ⎯ 100 µs DS07-13751-2E MB90820B Series ■ SECTOR CONFIGURATION OF FLASH MEMORY The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When 512K bits flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank. Flash memory SA3 (16K bytes) SA2 (8K bytes) SA1 (8K bytes) SA0 (32K bytes) CPU address *Writer address FFFFFFH 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H 7A000H FF9FFFH 79FFFH FF8000H FF7FFFH 78000H 77FFFH FF0000H 70000H When 1024K bits flash memory is accessed from the CPU, SA0 to SA4 are allocated in the FE and FF bank. Flash memory SA4 (16K bytes) SA3 (8K bytes) SA2 (8K bytes) SA1 (32K bytes) CPU address FFFFFFH 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H 7A000H FF9FFFH 79FFFH FF8000H 78000H 77FFFH FF7FFFH FF0000H SA0 (64K bytes) *Writer address FEFFFFH 70000H 6FFFFH FE0000H 60000H * : The writer address is the address corresponding to the CPU address when writing data from a parallel flash memory writer. Use the writer address when programming or erasing using a general-purpose parallel writer. DS07-13751-2E 17 MB90820B Series ■ BLOCK DIAGRAM CR oscillation circuit *1 X0 Clock control circuit, monitor circuit *1 X1 CPU 2 F MC-16LX core Time-base timer Reset circuit (Watchdog timer) RST Other pins VSS × 2, VCC × 2, MD0 to MD2, C Delayed interrupt generator Interrupt controller 7 P30 to P36 Multi-functional timer 8 P51/INT7 6 P45/SIN0 P44/SOT0 P43/SCK0 16-bit input capture (ch.0 to ch.3) UART (ch.0) P72/SIN1/AN10 P73/SOT1/AN11 P74/SCK1/AN12 16-bit PPG (ch.1) P50/PPG2 16-bit PPG (ch.2) PWC (ch.1) P46/PWI1 P47/PWO1 4 4 16-bit free-run timer UART (ch.1) P40/PPG1 P37/PPG0 16-bit PPG timer (ch.0) F2MC-16LX bus P16/INT6 to P11/INT1 DTP/External interrupt P75/FRCK/AN13 P82/RTO0 (U) *2 P83/RTO1 (X) *2 P84/RTO2 (V) *2 P85/RTO3 (Y) *2 P86/RTO4 (W) *2 P87/RTO5 (Z) *2 16-bit output compare (ch.0 to ch.5) Waveform generator P10/INT0/DTTI P17 P06/PWI0 *2 P07/PWO0 *2 PWC (ch.0) 6 16-bit reload timer (ch.0) P42/TO0 P41/TIN0 16-bit reload timer (ch.1) P21/TO1 P20/TIN1 P22 to P27 6 P76/IN0/AN14 P77/IN1/AN15 P80/IN2 P81/IN3 CMOS I/O port 0, 1, 3, 7, 8 P00 to P05 *2 CMOS I/O port 6 A/D converter (8/10-bit) CMOS I/O port 1, 2, 4, 5, 7 RAM 16 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVR AVCC AVSS ROM 8-bit D/A converter P70/DA0/AN8 P71/DA1/AN9 ROM correction ROM mirroring CMOS I/O port 7 Note : P00 to P07, P10 to P17, P20 to P27 and P30 to P37: With build-in resistors that can be used as input pull-up resistors. *1 : MB90F828B *2 : High current drive pin. 18 DS07-13751-2E MB90820B Series ■ MEMORY MAP FFFFFFH Address #1 ROM area Address #1 - 1H 010000H 00FFFFH Address #2 ROM area* (FF bank image) : Internal access memory Address #2 - 1H : Access not allowed Address #3 + 1H Address #3 000100H 0000FFH 0000F0H 0000EFH 000000H RAM Register area Peripheral area * : In Single chip mode, the mirror function is supported. Parts no. Address#1 Address#2 Address#3 MB90822B FF0000H 008000H 0010FFH MB90823B FE0000H 008000H 0010FFH MB90F822B FF0000H 008000H 0010FFH MB90F823B FE0000H 008000H 0010FFH MB90F828B FE0000H 008000H 0020FFH MB90V820B (FE0000H) 008000H 0040FFH Note: The ROM data of bank FF is reflected to the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 32 K bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF8000H to FFFFFFH looks, therefore, as if it were the image for 008000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF8000H to FFFFFFH. DS07-13751-2E 19 MB90820B Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH : Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a sequence of 32-bit register. AL : User stack pointer (USP) The 16-bit pointer indicating the user stack address. USP : System stack pointer (SSP) The 16-bit pointer indicating the system stack address. SSP : Processor status (PS) The 16-bit register indicating the system status. PS PC DPR : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in executing of the short direct addressing. PCB : Program bank register (PCB) The 8-bit register indicating the program space. DTB : Data bank register (DTB) The 8-bit register indicating the data space. USB : User stack bank register (USB) The 8-bit register indicating the user stack space. SSB : System stack bank register (SSB) The 8-bit register indicating the system stack space. ADB : Additional data bank register (ADB) The 8-bit register indicating the additional space. 8-bit 16-bit 32-bit 20 DS07-13751-2E MB90820B Series • General-purpose registers Maximum of 32 banks R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 RL3 RL2 RW3 RL1 RW2 RW1 RL0 RW0 000180H + (RP × 10H) 16-bit • Processor status (PS) ILM RP CCR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS Initial value X ILM2 ILM1 ILM0 0 0 0 B4 B3 B2 B1 B0 I S T N Z V C 0 0 0 0 0 0 1 X X X X X : Unused : Undefined DS07-13751-2E 21 MB90820B Series ■ I/O MAP Byte access Word access Resource name Initial value Port 0 data register R/W R/W Port 0 XXXXXXXXB PDR1 Port 1 data register R/W R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 data register R/W R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W R/W Port 6 XXXXXXXXB 000007H PDR7 Port 7 data register R/W R/W Port 7 XXXXXXXXB 000008H PDR8 Port 8 data register R/W R/W Port 8 XXXXXXXXB Address Abbreviation 000000H PDR0 000001H Register 000009H to 00000FH Prohibited area 000010H DDR0 Port 0 data direction register R/W R/W Port 0 00000000B 000011H DDR1 Port 1 data direction register R/W R/W Port 1 00000000B 000012H DDR2 Port 2 data direction register R/W R/W Port 2 00000000B 000013H DDR3 Port 3 data direction register R/W R/W Port 3 00000000B 000014H DDR4 Port 4 data direction register R/W R/W Port 4 00000000B 000015H DDR5 Port 5 data direction register R/W R/W Port 5 XXXXXX00 B 000016H DDR6 Port 6 data direction register R/W R/W Port 6 00000000B 000017H DDR7 Port 7 data direction register R/W R/W Port 7 00000000B 000018H DDR8 Port 8 data direction register R/W R/W Port 8 00000000B 000019H to 00001FH Prohibited area 000020H SMR0 Serial mode register ch.0 000021H SCR0 Serial control register ch.0 000022H SIDR0 / SODR0 000023H SSR0 Serial status register ch.0 000024H SMR1 Serial mode register ch.1 000025H SCR1 Serial control register ch.1 000026H SIDR1 / SODR1 000027H SSR1 Serial input data register ch.0 / Serial output data register ch.0 Serial input data register ch.1 / Serial output data register ch.1 Serial status register ch.1 R/W R/W 00000000B W, R/W W, R/W R/W R/W 00000100B UART ch.0 R, R/W R, R/W R/W 00001000B R/W 00000000B W, R/W W, R/W R/W R/W R, R/W R, R/W XXXXXXXXB 00000100B UART ch.1 XXXXXXXXB 00001000B (Continued) 22 DS07-13751-2E MB90820B Series Address Abbreviation 000028H PWCSL1 000029H PWCSH1 00002AH 00002BH 00002CH PWC1 DIV1 Register PWC control status register ch.1 PWC data buffer register ch.1 Divide ratio control register ch.1 00002DH, 00002EH Byte access Word access R/W R/W Resource name 00000000B R, R/W R, R/W ⎯ R/W R/W R/W Initial value 00000000B PWC timer ch.1 XXXXXXXXB XXXXXXXXB XXXXXX00B Prohibited area 00002FH PCKCR 000030H ENIR 000031H W W DTP / Interrupt enable register R/W R/W 00000000B EIRR DTP / Interrupt cause register R/W R/W 000032H ELVRL Request level setting register (lower byte) R/W R/W XXXXXXXXB DTP/ external interrupt 0 0 0 0 0 0 0 0 B ch.0 to ch.7 000033H ELVRH Request level setting register (higher byte) R/W R/W 000034H 000035H 000038H 000039H 00003AH 00003BH 00003CH 00003DH CDCR0 000044H 000045H R/W Communication prescaler ch.0 00XXX000 B R/W R/W Communication prescaler ch.1 00XXX000 B R/W PDCR0 PPG down counter register ch.0 ⎯ R PCSR0 PPG cycle setting register ch.0 ⎯ W PDUT0 PPG duty setting register ch.0 ⎯ W R/W R/W XX000000 B R/W R/W 00000000B PCNTH0 000043H Clock division ratio control register ch.0 Clock division ratio control register ch.1 00003FH 000042H 00000000B CDCR1 PCNTL0 000041H XXXX0000 B Prohibited area 00003EH 000040H PLL Prohibited area 000036H 000037H PLL clock control register PPG control status register ch.0 11111111B 11111111B XXXXXXXXB 16-bit PPG timer XXXXXXXXB ch.0 XXXXXXXXB XXXXXXXXB 11111111B PDCR1 PPG down counter register ch.1 ⎯ R PCSR1 PPG cycle setting register ch.1 ⎯ W PDUT1 PPG duty setting register ch.1 ⎯ W R/W R/W XX000000 B R/W R/W 00000000B 000046H PCNTL1 000047H PCNTH1 PPG control status register ch.1 11111111B XXXXXXXXB 16-bit PPG timer XXXXXXXXB ch.1 XXXXXXXXB XXXXXXXXB (Continued) DS07-13751-2E 23 MB90820B Series Address 000048H 000049H 00004AH 00004BH 00004CH Abbreviation Register Byte Word access access ⎯ R PCSR2 PPG cycle setting register ch.2 ⎯ W ⎯ W R/W R/W XX000000B R/W R/W 00000000B PCNTL2 00004FH PCNTH2 PPG control status register ch.2 TMRR0 16-bit timer register ch.0 ⎯ R/W TMRR1 16-bit timer register ch.1 ⎯ R/W TMRR2 16-bit timer register ch.2 ⎯ R/W 000052H 000053H 000054H 000055H 11111111B XXXXXXXXB 16-bit PPG timer ch.2 00004EH 000051H 11111111B PPG down counter register ch.2 PPG duty setting register ch.2 000050H Initial value PDCR2 PDUT2 00004DH Resource name XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Waveform generator 000056H DTCR0 16-bit timer control register ch.0 R/W R/W 00000000B 000057H DTCR1 16-bit timer control register ch.1 R/W R/W 00000000B 000058H DTCR2 16-bit timer control register ch.2 R/W R/W 00000000B 000059H SIGCR Waveform control register R/W R/W 00000000B 00005AH CPCLRB / CPCLR Compare clear buffer register/ Compare clear register ⎯ R/W Timer data register ⎯ R/W 00005BH 00005CH 00005DH TCDT 11111111B 11111111B 00000000B 16-bit free-run timer 0 0 0 0 0 0 0 0 B 00005EH TCCSL Timer control status register (lower) R/W R/W X0100000B 00005FH TCCSH Timer control status register (upper) R/W R/W 00000000B IPCP0 Input capture data register ch.0 ⎯ R IPCP1 Input capture data register ch.1 ⎯ R 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit input capture (ch.0 to ch.3) IPCP2 Input capture data register ch.2 ⎯ R IPCP3 Input capture data register ch.3 ⎯ R XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 24 DS07-13751-2E MB90820B Series Byte Word access access Register Abbreviation 000068H PICSL01 Input capture control status register ch.0,ch.1 (lower) 000069H PICSH01 PPG output control / Input capture control status register ch.0,ch.1 (upper) 00006AH ICSL23 Input capture control status register ch.2,ch.3 (lower) R/W R/W 00000000B 00006BH ICSH23 Input capture control status register ch.2,ch.3 (upper) R R XXXXXX00 B 00006CH to 00006EH R/W Resource name Initial value Address R/W R, R/W R, R/W 00000000B 16-bit input capture (ch.0 to ch.3) 00000000B Prohibited area ROM mirroring function selection register W W OCCPB0 / OCCP0 Output compare buffer register / Output compare register ch.0 ⎯ R/W OCCPB1 / OCCP1 Output compare buffer register / Output compare register ch.1 ⎯ R/W OCCPB2 / OCCP2 Output compare buffer register / Output compare register ch.2 ⎯ R/W OCCPB3 / OCCP3 Output compare buffer register / Output compare register ch.3 ⎯ R/W OCCPB4 / OCCP4 Output compare buffer register / Output compare register ch.4 ⎯ R/W 00007BH OCCPB5 / OCCP5 Output compare buffer register / Output compare register ch.5 ⎯ R/W 00007CH OCS0 Compare control register ch.0 R/W R/W 00001100B 00007DH OCS1 Compare control register ch.1 R/W R/W X1 1 0 0 0 0 0 B 00007EH OCS2 Compare control register ch.2 R/W R/W 00001100B 00007FH OCS3 Compare control register ch.3 R/W R/W X1 1 0 0 0 0 0 B 000080H OCS4 Compare control register ch.4 R/W R/W 00001100B 000081H OCS5 Compare control register ch.5 R/W R/W X1 1 0 0 0 0 0 B 000082H TMCSRL0 Timer control status register ch.0 (lower) R/W R/W 00000000B 000083H TMCSRH0 Timer control status register ch.0 (upper) R/W R/W 000084H 000085H TMR0 / TMRD0 ⎯ R/W 000086H TMCSRL1 R/W R/W 00006FH ROMM 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 16 bit timer register ch.0 / 16-bit reload register ch.0 Timer control status register ch.1 (lower) ROM mirroring function XXXXXXX1 B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output compare (ch.0 to ch.5) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit reload timer (ch.0) XXX1 0000 B XXXXXXXXB XXXXXXXXB 16-bit reload timer (ch.1) 00000000B (Continued) DS07-13751-2E 25 MB90820B Series Address Abbreviation 000087H TMCSRH1 000088H 000089H TMR1 / TMRD1 16 bit timer register ch.1 / 16-bit reload register ch.1 00008AH CSVCR Clock supervisor control register* Register Timer control status register ch.1 (upper) 00008BH Byte access Word access R/W R/W ⎯ R/W R, R/W ⎯ Clock supervisor 00011100B Resource name Initial value XXX1 0000 B 16-bit reload timer (ch.1) XXXXXXXXB XXXXXXXXB Prohibited area 00008CH RDR0 Port 0 pull-up resistor setting register R/W R/W Port 0 00000000B 00008DH RDR1 Port 1 pull-up resistor setting register R/W R/W Port 1 00000000B 00008EH RDR2 Port 2 pull-up resistor setting register R/W R/W Port 2 00000000B 00008FH RDR3 Port 3 pull-up resistor setting register R/W R/W Port 3 00000000B Address match detection XXXX0 0 0 0 B 000090H to 00009DH Prohibited area Program address detection control status register R/W R/W Delayed interrupt cause / clear register R/W R/W 00009EH PACSR 00009FH DIRR 0000A0H LPMCR Low-power consumption mode control register W, R/W W, R/W 0000A1H CKSCR Clock selection register R, R/W R, R/W 0000A2H to 0000A7H WDTC Watchdog timer control register 0000A9H TBTC Time-base timer control register W, R/W W, R/W 0000AAH to 0000ADH 0000AFH Low-power consumption control register 00011000B Watchdog timer XXXXX11 1 B Time-base timer 1 XX0 0 1 0 0 B Flash memory interface circuit 0 0 0 X0 0 0 0 B 11111100B Prohibited area 0000A8H 0000AEH Delayed interrupt XXXXXXX0 B R, W R, W Prohibited area FMCS Flash memory control status register R, R/W R, R/W Prohibited area (Continued) 26 DS07-13751-2E MB90820B Series Byte access Word access Interrupt control register 00 R/W R/W 00000111B ICR01 Interrupt control register 01 R/W R/W 00000111B 0000B2H ICR02 Interrupt control register 02 R/W R/W 0000B3H ICR03 Interrupt control register 03 R/W R/W 0000B4H ICR04 Interrupt control register 04 R/W R/W 00000111B 0000B5H ICR05 Interrupt control register 05 R/W R/W 00000111B 0000B6H ICR06 Interrupt control register 06 R/W R/W 00000111B 0000B7H ICR07 Interrupt control register 07 R/W R/W 00000111B 0000B8H ICR08 Interrupt control register 08 R/W R/W 00000111B 0000B9H ICR09 Interrupt control register 09 R/W R/W 00000111B 0000BAH ICR10 Interrupt control register 10 R/W R/W 0000BBH ICR11 Interrupt control register 11 R/W R/W 0000BCH ICR12 Interrupt control register 12 R/W R/W 00000111B 0000BDH ICR13 Interrupt control register 13 R/W R/W 00000111B 0000BEH ICR14 Interrupt control register 14 R/W R/W 00000111B 0000BFH ICR15 Interrupt control register 15 R/W R/W 00000111B 0000C0H PWCSL0 R/W R/W 00000000B 0000C1H PWCSH0 PWC control status register ch.0 Address Abbreviation 0000B0H ICR00 0000B1H 0000C2H 0000C3H PWC0 Register Resource name Interrupt controller Interrupt controller R, R/W R, R/W PWC data buffer register ch.0 ⎯ R/W Initial value 00000111B 00000111B 00000111B 00000111B 00000000B PWC timer (ch.0) XXXXXXXXB XXXXXXXXB 0000C4H DIV0 Divide ratio control register ch.0 R/W R/W 0000C5H ADER0 A/D input enable register 0 R/W R/W 0000C6H ADCS0 A/D control status register 0 R/W R/W 0000C7H ADCS1 A/D control status register 1 W, R/W W, R/W 0000C8H ADCR0 A/D data register 0 R R 0000C9H ADCR1 A/D data register 1 R R 0000CAH ADSR0 A/D setting register 0 R/W R/W 00000000B 0000CBH ADSR1 A/D setting register 1 R/W R/W 00000000B 0000CCH DAT0 D/A data register 0 R/W R/W XXXXXXXXB 0000CDH DAT1 D/A data register 1 R/W R/W 0000CEH DACR0 D/A control register 0 R/W R/W 0000CFH DACR1 D/A control register 1 R/W R/W 0000D0H ADER1 A/D input enable register 1 R/W R/W 0000D1H to 0000EFH XXXXXX00B Port 6, A/D 11111111B 000XXXX0 B 0000000XB 8/10-bit A/D converter 8-bit D/A converter XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXX0B XXXXXXX0B Port 7, A/D 11111111B Prohibited area (Continued) DS07-13751-2E 27 MB90820B Series (Continued) Address Abbreviation Register 0000F0H to 0000FFH Byte access Word access Resource name Initial value External area 001FF0H PADRL0 Program address detection register 0 (lower) R/W R/W 001FF1H PADRM0 Program address detection register 0 (middle) R/W R/W 001FF2H PADRH0 Program address detection register 0 (higher) R/W R/W 001FF3H PADRL1 Program address detection register 1 (lower) R/W R/W 001FF4H PADRM1 Program address detection register 1 (middle) R/W R/W 001FF5H PADRH1 Program address detection register 1 (higher) R/W R/W Address match detection XXXXXXXXB XXXXXXXXB XXXXXXXXB Address match detection XXXXXXXXB XXXXXXXXB XXXXXXXXB * : For MB90F828B only. Prohibited for the other products. • Meaning of abbreviations used for reading and writing R/W: Read and write enabled R : Read-only W : Write-only • Explanation of initial values 0 : The bit is initialized to “0”. 1 : The bit is initialized to “1”. X : The initial value of the bit is undefined. 28 DS07-13751-2E MB90820B Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause EI2OS support Interrupt vector Number Reset #08 INT9 instruction Exception processing A/D converter conversion complete Output compare ch.0 match End of measurement by PWC timer ch.0 / PWC timer ch.0 overflow 16-bit PPG timer ch.0 Output compare ch.1 match 16-bit PPG timer ch.1 Output compare ch.2 match 16-bit reload timer ch.1 underflow Output compare ch.3 match DTP/ext. interrupt ch.0/ch.1 detection DTTI Output compare ch.4 match DTP/ext. interrupt ch.2/ch.3 detection Output compare ch.5 match End of measurement by PWC timer ch.1 / PWC timer ch.1 overflow DTP/ext. interrupt ch.4 detection DTP/ext. interrupt ch.5 detection DTP/ext. interrupt ch.6 detection DTP/ext. interrupt ch.7 detection Waveform generator 16-bit timers ch.0/ ch.1/ch.2 underflow 16-bit reload timer ch.0 underflow 16-bit free-run timer zero detect 16-bit PPG timer ch.2 Input capture ch.0/ch.1 16-bit free-run timer compare clear Input capture ch.2/ch.3 Time-base timer UART ch.1 receive UART ch.1 send UART ch.0 receive UART ch.0 send Flash memory status Delayed interrupt generator module Address 08H FFFFDCH #09 09H FFFFD8H #10 #11 #12 0AH 0BH 0CH FFFFD4H FFFFD0H FFFFCCH #13 0DH FFFFC8H #14 #15 #16 #17 #18 #19 0EH 0FH 10H 11H 12H 13H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H #20 14H FFFFACH #21 #22 #23 15H 16H 17H FFFFA8H FFFFA4H FFFFA0H #24 18H FFFF9CH #25 #26 #27 #28 19H 1AH 1BH 1CH FFFF98H FFFF94H FFFF90H FFFF8CH #29 1DH FFFF88H #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR Address ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Priority High Low : Can be used and support the EI2OS stop request. : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used. DS07-13751-2E 29 MB90820B Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Symbol Parameter Rating Unit Remarks Min Max VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *2 AVR VSS − 0.3 VSS + 6.0 V AVCC ≥ AVR, AVR ≥ AVss VI VSS − 0.3 VSS + 6.0 V *3 VO VSS − 0.3 VSS + 6.0 V *3 ICLAMP − 2.0 + 2.0 mA *5 Σ | ICLAMP | ⎯ 20 mA *5 IOL ⎯ 15 mA *4 IOLAV1 ⎯ 4 mA Except for P00 to P07, P82 to P87 IOLAV2 ⎯ 12 mA P00 to P07, P82 to P87 ΣIOL ⎯ 100 mA ΣIOLAV ⎯ 50 mA IOH ⎯ −15 mA “H” level average output current IOHAV ⎯ −4 mA “H” level total maximum output current ΣIOH ⎯ −100 mA ΣIOHAV ⎯ −50 mA Power consumption PD ⎯ 430 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C 1 Power supply voltage* 1 Input voltage* Output voltage* 1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level total average output current Storage temperature *4 *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC must never exceed VCC when the power is turned on. *3 : VI and VO must never exceed VCC + 0.3 V. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : The maximum output current is a peak value for a corresponding pin. (Continued) 30 DS07-13751-2E MB90820B Series (Continued) *5 : • • • • • • • • • • • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50, P51, P80 to P87. Use within recommended operating conditions. Use at DC voltage (current). The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. Care must be taken not to leave the +B input pin open. Note that analog system input/output pins (LCD drive pins and comparator input pins, etc.) other than the A/D input pins cannot accept +B input. Sample recommended circuits: Input/output equivalent circuits Protective diode Vcc P-ch Limiting resistance +B input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-13751-2E 31 MB90820B Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage “H” level input voltage Symbol Smoothing capacitor Condition Min Max ⎯ ⎯ 4.5 5.5 V At normal operation TA = −40 °C to +85 °C ⎯ ⎯ 4.0 5.5 V Normal operation when D/A converter is not used TA = −40 °C to +85 °C Unit VCC AVCC Remarks ⎯ ⎯ 3.5 5.5 V Normal operation when A/D converter and D/A converter are not used TA = −40 °C to +85 °C ⎯ ⎯ 3.0 5.5 V Maintains state in stop mode VIH P30 to P37, P60 to P67 0.7 VCC VCC + 0.3 V CMOS input VIHS P00 to P07, P10 to P17, P20 to P27, P40 to P44, P45*1, P46, P47, P50, P51, P70, P71, P72*1, P73 to P77, P80 to P87, RST 0.8 VCC VCC + 0.3 V CMOS hysteresis input VIHM MD0, MD1, MD2 VCC = 5 V VCC − 0.3 VCC + 0.3 P30 to P37, P60 to P67 ± 10% VSS − 0.3 0.3 VCC V MD input V CMOS input V CMOS hysteresis input V MD input *2 VIL “L” level input voltage Value Pin name VILS P00 to P07, P10 to P17, P20 to P27, P40 to P44, P45*1, P46, P47, P50, P51, P70, P71, P72*1, P73 to P77, P80 to P87, RST VSS − 0.3 VILM MD0, MD1, MD2 VSS − 0.3 VSS + 0.3 0.2 VCC CS ⎯ ⎯ 0.1 1.0 µF Reference input voltage of A/D converter AVR ⎯ ⎯ 2.7 AVCC V Operating temperature TA ⎯ ⎯ −40 +85 °C *1 : UART ch.0/ch.1 data input pins P45/SIN0, P72/SIN1/AN10 can be used as CMOS input by the communication prescaler control register (CDRR). *2 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. On the VCC pin, connect a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS. (Continued) 32 DS07-13751-2E MB90820B Series (Continued) • C pin connection circuit C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-13751-2E 33 MB90820B Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max Parameter Symbol Pin name “H” level output voltage VOH All output pins VOL1 All pins except VCC = 4.5 V, P00 to P07 IOL1 = 4.0 mA P82 to P87 VOL2 P00 to P07 P82 to P87 IIL All input pins Pull-up resistance RUP P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST Pull-down resistance RDOWN MD2 “L” level output voltage Input leakage current VCC = 4.5 V, IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V ⎯ ⎯ 0.4 V VCC = 4.5 V, IOL2 = 12.0 mA ⎯ ⎯ 0.4 V VCC = 5.5 V, VSS < VI< VCC −5 ⎯ +5 µA At pull-up disabled ⎯ 25 50 100 kΩ MASK ROM product ⎯ 25 50 100 kΩ MASK ROM product (Continued) 34 DS07-13751-2E MB90820B Series (Continued) Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition Power supply current* Max ⎯ 35 50 mA MASK ROM product ⎯ 45 60 mA Flash memory product VCC = 5.0 V, Internal frequency: 24 MHz, At writing in flash memory ⎯ 60 75 mA Flash memory product VCC = 5.0 V, Internal frequency: 24 MHz, At erasing memory ⎯ 65 80 mA Flash memory product Input capacitance ⎯ ⎯ ICTS VCC = 5.0 V, Internal frequency: 2 MHz, At main timer mode ⎯ ICCT VCC = 5.0 V, Internal frequency: 8 MHz, At timer mode, TA = +25 °C ICCH In stop mode, TA = +25 °C CIN VCC Except AVCC, AVSS, AVR, C, VCC and VSS Remarks Typ VCC = 5.0 V, Internal frequency: 24 MHz, At sleep mode ICCS Unit Min VCC = 5.0 V, Internal frequency: 24 MHz, At normal operation ICC Value ⎯ ⎯ ⎯ ⎯ mA MASK ROM product 15 25 ⎯ Flash memory product mA MASK ROM product 0.3 0.8 mA Flash memory product mA MASK ROM product 3 7 ⎯ ⎯ mA 5 20 5 15 mA Flash memory product µA MASK ROM product mA Flash memory product pF * : The power supply current is regulated with an external clock. DS07-13751-2E 35 MB90820B Series 4. AC Characteristics (1) Clock Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Unit Remarks Min Typ Max Parameter Clock frequency X0, X1 FC Clock cycle time tHCYL 3 ⎯ 16 When using oscillation circuit 3 ⎯ 24 When using external clock 4 ⎯ 24 4 ⎯ 12 2 multiplied PLL 4 ⎯ 8 3 multiplied PLL 4 ⎯ 6 4 multiplied PLL 4 ⎯ 4 6 multiplied PLL 62.5 ⎯ 333 ns When using oscillation circuit 41.67 ⎯ 333 ns When using external clock MHz X0, X1 1 multiplied PLL Input clock pulse width PWH, PWL X0 10 ⎯ ⎯ ns When using external clock, duty ratio is about 30% to 70%. Input clock rise/fall time tCR tCF X0 ⎯ ⎯ 5 ns When using external clock Internal operating clock frequency fCP ⎯ 1.5 ⎯ 24 MHz Internal operating clock cycle time tCP ⎯ 41.67 ⎯ 666 ns tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF 36 tCR DS07-13751-2E MB90820B Series Power supply voltage VCC (V) Relationship between internal operating clock frequency and power supply voltage Guaranteed D/A Converter operating range 5.5 4.5 Operation guarantee range of PLL 4.0 Guaranteed A/D Converter operating range 3.5 Normal operation guarantee range 1.5 4 24 Internal operating clock frequency fCp (MHz) Internal operating clock frequency fCp (MHz) Relationship between clock frequency and internal operating clock frequency X6 X4 X3 X2 X1 24 16 Not multiplied 12 8 4 1.5 3 4 8 12 16 Clock frequency FC (MHz) 24 The AC ratings are measured for the following measurement reference voltages • Input signal waveform • Output signal waveform Hysteresis input pin Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC DS07-13751-2E 37 MB90820B Series (2) External Reset Parameter Symbol Reset input time (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Unit Remarks Min Max Pin name RST tRSTL 500 ⎯ ns In normal operation Oscillation time of oscillator* + 100 ⎯ µs In stop mode 100 ⎯ µs In time-base timer mode * : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms. • In normal operation mode tRSTL RST 0.2 VCC 0.2 VCC • In stop mode, at power on tRSTL RST 0.2 VCC 0.2 VCC 90% of the oscillation amplitude X0 Internal operation clock Oscillation time of oscillator 100 µs Oscillator stabilization time Instruction execution Internal reset 38 DS07-13751-2E MB90820B Series (3) Power-on Reset Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Max Power supply rising time tR VCC Power supply cut-off time tOFF VCC 0.05 30 ms 1 ⎯ ms ⎯ Waiting time for power supply on tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Note : Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, be sure to set the slope of rising within 50 mV/ms or less as shown below. VCC 3.0 V VSS DS07-13751-2E RAM data hold time Be sure to set the slope of rising within 50 mV/ms or less. 39 MB90820B Series (4) UART Parameter Symbol (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Min Max 8 tCP ⎯ ns −80 + 80 ns 100 ⎯ ns SCK0 to SCK1 SIN0 to SIN1 60 ⎯ ns tSHSL SCK0 to SCK1 4 tCP ⎯ ns Serial clock “L” pulse width tSLSH SCK0 to SCK1 4 tCP ⎯ ns SCK ↓ → SOT delay time tSLOV SCK0 to SCK1 SOT0 to SOT1 ⎯ 150 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK1 SIN0 to SIN1 60 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK1 SIN0 to SIN1 60 ⎯ ns Serial clock cycle time tSCYC SCK0 to SCK1 SCK ↓ → SOT delay time tSLOV SCK0 to SCK1 SOT0 to SOT1 Valid SIN → SCK ↑ tIVSH SCK0 to SCK1 SIN0 to SIN1 SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width CL = 80 pF + 1 TTL for an output pin of internal shift clock mode CL = 80 pF + 1 TTL for an output pin of external shift clock mode Notes : • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. • tCP is machine cycle time (unit : ns). 40 DS07-13751-2E MB90820B Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN DS07-13751-2E tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 41 MB90820B Series (5) Resources Input Timing Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Min Max Symbol IN0 to IN3, TIN0 to TIN1, PWI0 to PWI1, DTTI tTIWH tTIWL Input pulse width IN0 to IN3, TIN0 to TIN1, PWI0 to PWI1, DTTI 0.8 VCC ⎯ 4 tCP ⎯ ns 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (6) Trigger Input Timing Parameter Input pulse width (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Min Max Symbol tTRGH tTRGL 0.8 VCC 5 tCP ⎯ ns 0.8 VCC 0.2 VCC INT0 to INT7 tTRGH 42 ⎯ INT0 to INT7 0.2 VCC tTRGL DS07-13751-2E MB90820B Series 5. A/D Converter Electrical Characteristics Parameter Resolution (3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin CondiSymbol Unit Remarks name tion Min Typ Max ⎯ ⎯ ⎯ 10 ⎯ bit Total error ⎯ ⎯ ⎯ ⎯ ±3.0 LSB Non-linearity error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB Differential linearity error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB Zero transition voltage VOT AN0 to AN15 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V Full-scale transition voltage VFST AN0 to AN15 AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB V Compare time ⎯ ⎯ 1.0 ⎯ ⎯ µs 4.5 V < AVcc < 5.5 V 2.0 ⎯ ⎯ µs 4.0 V < AVcc < 4.5 V Sampling time ⎯ ⎯ 0.5 ⎯ ⎯ µs 4.5 V < AVcc < 5.5 V 1.2 ⎯ ⎯ µs 4.0 V < AVcc < 4.5 V Analog port input current IAIN AN0 to AN15 − 0.3 ⎯ + 0.3 µA Analog input voltage VAIN AN0 to AN15 AVSS ⎯ AVR V Reference voltage ⎯ AVR AVSS + 2.7 ⎯ AVCC V Power supply current ⎯ 2.4 4.7 mA IAH ⎯ ⎯ 5 ⎯ 600 900 ⎯ ⎯ 5 ⎯ ⎯ 4 Reference voltage supply current Offset between channels IA IR IRH — AVCC AVR AN0 to AN15 ⎯ µA * µA µA * LSB * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) Note : The error increases proportionally as |AVR - AVSS| decreases. DS07-13751-2E 43 MB90820B Series 6. A/D Converter Glossary Resolution Non linearity error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line (“00 0000 0000”↔ “00 0000 0001”) and full-scale transition line (“11 1111 1110”↔“11 1111 1111”) and actual conversion characteristics. Differential linearity error : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value Total error : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH Digital output 3FDH 1.5 LSB Actual conversion characteristics {1 LSB × (N − 1) + 0.5 LSB} 004H VNT (Measurement value) 003H Actual conversion characteristics 002H 001H Ideal characteristics 0.5 LSB AVSS AVR Analog input Total error for digital output N = 1 LSB = (Ideal value) VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVss [V] 1024 [LSB] N : A/D converter digital output value VOT(Ideal value) = AVss + 0.5 LSB [V] VFST(Ideal value) = AVR − 1.5 LSB [V] VNT : Voltage at which of digital output transitions from (N − 1)H to NH. (Continued) 44 DS07-13751-2E MB90820B Series (Continued) Linearity error 3FEH 3FDH Digital output Ideal characteristics Actual conversion characteristics (N + 1)H {1 LSB × (N − 1) + VOT } VFST (Measurement value) VNT (Measurement value) 004H Actual conversion characteristics 003H 002H Actual conversion characteristics NH V(N + 1)T (N − 1)H (Measurement value) VNT Ideal characteristics 001H Digital output 3FFH Differential linearity error (Measurement value) Actual conversion characteristics (N − 2)H VOT(Measurement value) AVss AVR AVss Linearity error of = digital output N VNT − {1 LSB × (N − 1) + VOT} 1 LSB Differential linearity error V (N + 1) T − VNT = 1 LSB of digital output N 1 LSB = N AVR Analog input Analog input VFST − VOT 1022 [LSB] − 1 [LSB] [V] : A/D converter digital output value VOT : Voltage at which of digital output transmissions from “000H” to “001H”. VFST : Voltage at which of digital output transmissions from “3FEH” to “3FFH”. DS07-13751-2E 45 MB90820B Series 7. Notes on Using A/D Converter • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input circuit model R Analog input Comparator C During sampling : ON MB90822B/823B MB90F822B/F823B R 2.0 kΩ (Max) 2.0 kΩ (Max) C 14.4 pF (Max) 16.0 pF (Max) Note : The values are reference values. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ) 20 100 18 External impedance [kΩ] External impedance [kΩ] 90 MB90822B/ 823B MB90F822B/F823B 80 70 60 50 40 30 20 10 MB90822B/ 823B MB90F822B/F823B 16 14 12 10 8 6 4 2 0 0 0 5 10 15 20 25 30 35 Minimum sampling time [µs] 0 1 2 3 4 5 6 7 8 Minimum sampling time [µs] • About the error The accuracy gets worse as | AVR−AVSS | becomes smaller. 46 DS07-13751-2E MB90820B Series 8. Electrical Characteristics of D/A convertor Parameter (VCC = AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max Resolution ⎯ ⎯ ⎯ 8 ⎯ bit Differential linearity error ⎯ ⎯ ⎯ ⎯ ±0.5 LSB Conversion time ⎯ ⎯ ⎯ 0.45 ⎯ µs Analog output impedance ⎯ ⎯ ⎯ 2.9 3.8 kΩ ⎯ 160 920 µA ⎯ 0.1 ⎯ µA Power supply current IDVR IDVRS AVCC ⎯ * D/A stops * : With load capacitance 20 pF. DS07-13751-2E 47 MB90820B Series 9. Flash Memory Program/Erase Characteristics Parameter Condition Sector erase time Chip erase time TA = +25 °C VCC = 5.0 V Word (16 bit width) programing time Value Unit Remarks Min Typ Max ⎯ 1 15 s Excludes programming prior to erasure ⎯ 9 ⎯ s Excludes programming prior to erasure ⎯ 16 3,600 µs Except for the overhead time of the system Program/Erase cycle ⎯ 10,000 ⎯ ⎯ cycle Flash data retention time Average TA = +85 °C 20 ⎯ ⎯ year * * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . ■ ORDERING INFORMATION Part number Package MB90F823BPMC MB90F822BPMC MB90822BPMC MB90823BPMC MB90F828BPMC 80-pin plastic LQFP (FPT-80P-M21) MB90F823BPMC1 MB90F822BPMC1 MB90822BPMC1 MB90823BPMC1 MB90F828BPMC1 80-pin plastic LQFP (FPT-80P-M22) MB90F823BPF MB90F822BPF MB90822BPF MB90823BPF MB90F828BPF 80-pin plastic QFP (FPT-80P-M06) 48 DS07-13751-2E MB90820B Series ■ PACKAGE DIMENSIONS 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12 mm × 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.47 g Code (Reference) P-LFQFP80-12×12-0.50 (FPT-80P-M21) 80-pin plastic LQFP (FPT-80P-M21) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 60 0.145±0.055 (.006±.002) 41 61 40 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 INDEX 0˚~8˚ 80 (Mounting height) 0.10±0.05 (.004±.002) (Stand off) 21 "A" LEAD No. 1 20 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) M ©2006-2008 FUJITSU MICROELECTRONICS LIMITED F80035S-c-2-3 C 2006 FUJITSU LIMITED F80035S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS07-13751-2E 49 MB90820B Series 80-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 14.00 mm × 14.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.62 g Code (Reference) P-LFQFP80-14×14-0.65 (FPT-80P-M22) 80-pin plastic LQFP (FPT-80P-M22) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 60 0.145±0.055 (.006±.002) 41 40 61 0.10(.004) Details of "A" part +0.20 +.008 1.50 –0.10 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8˚ 21 80 1 "A" 20 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) 0.10±0.10 (.004±.004) (Stand off) M ©2007-2008 FUJITSU MICROELECTRONICS LIMITED F80036S-c-1-2 C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 2007 FUJITSU LIMITED F80036S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 50 DS07-13751-2E MB90820B Series (Continued) 80-pin plastic QFP Lead pitch 0.80 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP80-14×20-0.80 (FPT-80P-M06) 80-pin plastic QFP (FPT-80P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 64 41 40 65 0.10(.004) 17.90±0.40 (.705±.016) * 14.00±0.20 (.551±.008) INDEX Details of "A" part 25 80 0.25(.010) +0.30 3.05 –0.20 +.012 .120 –.008 (Mounting height) 1 24 0.80(.031) 0.37±0.05 (.015±.002) 0.16(.006) 0~8° M "A" C 2002-2008 FUJITSU MICROELECTRONICS LIMITED F80010S-c-6-6 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) +0.10 0.30 –0.25 +.004 .012 –.010 (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-13751-2E 51 MB90820B Series ■ MAIN CHANGES IN THIS EDITION Page Section Change Results 4 ■ PACKAGE AND CORRESPONDING PRODUCTS 43 ■ ELECTRICAL CHARACTERISTICS Changed the unit of zero transition voltage and full-scale tran5. A/D Converter Electrical sition voltage. Characteristics mV → V ■ ORDERING INFORMATION 48 Changed the MB90822B (FPT-80P-M21). X : Not available → : Available Added the part number. MB90822BPMC MB90823BPMC The vertical lines marked in the left side of the page show the changes. 52 DS07-13751-2E MB90820B Series MEMO DS07-13751-2E 53 MB90820B Series MEMO 54 DS07-13751-2E MB90820B Series MEMO DS07-13751-2E 55 MB90820B Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. 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