LINER LTC2420I 20-bit upower no latency adc in so-8 Datasheet

Final Electrical Specifications
LTC2420
20-Bit µPower
No Latency ∆Σ ADC in SO-8
TM
January 2000
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FEATURES
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DESCRIPTIO
20-Bit ADC in SO-8 Package
8ppm INL, No Missing Codes at 20 Bits
4ppm Full-Scale Error
0.5ppm Offset
1.2ppm Noise
Digital Filter Settles in a Single Cycle. Each
Conversion Is Accurate, Even After an Input Step.
Internal Oscillator—No External Components
Required
Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps
110dB Min, 50Hz/60Hz Notch Filter
Reference Input Voltage: 0.1V to VCC
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200µA) and Auto Shutdown
Pin Compatible with 24-Bit LTC2400
The LTC®2420 is a micropower 20-bit A/D converter with
an integrated oscillator, 8ppm INL and 1.2ppm RMS
noise that operates from 2.7V to 5.5V. It uses delta-sigma
technology and provides a digital filter that settles in a
single cycle for multiplexed applications. Through a single
pin, the LTC2420 can be configured for better than 110dB
rejection at 50Hz or 60Hz ±2%, or it can be driven by an
external oscillator for a user-defined rejection frequency
in the range 1Hz to 800Hz. The internal oscillator requires
no external frequency setting components.
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
4-Digit DVMs
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
The converter accepts any external reference voltage from
0.1V to VCC. With its extended input conversion range of
–12.5% VREF to 112.5% VREF, the LTC2420 smoothly
resolves the offset and overrange problems of preceding
sensors or signal conditioning circuits.
The LTC2420 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
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APPLICATIO S
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TYPICAL APPLICATIO
Total Unadjusted Error vs Output Code
VCC
1µF
1
VCC
FO
8
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
LTC2420
REFERENCE
VOLTAGE
0.1V TO VCC
2
ANALOG
INPUT RANGE
–0.12VREF TO 1.12VREF
3
4
VREF
VIN
GND
SCK
SDO
CS
7
6
3-WIRE
SPI INTERFACE
5
TOTAL UNADJUSTED ERROR (ppm)
10
2.7V TO 5.5V
VCC = 5V
VREF = 5V
TA = 25°C
FO = LOW
8
6
4
2
0
–2
–4
–6
–8
–10
2420 TA01
0
524,288
OUTPUT CODE (DECIMAL)
1,048,575
2420 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC2420
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ABSOLUTE MAXIMUM RATINGS
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PACKAGE/ORDER INFORMATION
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2420C ............................................... 0°C to 70°C
LTC2420I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
TOP VIEW
VCC 1
8
FO
VREF 2
7
SCK
VIN 3
6
SDO
GND 4
5
CS
LTC2420CS8
LTC2420IS8
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
2420
2420I
TJMAX = 125°C, θJA = 130°C/W
Consult factory for Military grade parts.
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CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4
8
10
20
ppm of VREF
ppm of VREF
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, (Note 5)
●
Integral Nonlinearity
VREF = 2.5V (Note 6)
VREF = 5V (Note 6)
●
●
Integral Nonlinearity (Fast Mode)
VREF = 5V, VREF = 2.5V, 100 Samples/Second, fO = 2.048MHz
●
40
250
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC
●
0.5
10
ppm of VREF
Offset Error (Fast Mode)
2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz
Offset Error Drift
2.5V ≤ VREF ≤ VCC
Full-Scale Error
2.5V ≤ VREF ≤ VCC
Full-Scale Error (Fast Mode)
2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz
20
Bits
3
ppm of VREF
0.04
4
●
10
ppm of VREF/°C
10
ppm of VREF
ppm of VREF
Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC
Total Unadjusted Error
VREF = 2.5V
VREF = 5V
Output Noise
VIN = 0V (Note 13)
6
µVRMS
Output Noise (Fast Mode)
VREF = 5V, 100 Samples/Second, fO = 2.048MHz
20
µVRMS
Normal Mode Rejection 60Hz ±2%
(Note 7)
●
110
130
dB
Normal Mode Rejection 50Hz ±2%
(Note 8)
●
110
130
dB
Power Supply Rejection, DC
VREF = 2.5V, VIN = 0V
100
dB
Power Supply Rejection, 60Hz ±2%
VREF = 2.5V, VIN = 0V, (Note 7)
110
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, VIN = 0V, (Note 8)
110
dB
2
0.04
8
16
ppm of VREF/°C
ppm of VREF
ppm of VREF
LTC2420
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Voltage Range
(Note 14)
VREF
Reference Voltage Range
CS(IN)
Input Sampling Capacitance
CS(REF)
Reference Sampling Capacitance
IIN(LEAK)
Input Leakage Current
CS = VCC
●
– 100
1
100
nA
IREF(LEAK)
Reference Leakage Current
VREF = 2.5V, CS = VCC
●
– 100
1
100
nA
●
– 0.125 • VREF
●
0.1
TYP
MAX
UNITS
1.125 • VREF
V
VCC
V
1
pF
1.5
pF
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
High-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
●
●
TYP
2.7
200
20
MAX
UNITS
5.5
V
300
30
µA
µA
3
LTC2420
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
20-Bit Effective Resolution
12-Bit Effective Resolution
tHEO
TYP
MAX
UNITS
kHz
MHz
●
●
2.56
2.56
307.2
2.048
External Oscillator High Period
●
0.5
390
µs
tLEO
External Oscillator Low Period
●
0.5
390
µs
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.23
tDOUT_ESCK
External SCK 24-Bit Data Output Time
(Note 9)
●
t1
CS ↓ to SDO Low Z
t2
CS ↑ to SDO High Z
t3
CS ↓ to SCK ↓
(Note 10)
t4
CS ↓ to SCK ↑
(Note 9)
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
t6
130.66
133.33
136
156.80
160
163.20
20480/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.25
1.28
192/fEOSC (in kHz)
ms
ms
24/fESCK (in kHz)
ms
●
0
150
ns
●
0
150
ns
●
0
150
ns
●
50
ns
200
●
(Note 5)
●
15
SCK Set-Up Before CS ↓
●
50
SCK Hold After CS ↓
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: All voltages are with respect to GND. VCC = 2.7 to 5.5V unless
otherwise specified. RSOURCE = 0Ω.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
4
●
●
●
ns
ns
ns
50
ns
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values VREF > 2.5V the extended input
of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤
0.267V + 0.89 • VCC the input voltage range is – 0.3V to 1.125 • VREF.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is – 0.3V
to VCC + 0.3V.
LTC2420
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
VREF (Pin 2): Reference Input. The reference voltage range
is 0.1V to VCC.
VIN (Pin 3): Analog Input. The input voltage range is
– 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input
voltage range may be limited by the pin absolute maximum rating of – 0.3V to VCC + 0.3V.
GND (Pin 4): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground
in a single point grounding system.
CS (Pin 5): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 6): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CS is HIGH (CS = VCC), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface. A
weak internal pull-up is automatically activated in Internal
Serial Clock Operation mode. The Serial Clock mode is
determined by the level applied to SCK at power up and the
falling edge of CS.
FO (Pin 8): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV) the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency fEOSC/2560.
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APPLICATIO S I FOR ATIO
The LTC2420 is pin compatible with the LTC2400. The two
devices are designed to allow the user to incorporate
either device in the same design with no modifications.
While the LTC2420 output word length is 24 bits (as
opposed to the 32-bit output of the LTC2400), its output
clock timing can be identical to the LTC2400. As shown in
Figure 1, the LTC2420 data output is concluded on the
falling edge of the 24th serial clock (SCK). In order to
maintain drop-in compatibility with the LTC2400, it is
possible to clock the LTC2420 with an additional 8 serial
clock pulses. This results in 8 additional output bits which
are always logic HIGH.
Output Data Format
The LTC2420 serial output data stream is 24 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 20 bits are
the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
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LTC2420
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APPLICATIO S I FOR ATIO
CS
8
8
8
8 (OPTIONAL)
SCK
SDO
EOC = 0
EOC = 1
DATA OUT
4 STATUS BITS 20 DATA BITS
CONVERSION
CONVERSION
SLEEP
EOC = 1
LAST 8 BITS ALWAYS 1
DATA OUTPUT
2420 F01
Figure 1. LTC2420 Compatible Timing with the LTC2400
Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣ VIN ≤ VREF, this bit is LOW. If the input is outside the
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
EXR
VIN > VREF
0
0
1
1
0 < VIN ≤ VREF
0
0
1
0
0
0
1/0
0
0
0
0
1
Input Range
VIN =
0+/0 –
VIN < 0
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the VIN pin is maintained within
the – 0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from – 0.125 • VREF to 1.125 • VREF. For input voltages
greater than 1.125 • VREF, the conversion result is clamped
to the value corresponding to 1.125 • VREF. For input
voltages below – 0.125 • VREF, the conversion result is
clamped to the value corresponding to – 0.125 • VREF.
Bit 19 (fifth output bit) is the most significant bit (MSB).
Operation at Higher Data Output Rates
Bits 19-0 are the 20-bit conversion result MSB first.
The LTC2420 typically operates with an internal oscillator
of 153.6kHz. This corresponds to a notch frequency of
60Hz and an output rate of 7.5 samples/second. The
internal oscillator is enabled if the FO pin is logic LOW
(logic HIGH for a 50Hz notch). It is possible to drive the FO
pin with an external oscillator for higher data output rates.
As shown in Figure 3, an external clock of 2.048MHz
applied to the FO pin results in a notch frequency of 800Hz
with a data output rate of 100 samples/second.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 2. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising
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Figure 4 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
LTC2420
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APPLICATIO S I FOR ATIO
CS
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
EOC
“0”
SIG
EXT
MSB
SDO
BIT 4
BIT 0
LSB20
Hi-Z
SCK
1
2
3
4
SLEEP
5
19
20
24
DATA OUTPUT
CONVERSION
2420 F02
Figure 2. Output Data Timing
Table 2. LTC2420 Output Data Format
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
EXR
Bit 19
MSB
Bit 18
Bit 17
Bit 16
Bit 15
…
Bit 0
LSB
VIN > 9/8 • VREF
0
0
1
1
0
0
0
1
1
...
1
9/8 • VREF
0
0
1
1
0
0
0
1
1
...
1
VREF + 1LSB
0
0
1
1
0
0
0
0
0
...
0
VREF
0
0
1
0
1
1
1
1
1
...
1
3/4VREF + 1LSB
0
0
1
0
1
1
0
0
0
...
0
3/4VREF
0
0
1
0
1
0
1
1
1
...
1
Input Voltage
1/2VREF + 1LSB
0
0
1
0
1
0
0
0
0
...
0
1/2VREF
0
0
1
0
0
1
1
1
1
...
1
1/4VREF + 1LSB
0
0
1
0
0
1
0
0
0
...
0
1/4VREF
0
0
1
0
0
0
1
1
1
...
1
0+/0 –
0
0
1/0*
0
0
0
0
0
0
...
0
–1LSB
0
0
0
1
1
1
1
1
1
...
1
–1/8 • VREF
0
0
0
1
1
1
1
0
0
...
0
VIN < –1/8 • VREF
0
0
0
1
1
1
1
0
0
...
0
*The sign bit changes state during the 0 code.
800Hz NOTCH (100 SAMPLES/SECOND)
60Hz NOTCH (7.5 SAMPLES/SECOND)
1
2
3
4
LTC2420
VCC
FO
VREF
SCK
VIN
SDO
GND
CS
8
7
6
TOTAL UNADJUSTED ERROR (ppm)
256
EXTERNAL 2.048MHz CLOCK SOURCE
12 BITS
192
160
13 BITS
128
96
14 BITS
64
32
0
5
VREF = 5V
224
16 BITS
0
50
100
150
OUTPUT RATE (SAMPLES/SEC)
INTERNAL 153.6kHz OSCILLATOR
2420 F03
Figure 3. Selectable 100 Samples/Second Turbo Mode
2420 F04
Figure 4. Total Error vs Output Rate (VREF = 5V)
7
LTC2420
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APPLICATIO S I FOR ATIO
output data rate (ODR) and the frequency applied to the FO
pin (FO) is:
ODR = FO/20480
For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure 5,
for output data rates of 100 samples/second, the TUE is
better than 15 bits for VREF below 2.5V. Figure 6 shows an
unaveraged total unadjusted error for the LTC2420 operating at 100 samples/second with VREF = 2.5V. Figure 7
shows the same device operating with a 5V reference and
an output data rate of 7.5 samples/second.
10
256
OUTPUT RATE = 100sps
12 BITS
224
TOTAL UNADJUSTED ERROR (ppm)
TOTAL UNADJUSTED ERROR (ppm)
At 100 samples/second, the LTC2420 can be used to
capture transient data. This is useful for monitoring settling or auto gain ranging in a system. The LTC2420 can
monitor signals at an output rate of 100 samples/second.
After acquiring 100 samples/second data the FO pin may
be driven LOW enabling 60Hz rejection to 110dB and the
highest possible DC accuracy. The no latency architecture
of the LTC2420 allows consecutive readings (one at 100
samples/second the next at 7.5 samples/second) without
interaction between the two readings.
192
160
13 BITS
128
96
14 BITS
64
15 BITS
32
0
1.0
VCC = 5V
VREF = 2.5V
5
0
–5
–10
–15
–20
–25
–30
–35
–40
1.5
2.0 2.5 3.0 3.5 4.0
REFERENCE VOLTAGE (V)
4.5
0
5.0
2420 F06
2420 F05
Figure 5. Total Error vs VREF (Output Rate = 100sps)
Figure 6. Total Unadjusted Error at
100 Samples/Second (No Averaging)
TOTAL UNADJUSTED ERROR (ppm)
6
VCC = 5V
VREF = 5V
4
2
0
–2
–4
–6
–8
–10
5
0
INPUT VOLTAGE (V)
2420 F07
Figure 7. Total Unadjusted Error at 7.5 Samples/Second
(No Averaging)
8
2.5
INPUT VOLTAGE (V)
LTC2420
U
W
U
U
APPLICATIO S I FOR ATIO
As shown in Figure 8, the LTC2420 can capture transient
data with 90dB of dynamic range (with a 300mVP-P input
signal at 2Hz). The exceptional DC performance of the
LTC2420 enables signals to be digitized independent of a
0
fIN = 2Hz
500ms
0.15
2Hz
100sps
0V OFFSET
–20
0.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
0.20
large DC offset. Figures 9a and 9b show the dynamic
performance with a 15Hz signal superimposed on a 2V DC
level. The same signal with no DC level is shown in Figures
9c and 9d.
0.05
0
–0.05
–40
–60
–80
–0.10
–100
–0.15
–120
–0.20
FREQUENCY (Hz)
TIME
2420 F08b
2420 F08a
8a. Digitized Waveform
8b. Output FFT
Figure 8. Transient Signal Acquisiton
0
VIN = 300mVP-P + 2V DC
2.15
15Hz
100sps
2V OFFSET
–20
2.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
2.20
2.05
2.00
1.95
–40
–60
–80
1.90
–100
1.85
–120
1.80
FREQUENCY (Hz)
TIME
2420 F09b
2420 F09a
9a. Digitized Waveform with 2V DC Offset
0
VIN = 300mVP-P + 0V DC
0.15
15Hz
100sps
0V OFFSET
–20
0.10
MAGNITUDE (dB)
ADC OUTPUT (NORMALIZED TO VOLTS)
0.20
9b. FFT Waveform with 2V DC Offset
0.05
0.00
–0.05
–40
–60
–80
–0.10
–100
–0.15
–120
–0.20
FREQUENCY (Hz)
TIME
2420 F09d
2420 F09c
9c. Digitized Waveform with No Offset
9d. FFT Waveform with No Offset
Figure 9. Using the LTC2420’s High Accuracy Wide Dynamic Range to Digitize
a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V)
9
LTC2420
U
U
W
U
APPLICATIO S I FOR ATIO
reduces the magnitude of averaged noise by 30% and
improves resolution by 0.5 bit without compromising
linearity. Resistor R2 performs two functions: it isolates
C1 from the LTC2420’s input and limits the LTC2420’s
input current should its input voltage drop below –300mV
or swing above VCC + 300mV.
Single-Chip Instrumentation Amplifier
for the LTC2420
The circuit in Figure 10 is a simple solution for processing
differential signals in pressure transducer, weigh scale or
strain gauge applications that can operate on a supply
voltage range of ±5V to ±15V. The circuit uses an LT®1920
single-chip instrumentation amplifier to perform a differential to single-ended conversion. The amplifier’s output
voltage is applied to the LTC2420’s input and converted to
a digital value with an overall accuracy exceeding 17 bits
(0.0008%). Key circuit performance results are shown in
Table 3.
The LT1920 is the choice for applications where low cost
is important. For applications where more precision is
required, the LT1167 is a pin-to-pin alternative choice with
a lower offset voltage, lower input bias current and higher
gain accuracy than the LT1920. The LT1920’s maximum
total input-referred offset (VOST) is 135µV for a gain of
100. At the same gain, the LT1167’s VOST is 63µV. At gains
of 10 or 100, the LT1920’s maximum gain error is 0.3%
and its maximum gain nonlinearity is 30ppm. At the same
gains, the LT1167’s maximum gain error is 0.1% and its
maximum gain nonlinearity is 15ppm. Table 4 summarizes the performance of Figure 10’s circuit using the
LT1167.
The practical gain range for this topology as shown is from
5 to 100 because the LTC2420’s wide dynamic range
makes gains below 5 virtually unnecessary, whereas gain
up to 100 significantly reduce the input referred noise.
The optional passive RC lowpass filter between the
amplifier’s output and the LTC2420’s input attenuates
high frequency noise and its effects. Typically, the filter
5V 0.1µF
VREFIN
VS+ 0.1µF
2
DIFFERENTIAL
INPUT
RG**
1
8
3
VIN+
RG
1
7
LT1920
RG
VIN–
4
R1*
47Ω
6
R2*
10k
0.1µF
C1*
1µF
VS –
2
3
VCC
VREF
LTC2420
VIN
SDO
SCK
GND
4
†
†
CS
FO
5
6
7
CHIP SELECT
SERIAL DATA OUT
SERIAL CLOCK
2429 F10
8
†
SINGLE POINT
“STAR” GROUND
*OPTIONAL—SEE TEXT
**RG = 49.4k/(AV – 1): USE 5.49k FOR AV = 10; 499Ω FOR AV = 100
†USE SHORT LEAD LENGTHS
Figure 10. The LT1920 is a Simple Solution That Converts a Differential Input
to a Ground Referred Single-Ended Signal for the LTC2420
10
LTC2420
U
W
U
U
APPLICATIO S I FOR ATIO
Table 3. Typical Performance of the LTC2420 ADC When Used with the
LT1920 Instrumentation Amplifiers in Figure 9’s Differential Digitizing Circuit
VS = ±5V
PARAMETER
Differential Input Voltage Range
Zero Error
VS = ±15V
AV = 10
AV = 100
AV = 10
AV = 100
TOTAL (UNITS)
– 30 to 400
– 3 to 40
– 30 to 500
– 3 to 50
mV
–160
– 2650
– 213
– 2625
Maximum Input Current
2.0
Nonlinearity
±8.2
±7.4
Noise (Without Averaging)
1.8*
0.25*
Noise (Averaged 64 Readings)
0.2*
0.03*
21
20.6
17.2
17.3
Resolution (with Averaged Readings)
Overall Accuracy (Uncalibrated)
Common Mode Range
±6.5
±6.1
ppm
1.5*
0.27*
µVRMS
0.19*
0.03*
µVRMS
21.3
20.5
Bits
17.5
18.2
Bits
≥120
Common Mode Rejection Ratio
2/–1.5**
2.2/–1.7**
µV
nA
dB
11.5/–11**
11.7/–11.2**
V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
Table 4. Typical Performance of the LTC2420 ADC When Used with the
LT1167 Instrumentation Amplifiers in Figure 9’s Differential Digitizing Circuit
VS = ±5V
PARAMETER
VS = ±15V
AV = 10
AV = 100
AV = 10
AV = 100
TOTAL (UNITS)
– 30 to 400
– 3 to 40
– 30 to 500
– 3 to 50
mV
–94
– 1590
– 110
– 1470
µV
Nonlinearity
±4.1
±4.4
±4.1
±3.7
ppm
Noise (Without Averaging)
1.4*
0.19*
1.5*
0.18*
µVRMS
Noise (Averaged 64 Readings)
0.18*
0.02*
0.19*
0.02*
µVRMS
Resolution (with Averaged Readings)
21.4
21.0
21.3
21.1
Bits
Overall Accuracy (Uncalibrated)
18.2
18.1
18.2
19.4
Bits
2/–1.5**
2.2/–1.7**
11.5/–11**
11.7/–11.2**
Differential Input Voltage Range
Zero Error
Maximum Input Current
0.5
≥120
Common Mode Rejection Ratio
Common Mode Range
nA
dB
V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
11
LTC2420
W
PACKAGE I FOR ATIO
Dimensions in inches (millimeters) unless otherwise noted.
U
U
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
2
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
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12
Linear Technology Corporation
2420i LT/TP 0100 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000