Fairchild FSBM30SH60 Spmtm (smart power module) Datasheet

FSBM30SH60A
FSBM30SH60A
SPMTM (Smart Power Module)
General Description
Features
FSBM30SH60A is an advanced smart power module
(SPM) that Fairchild has newly developed and designed to
provide very compact and high performance ac motor
drives mainly targeting high speed low-power inverterdriven application like washing machines. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced current
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
integrated under-voltage lock-out protection. The high
speed built-in HVIC provides opto-coupler-less IGBT gate
driving capability that further reduce the overall size of the
inverter system design. In addition the incorporated HVIC
facilitates the use of single-supply drive topology enabling
the FSBM30SH60A to be driven by only one drive supply
voltage without negative bias. Inverter current sensing
application can be achieved due to the divided negative dc
terminals.
• UL Certified No. E209204
• 600V-30A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection
• Divided negative dc-link terminals for inverter current
sensing applications
• Single-grounded power supply due to built-in HVIC
• Typical switching frequency of 15kHz
• Inverter power rating of 2.4kW / 100~253 Vac
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
• Adjustable current protection level by varying series
resistor value with sense-IGBTs
Applications
• AC 100V ~ 253V 3-phase inverter drive for small power
(2.4kW) ac motor drives
• Home appliances applications requiring high switching
frequency operation like washing machines drive system
• Application ratings:
- Power : 2.4kW / 100~253 Vac
- Switching frequency : Typical 15kHz (PWM Control)
- 100% load current : 11A (Irms)
- 150% load current : 16.5A (Irms) for 1 minute
External View
Top View
Bottom View
60mm
31mm
Fig. 1.
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Integrated Power Functions
• 600V-30A IGBT inverter for 3-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 13 and 14.
• For inverter low-side IGBTs: Gate drive circuit, Short-Circuit (SC) protection
Control supply circuit under-voltage (UV) protection
• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side control supply circuit)
• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Top View
(1) VCC(L)
(2) com(L)
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) com(L)
(7) FO
(8) CFOD
(9) CSC
(24) NC
(25) NC
(26) NU
(27) NV
(28) NW
(10) RSC
(11) IN(UH)
(12) VCC(UH)
(29) U
(13) VB(U)
(14) VS(U)
(30) V
(15) IN(VH)
(16) com(H)
(17) VCC(VH)
Case Temperature (TC)
Detecting Point
(31) W
(18) VB(V)
(19) VS(V)
Ceramic Substrate
(20) IN(WH)
(21) VCC(WH)
(32) P
(22) VB(W)
(23) VS(W)
Fig. 2.
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Pin Descriptions
Pin Number
1
Pin Name
VCC(L)
2
COM(L)
Low-side Common Supply Ground
3
IN(UL)
Signal Input for Low-side U Phase
4
IN(VL)
Signal Input for Low-side V Phase
5
IN(WL)
Signal Input for Low-side W Phase
6
COM(L)
Low-side Common Supply Ground
7
VFO
8
CFOD
Capacitor for Fault Output Duration Time Selection
9
CSC
Capacitor (Low-pass Filter) for Short-Circuit Current Detection Input
10
RSC
11
IN(UH)
12
VCC(UH)
13
VB(U)
High-side Bias Voltage for U Phase IGBT Driving
14
VS(U)
High-side Bias Voltage Ground for U Phase IGBT Driving
15
IN(VH)
Signal Input for High-side V Phase
16
COM(H)
High-side Common Supply Ground
17
VCC(VH)
High-side Bias Voltage for V Phase IC
18
VB(V)
High-side Bias Voltage for V Phase IGBT Driving
19
VS(V)
High-side Bias Voltage Ground for V Phase IGBT Driving
20
IN(WH)
21
VCC(WH)
22
VB(W)
23
VS(W)
24
NC
No Connection
25
NC
No Connection
26
NU
Negative DC–Link Input for U Phase
27
NV
Negative DC–Link Input for V Phase
28
NW
29
U
Output for U Phase
30
V
Output for V Phase
31
W
Output for W Phase
32
P
Positive DC–Link Input
©2003 Fairchild Semiconductor Corporation
Pin Description
Low-side Common Bias Voltage for IC and IGBTs Driving
Fault Output
Resistor for Short-Circuit Current Detection
Signal Input for High-side U Phase
High-side Bias Voltage for U Phase IC
Signal Input for High-side W Phase
High-side Bias Voltage for W Phase IC
High-side Bias Voltage for W Phase IGBT Driving
High-side Bias Voltage Ground for W Phase IGBT Driving
Negative DC–Link Input for W Phase
Rev. E, August 2003
FSBM30SH60A
Internal Equivalent Circuit and Input/Output Pins
Bottom View
(22) V B(W )
(21) V C C(W H )
VC C
COM
(20) IN (W H )
(32) P
VB
IN
OUT
VS
(23) V S(W )
(18) V B(V )
VB
(17) V C C(VH )
VC C
(16) C O M (H )
COM
(15) IN (VH )
IN
OUT
VS
(19) V S(V )
(13) V B(U )
(12) V C C(UH )
(31) W
(30) V
VB
VC C
OUT
COM
(11) IN (U H )
IN
VS
(14) V S(U )
(29) U
(10) R SC
(9) C SC
C (S C )
(8) C FO D
C (F O D )
(7) V FO
VF O
O U T (W L)
(28) N W
(6) C O M (L)
(5) IN (W L)
IN (W L)
(4) IN (VL)
IN (V L)
(3) IN (U L)
IN (U L)
(2) C O M (L)
C O M (L)
(1) V C C(L)
VC C
O U T (V L)
(27) N V
O U T (U L)
(26) N U
(25) N C
(24) N C
Note:
1) Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and
protection functions.
2) Inverter power side is composed of four inverter dc-link input pins and three inverter output pins.
3) Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
Fig. 3.
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
(TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Item
Supply Voltage
Supply Voltage (Surge)
Collector-Emitter Voltage
Symbol
VPN
Condition
Applied between P- NU, NV, NW
Rating
450
Unit
V
VPN(Surge)
Applied between P- NU, NV, NW
500
V
600
V
A
VCES
Each IGBT Collector Current
± IC
TC = 25°C
30
Each IGBT Collector Current
± IC
TC = 100°C
15
A
Each IGBT Collector Current (Peak)
± ICP
TC = 25°C,
Instantaneous Value (Pulse)
60
A
Collector Dissipation
PC
TC = 25°C per One Chip
Operating Junction Temperature
TJ
(Note 1)
62
W
-20 ~ 125
°C
Note:
1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation.
Control Part
Item
Control Supply Voltage
Symbol
Condition
VCC
Applied between VCC(UH), VCC(VH), VCC(WH) - COM(H),
VCC(L) - COM(L)
Rating
20
Unit
V
20
V
V
High-side Control Bias Voltage
VBS
Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W)
Input Signal Voltage
VIN
Applied between IN(UH), IN(VH), IN(WH) - COM(H)
IN(UL), IN(VL), IN(WL) - COM(L)
-0.3 ~ VCC+0.3
Fault Output Supply Voltage
VFO
Applied between VFO - COM(L)
-0.3 ~ VCC+0.3
V
Fault Output Current
IFO
Sink Current at VFO Pin
5
mA
Current Sensing Input Voltage
VSC
Applied between CSC - COM(L)
-0.3 ~ VCC+0.3
V
Total System
Item
Self Protection Supply Voltage Limit
(Short-Circuit Protection Capability)
Module Case Operation Temperature
Symbol
Condition
VPN(PROT) VCC = VBS = 13.5 ~ 16.5V
TJ = 25°C, Non-repetitive, less than 6µs
TC
Storage Temperature
TSTG
Isolation Voltage
VISO
©2003 Fairchild Semiconductor Corporation
Note Fig.2
60Hz, Sinusoidal, AC 1 minute, Connection
Pins to Heat-sink Plate
Rating
400
Unit
V
-20 ~ 100
°C
-20 ~ 125
°C
2500
Vrms
Rev. E, August 2003
FSBM30SH60A
Absolute Maximum Ratings
Thermal Resistance
Item
Junction to Case Thermal
Resistance
Contact Thermal
Resistance
Symbol
Condition
Rth(j-c)Q Each IGBT under Inverter Operating Condition
Min. Typ.
-
Max.
2.0
Unit
°C/W
Rth(j-c)F
Each FWDi under Inverter Operating Condition
-
-
3.2
°C/W
Rth(c-f)
Ceramic Substrate (per 1 Module)
Thermal Grease Applied (Note 3)
-
-
0.06
°C/W
Typ.
-
Max.
2.5
Unit
V
Note:
2. For the measurement point of case temperature(TC), please refer to Fig. 2.
3. The thickness of thermal grease should not be more than 100um.
Electrical Characteristics
(TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Item
Collector - Emitter
Saturation Voltage
Symbol
VCE(SAT) VCC = VBS = 15V
VIN = 0V
Condition
IC = 30A, TJ = 25°C
Min.
-
FWDi Forward Voltage
VFM
VIN = 5V
-
-
2.6
V
Switching Times
tON
VPN = 300V, VCC = VBS = 15V
IC = 30A, TJ = 25°C
VIN = 5V ↔ 0V, Inductive Load
(High, Low-side)
-
0.39
-
us
(Note 4)
VCE = VCES, TJ = 25°C
tC(ON)
tOFF
tC(OFF)
trr
Collector - Emitter
Leakage Current
ICES
IC = 30A, TJ = 25°C
-
0.2
-
us
-
0.85
-
us
-
0.24
-
us
-
0.13
-
us
-
-
250
µA
Note:
4. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition
internally. For the detailed information, please see Fig. 4.
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Absolute Maximum Ratings
1 0 0 % IC
VCE
IC
IC
V IN
V IN (O N )
FSBM30SH60A
t rr
VCE
V IN
t ON
t
C (O N )
t OFF
tC(OFF)
V IN(OFF)
(a) Turn-on
(b) Turn-off
Fig. 4. Switching Time Definition
VCE : 100V/div.
IC : 10A/div.
time : 0.1us/div.
(a)(a)
Turn-on
turn-on
IC : 10A/div.
VCE : 100V/div.
time : 0.1us/div.
(b)turn-off
Turn-off
(b)
Fig. 5. Experimental Results of Switching Waveforms
Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), TJ=25°°C
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
Control Part (TJ = 25°C, Unless Otherwise Specified)
Item
Symbol
Quiescent VCC Supply Cur- IQCCL VCC = 15V
rent
IN(UL, VL, WL) = 5V
IQCCH VCC = 15V
IN(UH, VH, WH) = 5V
Condition
VCC(L) - COM(L)
VCC(UH), VCC(VH), VCC(WH) COM(H)
-
-
130
uA
Quiescent VBS Supply Current
IQBS
VBS = 15V
IN(UH, VH, WH) = 5V
VB(U) - VS(U), VB(V) -VS(V),
VB(W) - VS(W)
-
-
420
uA
Fault Output Voltage
VFOH
VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up
4.5
-
-
V
VFOL
VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up
-
-
1.1
V
Short-Circuit Trip Level
Sensing Voltage
of IGBT Current
Supply Circuit UnderVoltage Protection
Fault OutputPulse Width
VSC(ref)
VSEN
Min.
-
Typ. Max. Unit
26
mA
VCC = 15V (Note 5)
0.45
0.51 0.56
V
RSC = 50 Ω, RSU = RSV = RSW = 0 Ω and IC = 45A
(Note Fig. 6)
0.45
0.51 0.56
V
UVCCD
Detection Level
11.5
12
12.5
UVCCR
Reset Level
12
12.5
13
V
UVBSD
Detection Level
7.3
9.0
10.8
V
UVBSR
Reset Level
8.6
10.3
12
V
CFOD = 33nF (Note 6)
1.4
1.8
2.0
ms
tFOD
ON Threshold Voltage
VIN(ON)
OFF Threshold Voltage
VIN(OFF)
ON Threshold Voltage
VIN(ON)
OFF Threshold Voltage
VIN(OFF)
High-Side
Low-Side
V
Applied between IN(UH), IN(VH),
IN(WH) - COM(H)
-
-
0.8
V
3.0
-
-
V
Applied between IN(UL), IN(VL),
IN(WL) - COM(L)
-
-
0.8
V
3.0
-
-
V
Note:
5. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be
selected around 50 Ω in order to make the SC trip-level of about 45A at the shunt resistors (RSU,RSV,RSW) of 0Ω . For the detailed information about the
relationship between the external sensing resistor (RSC) and the shunt resistors (RSU,RSV,RSW), please see Fig. 6.
6. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F]
Recommended Operating Conditions
Item
Symbol
Condition
Values
Min.
-
Typ.
300
Max.
400
Unit
Supply Voltage
VPN
Applied between P - NU, NV, NW
Control Supply Voltage
VCC
Applied between VCC(UH), VCC(VH), VCC(WH) COM(H), VCC(L) - COM(L)
13.5
15
16.5
V
High-side Bias Voltage
VBS
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.5
15
16.5
V
Blanking Time for Preventing
Arm-short
tdead
For Each Input Signal
3
-
-
us
fPWM
TC ≤ 100°C, TJ ≤ 125°C
-
15
-
kHz
PWM Input Signal
V
Input ON Threshold Voltage
VIN(ON)
Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
0 ~ 0.65
V
Input OFF Threshold Voltage
VIN(OFF)
Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
4 ~ 5.5
V
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Electrical Characteristics
FSBM30SH60A
100
80
(1)
(2)
RSC [Ω]
60
40
20
0
0.00
0.01
0.02
0.03
0.04
0.05
RSU,RSV,RSW [Ω]
Fig. 7. RSC Variation by change of Shunt Resistors (RSU, RSV, RSW) for Short-Circuit Protection
(1) @ around 100% Rated Current Trip (IC ·=· 30A)
(2) @ around 150% Rated Current Trip (IC ·=· 45A)
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
Item
Mounting Torque
Limits
Condition
Mounting Screw: M4
(Note 7 and 8)
Ceramic Flatness
Unit
Recommended 10Kg•cm
Min.
8
Typ.
10
Max.
12
Kg•cm
Recommended 0.98N•m
0.78
0.98
1.17
N•m
0
-
+120
um
-
35
-
g
Note Fig.7
Weight
(+)
(+)
(+)
Datum Line
Fig. 7. Flatness Measurement Position of The Ceramic Substrate
Note:
7. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction.
8. Avoid one side tightening stress. Fig.8 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to
be damaged.
2
1
Fig. 8. Mounting Screws Torque Order
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Mechanical Characteristics and Ratings
FSBM30SH60A
Time Charts of SPMs Protective Function
Input Signal
Internal IGBT
Gate-Emitter Voltage
P3
Control Supply Voltage
P2
P5
UV detect
UV reset
P6
P1
Output Current
P4
Fault Output Signal
P1 : Normal operation - IGBT ON and conducting current
P2 : Under-Voltage detection
P3 : IGBT gate interrupt
P4 : Fault signal generation
P5 : Under-Voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 9. Under-Voltage Protection (Low-side)
Input Signal
P3
P5
VBS
UV detect
UV reset
P2
P6
P1
Output Current
Fault Output Signal
P4
P1 : Normal operation - IGBT ON and conducting current
P2 : Under-Voltage detection
P3 : IGBT gate interrupt
P4 : No fault signal
P5 : Under-Voltage reset
P6 : Normal operation - IGBT ON and conducting current
Fig. 10. Under-Voltage Protection (High-side)
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
P5
Input Signal
P6
Internal IGBT
Gate-Em itter Voltage
SC Detection
P1
P4
P7
Output Current
P2
SC Reference
Voltage (0.5V)
Sensing Voltage
RC Filter Delay
Fault Output Signal
P3
P8
P1 : Normal operation - IGBT ON and conducting current
P2 : Short-Circuit current detection
P3 : IGBT gate interrupt / Fault signal generation
P4 : IGBT is slowly turned off
P5 : IGBT OFF signal
P6 : IGBT ON signal - but IGBT cannot be turned on during the fault Output activation
P7 : IGBT OFF state
P8 : Fault Output reset and normal operation start
Fig. 11. Short-Circuit Current Protection (Low-side Operation only)
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
5V-Line
SPM
RPF
RPL
RPH
4.7k Ω
2k Ω
4.7k Ω
100 Ω
IN (UH) , IN (VH) , IN(WH)
100 Ω
CPU
IN (UL) , IN (VL) , IN (WL)
100 Ω
VFO
CPF
1nF
1nF
C PL
CPH
0.47nF
1.2nF
CO M
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins
and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to
each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
These Values depend on PW M C ontrol Algorithm
One-Leg Diagram of SPM
15V-Line
20 Ω
P
DBS
47uF
0.1uF
Vcc
VB
IN
HO
COM VS
Inverter
Output
Vcc
470uF
0.1uF
IN
OUT
COM
N
Note:
It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
15V line
5V line
R BS
DBS
(22) V B(W)
(21) V CC(W H)
R PH
RS
C BS
G ating W H
C B SC
(20) IN (W H)
(23) V S(W)
CPH
R BS
DBS
(18) V B(V)
(17) V CC(VH)
G ating VH
R PH
RS
(16) C OM (H)
CBS
CBSC
(19) V S(V)
CPH
C
P
U
(15) IN (VH)
DBS
R BS
(13) V B(U)
(12) V CC(UH)
RPH
RS
C BS
G ating U H
C PH
C B SC
(14) V S(U)
R SC
5V line
RF
RS
RPL
RPL R PL RPF
G ating W H
G ating VH
G ating U H
(9) C SC
(8) C FOD
C FO D
(7) V FO
(6) C OM (L)
RS
(5) IN (W L)
RS
(4) IN (VL)
RS
(3) IN (UL)
(2) C OM (L)
C B PF
CPL CPL
C PL
CPF
(1) V CC(L)
CSP15
VCC
O UT
C OM
IN
W (31)
VS
VB
VCC
O UT
C OM
IN
VS
V (30)
M
VB
VCC
C D CS
O UT
Vdc
C OM
IN
U (29)
VS
(10) R SC
R C SC
CSC
Fault
(11) IN (UH)
P (32)
VB
C (SC )
O UT(W L)
C (FO D)
N W (28)
R SW
VFO
IN (WL) O UT(VL)
IN (VL)
N V (27)
R SV
IN (UL)
C OM(L)
O UT(UL)
VCC
N U (26)
CSPC15
RSU
N C (24)
N C (25)
R FW
W -Phase C urrent
V-Phase Current
R FV
R FU
U -Phase C urrent
C FW
C FV
C FU
Note:
1) RPLCPL/RPHCPH /RPFCPF coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each
SPM input pin.
2) By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
possible.
3) VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please
refer to Fig. 14.
4) CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended.
5) VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin8) and COM(L)(pin2). (Example : if CFOD = 33 nF, then
tFO = 1.8 ms (typ.)) Please refer to the note 6 for calculation method.
6) Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ (at high side input) or 2kΩ (at low side input) resistance (other RC
coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board).
Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals.
7) To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.
8) In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 µs.
9) To enhance the noise immunity, CSC pin should be connected to the external circuit through a series resistor, RCSC, which is approximately 390Ω. RSCS should
be connected to CSC pin as close as possible.
10)Each capacitor should be mounted as close to the pins of the SPM as possible.
11)To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noinductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended.
12)Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and
the relays. It is recommended that the distance be 5cm at least.
Fig. 14. Typical Application Circuit
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
FSBM30SH60A
Detailed Package Outline Drawings
SPM32-AA
28x2.00 ±0.30=(56.0)
(2.00)
MAX1.05
MAX1.00
2.00 ±0.30
0.60 ±0.10
0.60 ±0.10
0.40
0.40
28.0 ±0.30
#23
36.05 ±0.50
Ø4.30
(34.80)
31.0 ±0.50
13.6 ±0.30
(3.30)
+0.10
#24
19.86±0.30
0.70 -0.05
#32
°)
(3° ~5
(17.00)
#1
7.20 ±0.5
(46.60)
12.30 ±0.5
53.0 ±0.30
60.0 ±0.50
3x7.62 ±0.30=(22.86)
3x4.0 ±0.30=(12.0 )
11.0 ±0.30
(3.70)
2.00 ±0.30
(3.50)
MAX1.00
MAX8.20
(10.14)
0.80
0.80
1.30±0.10
1.30±0.10
0.40
0.60±0.10
MAX3.20
MAX2.50
MAX1.60
Dimensions in Millimeters
©2003 Fairchild Semiconductor Corporation
Rev. E, August 2003
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effectiveness.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
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Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
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First Production
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supplementary data will be published at a later date.
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Rev. I5