AD AD5685R Quad, 16-/14-/12-bit nanodac Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
VDD
GND
VREF
AD5686R/AD5685R/AD5684R
VLOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
SCLK
SYNC
SDIN
SDO
VOUTA
BUFFER
INTERFACE LOGIC
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
2.5V
REFERENCE
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTB
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
VOUTC
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
VOUTD
BUFFER
LDAC RESET
POWER-ON
RESET
GAIN
×1/×2
RSTSEL
GAIN
POWERDOWN
LOGIC
10485-001
Data Sheet
Quad, 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
AD5686R/AD5685R/AD5684R
Figure 1.
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5686R/AD5685R/AD5684R, members of the
nanoDAC+® family, are low power, quad, 16-/14-/12-bit
buffered voltage output DACs. The devices include a 2.5 V,
2 ppm/°C internal reference (enabled by default) and a gain
select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V
(gain = 2). All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and exhibit less
than 0.1% FSR gain error and 1.5 mV offset error performance.
The devices are available in a 3 mm × 3 mm LFCSP and a
TSSOP package.
The AD5686R/AD5685R/AD5684R also incorporate a poweron reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remains there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 μA at 3 V while in power-down mode.
Table 1. Quad nanoDAC+ Devices
Interface
SPI
I2C
Reference
Internal
Internal
16-Bit
AD5686R
AD5696R
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5694R
PRODUCT HIGHLIGHTS
1.
2.
3.
High Relative Accuracy (INL).
AD5686R (16-bit): ±2 LSB maximum
AD5685R (14-bit): ±1 LSB maximum
AD5684R (12-bit): ±1 LSB maximum
Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
The AD5686R/AD5685R/AD5684R employ a versatile SPI
interface that operates at clock rates up to 50 MHz, and all
devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD5686R/AD5685R/AD5684R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Write and Update Commands .................................................. 22
Applications ....................................................................................... 1
Daisy-Chain Operation ............................................................. 23
Functional Block Diagram .............................................................. 1
Readback Operation .................................................................. 23
General Description ......................................................................... 1
Power-Down Operation ............................................................ 24
Product Highlights ........................................................................... 1
Load DAC (Hardware LDAC Pin) ........................................... 25
Revision History ............................................................................... 2
LDAC Mask Register ................................................................. 25
Specifications..................................................................................... 3
Hardware Reset (RESET) .......................................................... 26
AC Characteristics........................................................................ 5
Reset Select Pin (RSTSEL) ........................................................ 26
Timing Characteristics ................................................................ 6
Internal Reference Setup ........................................................... 26
Daisy-Chain and Readback Timing Characteristics ............... 7
Solder Heat Reflow..................................................................... 26
Absolute Maximum Ratings............................................................ 9
Long-Term Temperature Drift ................................................. 26
ESD Caution .................................................................................. 9
Thermal Hysteresis .................................................................... 27
Pin Configuration and Function Descriptions ........................... 10
Applications Information .............................................................. 28
Typical Performance Characteristics ........................................... 11
Microprocessor Interfacing ....................................................... 28
Terminology .................................................................................... 18
AD5686R/AD5685R/AD5684R to ADSP-BF531 Interface.. 28
Theory of Operation ...................................................................... 20
AD5686R/AD5685R/AD5684R to SPORT Interface ............ 28
Digital-to-Analog Converter .................................................... 20
Layout Guidelines....................................................................... 28
Transfer Function ....................................................................... 20
Galvanically Isolated Interface ................................................. 29
DAC Architecture ....................................................................... 20
Outline Dimensions ....................................................................... 30
Serial Interface ............................................................................ 21
Ordering Guide .......................................................................... 31
Standalone Operation ................................................................ 22
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE 2
AD5686R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5685R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5684R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Min
A Grade 1
Typ
Max
16
Min
B Grade1
Typ
Max
16
±2
±2
±8
±8
±1
14
±1
±1
±2
±3
±1
14
±0.5
±4
±1
12
±0.5
±1
±1
12
Bits
LSB
Test Conditions/Comments
LSB
Gain = 2
Gain = 1
Guaranteed monotonic by design
Bits
LSB
LSB
Guaranteed monotonic by design
±1
±1
Bits
LSB
LSB
mV
mV
% of
FSR
% of
FSR
% of
FSR
% of
FSR
µV/°C
±1
±1
ppm
Of FSR/°C
0.15
0.15
mV/V
DAC code = midscale; VDD = 5 V ± 10%
±2
±2
µV
±3
±2
±3
±2
µV/mA
µV
Due to single channel, full-scale
output change
Due to load current change
Due to powering down (per channel)
±0.12
0.4
+0.1
+0.01
±2
±1
4
±4
±0.2
0.4
+0.1
+0.01
±1
±1
1.5
±1.5
±0.1
Gain Error
±0.02
±0.2
±0.02
±0.1
Total Unadjusted Error
±0.01
±0.25
±0.01
±0.1
±0.12
±0.25
Offset Error Drift3
Gain Temperature
Coefficient3
DC Power Supply Rejection
Ratio3
Unit
±0.2
Guaranteed monotonic by design
All zeros loaded to DAC register
All ones loaded to DAC register
External reference; gain = 2; TSSOP
Internal reference; gain = 1; TSSOP
DC Crosstalk3
OUTPUT CHARACTERISTICS 3
Output Voltage Range
0
0
Capacitive Load Stability
Resistive Load 4
Load Regulation
Short-Circuit Current 5
Load Impedance at Rails 6
Power-Up Time
VREF
2 × VREF
0
0
80
80
V
V
nF
nF
kΩ
µV/mA
80
80
µV/mA
40
25
2.5
40
25
2.5
mA
Ω
µs
2
10
1
VREF
2 × VREF
2
10
1
Rev. 0 | Page 3 of 32
Gain = 1
Gain = 2, see Figure 34
RL = ∞
RL = 1 kΩ
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
See Figure 34
Coming out of power-down mode;
VDD = 5 V
AD5686R/AD5685R/AD5684R
Parameter
REFERENCE OUTPUT
Output Voltage 7
Reference TC 8, 9
Output Impedance3
Min
Data Sheet
A Grade 1
Typ
Max
2.4975
5
0.04
2.5025
20
Min
B Grade1
Typ
Max
2.4975
2
0.04
2.5025
5
Unit
Test Conditions/Comments
V
ppm/°C
Ω
At ambient
See the Terminology section
Output Voltage Noise3
Output Voltage Noise
Density3
12
12
240
µV p-p
nV/√Hz
0.1 Hz to 10 Hz
240
Load Regulation Sourcing3
20
20
µV/mA
At ambient
Load Regulation Sinking3
Output Current Load
Capability3
40
40
At ambient
±5
±5
µV/mA
mA
Line Regulation3
3
Long-Term Stability/Drift
3
Thermal Hysteresis
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
VDD
IDD
Normal Mode 10
All Power-Down
Modes 11
At ambient; f = 10 kHz, CL = 10 nF
VDD ≥ 3 V
100
100
µV/V
At ambient
12
12
ppm
After 1000 hours at 125°C
125
125
ppm
First cycle
25
25
ppm
Additional cycles
±2
0.3 × VLOGIC
µA
V
V
pF
Per pin
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
5.5
3
5.5
5.5
V
µA
V
V
0.7
1.3
4
mA
mA
µA
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
6
µA
−40°C to +105°C
±2
0.3 × VLOGIC
0.7 × VLOGIC
0.7 × VLOGIC
2
2
0.4
VLOGIC − 0.4
VLOGIC − 0.4
4
1.8
4
5.5
3
5.5
5.5
2.7
VREF + 1.5
0.59
1.1
1
0.7
1.3
4
1.8
2.7
VREF + 1.5
0.59
1.1
1
6
Temperature range: A and B grade: −40°C to +105°C.
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686R), 64 to 16,320 (AD5685R), and 12 to 4080 (AD5684R).
3
Guaranteed by design and characterization; not production tested.
4
Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5
VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 34).
7
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
8
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
9
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
10
Interface inactive. All DACs active. DAC outputs unloaded.
11
All DACs powered down.
1
2
Rev. 0 | Page 4 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted. 1
Table 3.
Parameter 2
Output Voltage Settling Time
AD5686R
AD5685R
AD5684R
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion 4
Output Noise Spectral Density
Output Noise
SNR
SFDR
SINAD
Min
Typ
Max
Unit
Test Conditions/Comments 3
5
5
5
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
90
83
80
8
8
7
µs
µs
µs
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
Guaranteed by design and characterization, not production tested.
See the Terminology section.
3
Temperature range is −40°C to +105°C, typical @ 25°C.
4
Digitally generated sine wave @ 1 kHz.
1
2
Rev. 0 | Page 5 of 32
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
AD5686R/AD5685R/AD5684R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time 2
2
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t6
t5
SDIN
DB23
DB0
t12
t10
LDAC1
t11
LDAC2
RESET
VOUT
t13
t14
10485-002
1
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
5
5
15
20
16
25
30
20
30
30
4.5
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 32
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Data Sheet
AD5686R/AD5685R/AD5684R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
Min
40
20
20
20
5
5
10
30
30
2.7 V ≤ VLOGIC ≤ 5.5 V
Max
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t115
15
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNC Rising Edge to SCLK Rising Edge
t125
15
10
ns
1
Min
66
33
33
33
5
5
15
60
60
1.8 V ≤ VLOGIC < 2.7 V
Max
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
36
25
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
VOH (MIN)
CL
20pF
200µA
10485-003
TO OUTPUT
PIN
IOL
IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDIN
t6
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t10
INPUT WORD FOR DAC N + 1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 32
10485-004
t5
AD5686R/AD5685R/AD5684R
Data Sheet
t1
SCLK
24
1
t8
t4
t3
24
1
t7
t2
t9
SYNC
t6
t5
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
NOP CONDITION
t10
DB0
DB23
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. 0 | Page 8 of 32
10485-005
SDIN
Data Sheet
AD5686R/AD5685R/AD5684R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free (J-STD-020)
ESD 1
FICDM
1
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
112.6°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
70°C/W
260°C
4 kV
1.5 kV
Human body model (HBM) classification.
Rev. 0 | Page 9 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 RESET
14 RSTSEL
16 VOUTB
15 VREF
AD5686R/AD5685R/AD5684R
VOUTA 1
12 SDIN
11 SYNC
VDD 3
10 SCLK
9 VLOGIC
10485-006
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
GND 4
AD5686R/
AD5685R/
AD5684R
VDD 5
TOP VIEW
(Not to Scale)
VOUTA 3
GAIN 8
LDAC 7
SDO 6
VOUTD 5
VOUTC 4
16 RSTSEL
VREF 1
VOUTB 2
Figure 6. 16-Lead LFCSP Pin Configuration
15
RESET
14
SDIN
13
SYNC
12
SCLK
VOUTC 6
11
VLOGIC
VOUTD 7
10
GAIN
SDO 8
9
LDAC
10485-007
GND 2
Figure 7. 16-Lead TSSOP Pin Configuration
Table 6. Pin Function Descriptions
LFCSP
1
2
3
Pin No.
TSSOP
3
4
5
Mnemonic
VOUTA
GND
VDD
4
5
6
6
7
8
VOUTC
VOUTD
SDO
7
9
LDAC
8
10
GAIN
9
10
11
12
VLOGIC
SCLK
11
13
SYNC
12
14
SDIN
13
15
RESET
14
16
RSTSEL
15
1
VREF
16
17
2
N/A
VOUTB
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5686R/AD5685R/AD5684R devices
together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is
valid on the falling edge of the clock.
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to simultaneously update. This pin can also be tied permanently low.
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this
pin is tied to VDD, all four DACs output a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.
Reference Voltage. The AD5686R/AD5685R/AD5684R have a common reference pin. When using
the internal reference, this is the reference output pin. When using an external reference, this is the
reference input pin. The default for this pin is as a reference output.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 10 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
TYPICAL PERFORMANCE CHARACTERISTICS
2.5020
VDD = 5V
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
2.5015
2.5010
50
2.5005
40
HITS
VREF (V)
VDD = 5.5V
0 HOUR
168 HOURS
500 HOURS
1000 HOURS
60
2.5000
30
2.4995
20
2.4990
10
2.4985
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
2.498
1600
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
VDD = 5V
TA = 25°C
1200
1000
NSD (nV/ Hz)
2.5000
2.4995
800
600
400
2.4990
200
2.4985
VDD = 5V
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 9. Internal Reference Voltage vs. Temperature (Grade A)
90
0
10
10485-109
–20
100
1k
10k
100k
1M
FREQUENCY (MHz)
Figure 12. Internal Reference Noise Spectral Density vs. Frequency
VDD = 5V
VDD = 5V
TA = 25°C
80
T
60
50
1
40
30
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TEMPERATURE DRIFT (ppm/°C)
5.0
CH1 10µV
M1.0s
A CH1
160mV
Figure 13. Internal Reference Noise, 0.1 Hz to 10 Hz
Figure 10. Reference Output Temperature Drift Histogram
Rev. 0 | Page 11 of 32
10485-112
10
10485-250
NUMBER OF UNITS
70
10485-111
VREF (V)
2.502
1400
2.5005
2.4980
–40
2.501
Figure 11. Reference Long-Term Stability/Drift
2.5020
2.5010
2.500
VREF (V)
Figure 8. Internal Reference Voltage vs. Temperature (Grade B)
2.5015
2.499
10485-251
–20
10485-212
2.4980
–40
AD5686R/AD5685R/AD5684R
Data Sheet
2.5000
10
VDD = 5V
TA = 25°C
8
2.4999
6
4
2.4997
2
INL (LSB)
VREF (V)
2.4998
2.4996
0
–2
–4
2.4995
–6
2.4994
–0.003
–0.001
0.001
0.003
–10
10485-113
2.4993
–0.005
0.005
ILOAD (A)
0
2500
7500
10000
12500
15000 16348
3125
3750 4096
CODE
Figure 17. AD5685R INL
Figure 14. Internal Reference Voltage vs. Load Current
2.5002
5000
10485-119
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–8
10
TA = 25°C
D1
8
2.5000
6
4
D3
INL (LSB)
VREF (V)
2.4998
2.4996
2
0
–2
2.4994
–4
–6
D2
3.5
4.0
4.5
5.0
5.5
VDD (V)
–10
0
625
0.8
6
0.6
4
0.4
2
0.2
DNL (LSB)
8
0
–2
0
–0.2
–4
–0.4
–6
–0.6
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.8
CODE
60000
10485-118
INL (LSB)
1.0
50000
2500
Figure 18. AD5684R INL
10
40000
1875
CODE
Figure 15. Internal Reference Voltage vs. Supply Voltage
V = 5V
–8 DD
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
0
10000
20000
30000
1250
–1.0
0
10000
20000
30000
40000
CODE
Figure 19. AD5686R DNL
Figure 16. AD5686R INL
Rev. 0 | Page 12 of 32
50000
60000
10485-121
3.0
10485-117
2.4990
2.5
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–8
10485-120
2.4992
AD5686R/AD5685R/AD5684R
10
0.8
8
0.6
6
0.4
4
0.2
0
–0.2
2
–4
–0.6
–6
V = 5V
–0.8 DD
TA = 25°C
INTERNAL REFERENCE = 2.5V
–1.0
0
2500
5000
7500
–8
12500
15000 16383
CODE
DNL
–2
–0.4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
0
0.5
8
0.6
6
0.4
4
ERROR (LSB)
0.8
0.2
0
–0.2
3.5
4.0
4.5
5.0
–2
–6
–8
3125
3750 4096
INL
DNL
–0.6
CODE
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
Figure 24. INL Error and DNL Error vs. Supply Voltage
Figure 21. AD5684R DNL
0.10
8
0.08
6
0.06
4
0.04
ERROR (% of FSR)
10
INL
0
DNL
–2
–4
–6
0.02
0
FULL-SCALE ERROR
GAIN ERROR
–0.02
–0.04
–10
–40
10
60
110
TEMPERATURE (°C)
Figure 22. INL Error and DNL Error vs. Temperature
VDD = 5V
–0.08 T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 25. Gain Error and Full-Scale Error vs. Temperature
Rev. 0 | Page 13 of 32
10485-127
–0.06
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
10485-124
ERROR (LSB)
3.0
0
–4
–8
2.5
2
–0.4
10485-123
DNL (LSB)
10
2
2.0
Figure 23. INL Error and DNL Error vs. VREF
1.0
2500
1.5
VREF (V)
Figure 20. AD5685R DNL
VDD = 5V
–0.8
TA = 25°C
INTERNAL REFERENCE = 2.5V
–1.0
0
625
1250
1875
1.0
10485-126
10000
INL
0
10485-125
ERROR (LSB)
1.0
10485-122
DNL (LSB)
Data Sheet
AD5686R/AD5685R/AD5684R
Data Sheet
0.10
1.2
0.8
0.6
0.4
ZERO-CODE ERROR
0.2
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0.06
0.05
0.04
0.03
0.02
0.01
0
–40
10485-128
OFFSET ERROR
0
–40
0.07
0.08
0.08
TOTAL UNADJUSTED ERROR (% of FSR)
0.10
ERROR (% of FSR)
0.06
0.04
0.02
GAIN ERROR
0
FULL-SCALE ERROR
–0.04
4.7
5.2
10485-129
–0.06
SUPPLY VOLTAGE (V)
20
40
60
80
100
120
Figure 29. TUE vs. Temperature
0.10
VDD = 5V
–0.08 T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
4.2
0
TEMPERATURE (°C)
Figure 26. Zero-Code Error and Offset Error vs. Temperature
–0.02
–20
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
V = 5V
–0.08 T DD= 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
10485-132
ERROR (mV)
1.0
VDD = 5V
0.09 TA = 25°C
INTERNAL REFERENCE = 2.5V
0.08
10485-131
TOTAL UNADJUSTED ERROR (% of FSR)
VDD = 5V
1.4 T = 25°C
A
INTERNAL REFERENCE = 2.5V
Figure 30. TUE vs. Supply, Gain = 1
Figure 27. Gain Error and Full-Scale Error vs. Supply
1.5
0
ZERO-CODE ERROR
0
OFFSET ERROR
–0.5
–1.0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–1.5
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
10485-130
ERROR (mV)
0.5
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
VDD = 5V
–0.09 T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.10
0
10000
20000
30000
40000
CODE
Figure 28. Zero-Code Error and Offset Error vs. Supply
Figure 31. TUE vs. Code
Rev. 0 | Page 14 of 32
50000
60000 65535
10485-133
TOTAL UNADJUSTED ERROR (% of FSR)
1.0
Data Sheet
AD5686R/AD5685R/AD5684R
7
VDD = 5V
TA = 25°C
EXTERNAL
REFERENCE = 2.5V
25
VDD = 5V
6 TA = 25°C
GAIN = 2
INTERNAL
5 REFERENCE = 2.5V
20
0xFFFF
VOUT (V)
HITS
4
15
0xC000
3
0x8000
2
0x4000
10
1
0x0000
0
5
560
580
600
620
640
IDD (V)
–2
–0.06
10485-135
540
–0.04
–0.02
Figure 32. IDD Histogram with External Reference, 5 V
0.02
0.04
0.06
Figure 35. Source and Sink Capability at 5 V
5
VDD = 5V
30 T = 25°C
A
INTERNAL
REFERENCE = 2.5V
25
VDD = 5V
TA = 25°C
4 EXTERNAL REFERENCE = 2.5V
GAIN = 1
0xFFFF
3
0xC000
VOUT (V)
20
HITS
0
LOAD CURRENT (A)
10485-138
–1
0
15
2
0x8000
1
0x4000
10
0
5
0x0000
1000
1020
1040
1060
1080
1100
1120
1140
IDD FULLSCALE (V)
–2
–0.06
10485-136
0
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
10485-139
–1
Figure 36. Source and Sink Capability at 3 V
Figure 33. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2
1.0
1.4
0.8
0.6
1.2
0.4
CURRENT (mA)
SINKING 5V
0
–0.2
1.0
ZERO CODE
0.8
EXTERNAL REFERENCE, FULL-SCALE
0.6
SOURCING 5V
–0.4
0.4
–0.6
SOURCING 2.7V
–1.0
0
5
10
15
20
25
LOAD CURRENT (mA)
30
0
–40
10
60
TEMPERATURE (°C)
Figure 37. Supply Current vs. Temperature
Figure 34. Headroom/Footroom vs. Load Current
Rev. 0 | Page 15 of 32
110
10485-140
0.2
–0.8
10485-200
ΔVOUT (V)
SINKING 2.7V
0.2
FULL-SCALE
AD5686R/AD5685R/AD5684R
Data Sheet
2.5008
4.0
DAC A
DAC B
DAC C
DAC D
3.5
2.5003
3.0
VOUT (V)
VOUT (V)
2.5
2.0
2.4998
1.5
80
160
2.4988
10485-141
VDD = 5V
0.5 TA = 25°C
INTERNAL REFERENCE = 2.5V
¼ TO ¾ SCALE
0
10
20
40
320
TIME (µs)
0
6
8
10
12
Figure 41. Digital-to-Analog Glitch Impulse
0.06
6
CH A
CH B
CH C
CH D
VDD
0.003
CH B
CH C
CH D
5
4
0.03
3
0.02
2
0.01
1
0
0
VOUT AC-COUPLED (V)
0.002
0.04
VDD (V)
VOUT (V)
4
TIME (µs)
Figure 38. Settling Time, 5.25 V
0.05
2
10485-144
CHANNEL B
TA = 25°C
VDD = 5.25V
INTERNAL REFERENCE
CODE = 7FFF TO 8000
ENERGY = 0.227206nV-sec
2.4993
1.0
0.001
0
–0.001
10
–1
15
TIME (µs)
–0.002
0
5
10
15
20
10485-145
5
10485-142
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.01
–10
–5
0
25
TIME (µs)
Figure 39. Power-On Reset to 0 V
Figure 42. Analog Crosstalk, Channel A
3
CH A
CH B
CH C
CH D
SYNC
T
GAIN = 2
VOUT (V)
2
GAIN = 1
1
0
5
TIME (µs)
10
10485-143
0
–5
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
Figure 40. Exiting Power-Down to Midscale
VDD = 5V
TA = 25°C
EXTERNAL REFERENCE = 2.5V
CH1 10µV
M1.0s
A CH1
802mV
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Rev. 0 | Page 16 of 32
10485-146
1
Data Sheet
AD5686R/AD5685R/AD5684R
4.0
0nF
0.1nF
10nF
0.22nF
4.7nF
3.9
T
3.8
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
VOUT (V)
3.7
1
3.6
3.5
3.4
3.3
3.2
M1.0s
A CH1
10485-147
CH1 10µV
3.0
1.590
802mV
1.595
1.600
1.605
1.610
1.615
1.620
1.625
1.630
TIME (ms)
10485-150
3.1
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
Figure 47. Settling Time vs. Capacitive Load
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
0
1600
VDD = 5V
TA = 25°C
1400 INTERNAL REFERENCE = 2.5V
FULL-SCALE
MIDSCALE
ZERO-SCALE
–10
1000
800
600
400
1k
10k
100k
1M
FREQUENCY (Hz)
10485-148
100
Figure 45. Noise Spectral Density
20
–80
–100
–120
–140
–160
FREQUENCY (Hz)
10485-149
THD (dBV)
–60
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
100k
1M
10M
Figure 48. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p,
10 kHz to 10 MHz
–40
–180
VDD = 5V
TA = 25°C
EXTERNAL REFERENCE = 2.5V, ±0.1V p-p
FREQUENCY (Hz)
–20
0
–40
–60
10k
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0
–30
–50
200
0
10
–20
10485-151
BANDWIDTH (dB)
NSD (nV/ Hz)
1200
Figure 46. Total Harmonic Distortion @ 1 kHz
Rev. 0 | Page 17 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 16.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 19.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5686R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 26.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 25.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from the ideal
expressed as % of FSR.
Offset Error Drift
This is a measurement of the change in offset error with a
change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5686R
with Code 512 loaded in the DAC register. It can be negative
or positive.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the rising edge of SYNC.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 41).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density is shown in Figure 45.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-sec.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%.
Rev. 0 | Page 18 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The
energy of the glitch is expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Voltage Reference TC
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows;
 VREFmax − VREFmin 
6
TC = 
 × 10
V
TempRange
×
 REFnom

where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range of −40°C to
+105°C.
Rev. 0 | Page 19 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
VREF
The AD5686R/AD5685R/AD5684R are quad 16-/14-/12-bit,
serial input, voltage output DACs with an internal reference.
The parts operate from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5686R/AD5685R/AD5684R in a 24-bit word
format via a 3-wire serial interface. The AD5686R/AD5685R/
AD5684R incorporate a power-on reset circuit to ensure that the
DAC output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
R
R
R
TRANSFER FUNCTION
R
The internal reference is on by default. To use an external
reference, only a nonreference option is available. Because the
input coding to the DAC is straight binary, the ideal output
voltage when using an external reference is given by
10485-053
Internal Reference
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
0 to 4,095 for the 12-bit device.
0 to 16,383 for the 14-bit device.
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
Gain is the gain of the output amplifier and is set to 1 by default.
This can be set to ×1 or ×2 using the gain select pin. When this
pin is tied to GND, all four DAC outputs have a span from 0 V
to VREF. If this pin is tied to VDD, all four DACs output a span of
0 V to 2 × VREF.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 49 shows a block diagram of the DAC
architecture.
VREF
2.5V
REF
RESISTOR
STRING
REF (–)
VOUTX
GAIN
(GAIN = 1 OR 2)
The AD5686R/AD5685R/AD5684R have a 2.5 V, 2 ppm/°C
reference, giving a full-scale output of 2.5 V or 5 V, depending
on the state of the GAIN pin. The internal reference associated
with the device is available at the VREF pin. This buffered
reference is capable of driving external loads of up to 10 mA.
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
•
•
10485-052
GND
The AD5686R/AD5685R/AD5684R on-chip reference is on at
power-up but can be disabled via a write to a control register.
See the Internal Reference Setup section for details.
If this pin is tied to GND, all four outputs have a gain of 1
and the output range is 0 V to VREF.
If this pin is tied to VLOGIC, all four outputs have a gain of 2
and the output range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
REF (+)
DAC
REGISTER
R
Figure 50. Resistor String Structure
D
VOUT = VREF × Gain  N 
 2 
INPUT
REGISTER
TO OUTPUT
AMPLIFIER
Figure 49. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 50. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. 0 | Page 20 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
SERIAL INTERFACE
Table 7. Command Definitions
The AD5686R/AD5685R/AD5684R have a 3-wire serial
interface (SYNC, SCLK, and SDIN) that is compatible with
SPI, QSPI, and MICROWIRE interface standards as well as
most DSPs. See Figure 2 for a timing diagram of a typical
write sequence. The AD5686R/AD5685R/AD5684R contain
an SDO pin to allow the user to daisy-chain multiple devices
together (see the Daisy-Chain Operation section) or for
readback.
C3
0
0
0
0
0
0
0
0
1
1
1
…
1
Input Shift Register
The input shift register of the AD5686R/AD5685R/AD5684R is
24 bits wide. Data is loaded MSB first (DB23) and the first four
bits are the command bits, C3 to C0 (see Table 7), followed by
the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D
(see Table 8), and finally the bit data-word.
The data-word comprises 16-bit, 14-bit, or 12-bit input code,
followed by zero, two or four don’t care bits for the AD5686R,
AD5685R, and AD5684R, respectively (see Figure 51, Figure 52,
and Figure 53). These data bits are transferred to the input
register on the 24 falling edges of SCLK and are updated on the
rising edge of SYNC.
Command
C2 C1
0
0
0
0
0
1
0
1
1
1
1
0
0
0
…
1
1
0
0
1
1
0
0
1
…
1
C0
0
1
0
1
0
1
0
1
0
1
0
…
1
Description
No operation
Write to Input Register n (dependent on LDAC)
Update DAC Register n with contents of Input
Register n
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference setup register
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
Reserved
Reserved
Table 8. Address Commands
DAC D
0
0
0
1
0
1
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected.
1
Address (n)
DAC C DAC B
0
0
0
1
1
0
0
0
0
1
1
1
DAC A
1
0
0
0
1
1
Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
C3
C2
Selected DAC Channel 1
DAC A
DAC B
DAC C
DAC D
DAC A and DAC B
All DACs
DB0 (LSB)
C1
C0 DAC DAC DAC DAC D15 D14 D13 D12 D11 D10
D
C
B
A
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND BITS
10485-054
DATA BITS
ADDRESS BITS
Figure 51. AD5686R Input Shift Register Content
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0 DAC DAC DAC DAC D13 D12 D11 D10
D
C
B
A
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
COMMAND BITS
10485-055
DATA BITS
ADDRESS BITS
Figure 52. AD5685R Input Shift Register Content
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0
DAC DAC DAC DAC D11 D10
D
C
B
A
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
10485-056
DATA BITS
ADDRESS BITS
Figure 53. AD5684R Input Shift Register Content
Rev. 0 | Page 21 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
STANDALONE OPERATION
WRITE AND UPDATE COMMANDS
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
clocked in, SYNC should be brought high. The programmed
function is then executed, that is, an LDAC-dependent change
in DAC register contents and/or a change in the mode of
operation. If SYNC is taken high at a clock before the 24th clock,
it is considered a valid frame and invalid data may be loaded to
the DAC. SYNC must be brought high for a minimum of
20 ns (single channel, see t8 in Figure 2) before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. SYNC should be idled at rails between write
sequences for even lower power operation of the part.
The SYNC line is kept low for 24 falling edges of SCLK, and the
DAC is updated on the rising edge of SYNC.
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write to each DAC’s
dedicated input register individually. When LDAC is low,
the input register is transparent (if not controlled by the
LDAC mask register).
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
LDAC)
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
When the data has been transferred into the input register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low while the SYNC line is high.
Rev. 0 | Page 22 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together and is enabled
through a software executable daisy-chain enable (DCEN)
command. Command 1000 is reserved for this DCEN function
(see Table 7). The daisy-chain mode is enabled by setting
Bit DB0 in the DCEN register. The default setting is standalone
mode, where DB0 = 0. Table 9 shows how the state of the bit
corresponds to the mode of operation of the device.
READBACK OPERATION
Table 9. Daisy-Chain Enable (DCEN) Register
DB0
0
1
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
address bits, DAC A to DAC D, selects the register to read. Note
that only one DAC register can be selected during readback.
The remaining three address bits must be set to Logic 0. The
remaining data bits in the write sequence are don’t care bits. If
more than one or no bits are selected, DAC Channel A is read
back by default. During the next SPI write, the data appearing
on the SDO output contains the data from the previously
addressed register.
Description
Standalone mode (default)
DCEN mode
AD5686R/
AD5685R/
AD5684R
68HC11*
MOSI
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
SDO
MISO
DAC. When the serial transfer to all devices is complete, SYNC
is taken high. This latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register. The serial clock can be continuous or
a gated clock. A continuous SCLK source can be used only
if SYNC can be held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high after
the final clock to latch the data.
SDIN
AD5686R/
AD5685R/
AD5684R
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
SCLK
SYNC
1.
LDAC
SDO
2.
SDIN
AD5686R/
AD5685R/
AD5684R
SCLK
SYNC
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
10485-057
SDO
Figure 54. Daisy-Chaining the AD5686R/AD5685R/AD5684R
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDIN input on the next DAC in the chain, a daisy-chain interface
is constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices that are updated.
If SYNC is taken high at a clock that is not a multiple of 24, it is
considered a valid frame and invalid data may be loaded to the
Rev. 0 | Page 23 of 32
Write 0x900000 to the AD5686R/AD5685R/AD5684R
input register. This configures the part for read mode with
the DAC register of Channel A selected. Note that all data
bits, DB15 to DB0, are don’t care bits.
Follow this with a second write, a NOP condition,
0x000000. During this write, the data from the register is
clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
AD5686R/AD5685R/AD5684R
Data Sheet
POWER-DOWN OPERATION
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
power-down options. The output is connected internally to
GND through either a 1 kΩ or a 100 kΩ resistor, or it is left
open-circuited (three-state). The output stage is illustrated in
Figure 55.
The AD5686R/AD5685R/AD5684R contain three separate
power-down modes. Command 0100 is designated for the powerdown function (see Table 7). These power-down modes are
software-programmable by setting eight bits, Bit DB7 to Bit DB0,
in the input shift register. There are two bits associated with each
DAC channel. Table 10 shows how the state of the two bits
corresponds to the mode of operation of the device.
Table 10. Modes of Operation
PDx1
0
PDx0
0
0
1
1
1
0
1
DAC
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUTX
RESISTOR
NETWORK
10485-058
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
Figure 55. Output Stage During Power-Down
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding bits. See
Table 11 for the contents of the input shift register during the
power-down/power-up operation.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The DAC register can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the parts work
normally with its normal power consumption of 4 mA at 5 V.
However, for the three power-down modes, the supply current
falls to 4 μA at 5 V. Not only does the supply current fall, but the
To reduce the current consumption further, the on-chip reference
can be powered off. See the Internal Reference Setup section.
Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation 1
DB23
0
DB22
1
DB21
0
DB20
0
Command bits (C3 to C0)
1
DB19 to DB16
X
Address bits
Don’t care
DB15
to
DB8
X
DB7
PDD1
DB6
PDD0
Power-Down
Select DAC D
X = don’t care.
Rev. 0 | Page 24 of 32
DB5
PDC1
DB4
PDC0
Power-Down
Select DAC C
DB3
PDB1
DB2
PDB0
Power-Down
Select DAC B
DB1
PDA1
DB0
(LSB)
PDA0
Power-Down
Select DAC A
Data Sheet
AD5686R/AD5685R/AD5684R
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5686R/AD5685R/AD5684R DACs have double
buffered interfaces consisting of two banks of registers:
input registers and DAC registers. The user can write to
any combination of the input registers. Updates to the DAC
register are controlled by the LDAC pin.
Command 0101 is reserved for this software LDAC function.
Address bits are ignored. Writing to the DAC, using Command
0101, loads the 4-bit LDAC register (DB3 to DB0). The default
for each channel is 0; that is, the LDAC pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the LDAC pin, regardless of the state of the hardware LDAC
pin. This flexibility is useful in applications where the user
wishes to select which channels respond to the LDAC pin.
OUTPUT
AMPLIFIER
VREF
16-/14-/12-BIT
DAC
LDAC
DAC
REGISTER
VOUTX
Table 12. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits
(DB3 to DB0)
0
1
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
LDAC Pin
LDAC Operation
1 or 0
X1
Determined by the LDAC pin.
DAC channels update and
override the LDAC pin. DAC
channels see LDAC as 1.
10485-059
INPUT
REGISTER
1
Figure 56. Simplified Diagram of Input Loading Circuitry for a Single DAC
X = don’t care.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 12). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
Instantaneous DAC Updating (LDAC Held Low)
LDAC is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of SYNC and
the output begins to change (see Table 13).
Deferred DAC Updating (LDAC is Pulsed Low)
LDAC is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Table 13. Write Commands and LDAC Pin Truth Table1
Commands
0001
Description
Write to Input Register n (dependent on LDAC)
0010
Update DAC Register n with contents of Input
Register n
0011
Write to and update DAC Channel n
Hardware LDAC
Pin State
VLOGIC
GND2
VLOGIC
Input Register
Contents
Data update
Data update
No change
GND
No change
VLOGIC
GND
Data update
Data update
DAC Register Contents
No change (no update)
Data update
Updated with input register
contents
Updated with input register
contents
Data update
Data update
A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
are not masked (blocked) by the LDAC mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
1
Rev. 0 | Page 25 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
HARDWARE RESET (RESET)
SOLDER HEAT REFLOW
RESET is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the RESET select pin. It is necessary to keep
RESET low for a minimum amount of time to complete the
operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
while the RESET pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see Table 7). Any events on LDAC or RESET during power-on
reset are ignored.
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
Figure 57 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
RESET SELECT PIN (RSTSEL)
60
POSTSOLDER
HEAT REFLOW
50
PRESOLDER
HEAT REFLOW
30
20
10
0
2.498
2.499
INTERNAL REFERENCE SETUP
The on-chip reference is on at power-up by default. To reduce the
supply current, this reference can be turned off by setting
software programmable bit, DB0, in the control register.
Table 14 shows how the state of the bit corresponds to the mode
of operation. Command 0111 is reserved for setting up the
internal reference (see Figure 9). Table 14 shows how the state
of the bits in the input shift register corresponds to the mode of
operation of the device during internal reference setup.
2.502
LONG-TERM TEMPERATURE DRIFT
Figure 58 shows the change in VREF value after 1000 hours in life
test at 150°C.
60
0 HOUR
168 HOURS
500 HOURS
1000 HOURS
50
40
HITS
30
20
10
0
2.498
2.499
2.500
2.501
2.502
VREF (V)
Figure 58. Reference Drift Through to 1000 Hours
Rev. 0 | Page 26 of 32
10485-061
Action
Reference on (default)
Reference off
2.501
Figure 57. SHR Reference Voltage Shift
Table 14. Reference Setup Register
Internal Reference
Setup Register (DB0)
0
1
2.500
VREF (V)
10485-060
The AD5686R/AD5685R/AD5684R contain a power-on reset
circuit that controls the output voltage during power-up. By
connecting the RSTSEL pin low, the output powers up to zero
scale. Note that this is outside the linear region of the DAC; by
connecting the RSTSEL pin high, VOUT powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC.
HITS
40
Data Sheet
AD5686R/AD5685R/AD5684R
THERMAL HYSTERESIS
9
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
8
7
6
5
4
3
2
1
0
–200
–150
–100
–50
0
DISTORTION (ppm)
Figure 59. Thermal Hysteresis
Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23
(MSB)
DB22 DB21
DB20
0
1
1
1
Command bits (C3 to C0)
1
DB19
X
DB18
DB17
DB16
X
X
X
Address bits (A2 to A0)
X = don’t care.
Rev. 0 | Page 27 of 32
DB15 to DB1
X
Don’t care
DB0 (LSB)
1/0
Reference setup register
50
10485-062
HITS
Thermal hysteresis data is shown in Figure 59. It is measured
by sweeping the temperature from ambient to −40°C, then
to +105°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements and
shown in blue in Figure 59. The same temperature sweep
and measurements were immediately repeated and the
results are shown in red in Figure 59.
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
AD5686R/AD5685R/AD5684R
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5686R/AD5685R/
AD5684R is via a serial bus that uses a standard protocol that
is compatible with DSP processors and microcontrollers.
The communications channel requires a 3- or 4-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The devices require a 24-bit data-word with data valid
on the rising edge of SYNC.
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5686R/
AD5685R/AD5684R are mounted should be designed so that
the AD5686R/AD5685R/AD5684R lie on the analog plane.
AD5686R/AD5685R/AD5684R TO ADSP-BF531
INTERFACE
The SPI interface of the AD5686R/AD5685R/AD5684R is
designed to be easily connected to industry-standard DSPs and
microcontrollers. Figure 60 shows the AD5686R/AD5685R/
AD5684R connected to the Analog Devices Blackfin® DSP. The
Blackfin has an integrated SPI port that can be connected
directly to the SPI pins of the AD5686R/AD5685R/AD5684R.
AD5686R/
AD5685R/
AD5684R
SYNC
SCLK
SDIN
LDAC
RESET
10485-164
PF9
PF8
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The AD5686R/AD5685R/AD5684R have an exposed paddle
beneath the device. Connect this paddle to the GND supply for
the part. For optimum performance, use special considerations
to design the motherboard and to mount the package. For
enhanced thermal, electrical, and board level performance,
solder the exposed paddle on the bottom of the package to the
corresponding thermal land paddle on the PCB. Design thermal
vias into the PCB land paddle area to further improve heat
dissipation.
ADSP-BF531
SPISELx
SCK
MOSI
The AD5686R/AD5685R/AD5684R should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on each
supply, located as close to the package as possible, ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) such
as the common ceramic types, which provide a low impedance
path to ground at high frequencies to handle transient currents
due to internal logic switching.
Figure 60. ADSP-BF531 Interface
AD5686R/AD5685R/AD5684R TO SPORT
INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 61 shows how one SPORT interface can be used to
control the AD5686R/AD5685R/AD5684R.
The GND plane on the device can be increased (as shown in
Figure 62) to provide a natural heat sinking effect.
AD5686R/
AD5685R/
AD5684R
AD5686R/
AD5685R/
AD5684R
ADSP-BF527
GND
PLANE
SYNC
SCLK
SDIN
LDAC
RESET
10485-165
BOARD
GPIO0
GPIO1
Figure 62. Paddle Connection to Board
Figure 61. SPORT Interface
Rev. 0 | Page 28 of 32
10485-166
SPORT_TFS
SPORT_TSCK
SPORT_DTO
Data Sheet
AD5686R/AD5685R/AD5684R
CONTROLLER
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that
may occur. iCoupler® products from Analog Devices provide
voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5686R/AD5685R/AD5684R makes the part
ideal for isolated interfaces because the number of interface
lines is kept to a minimum. Figure 63 shows a 4-channel
isolated interface to the AD5686R/AD5685R/AD5684R
using an ADuM1400. For further information, visit
http://www.analog.com/icouplers.
SERIAL
CLOCK IN
SERIAL
DATA OUT
ADuM14001
VOA
VIA
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
VIB
VOB
VIC
SYNC OUT
LOAD DAC
OUT
1
VOC
VOD
VID
ADDITIONAL PINS OMITTED FOR CLARITY.
Rev. 0 | Page 29 of 32
Figure 63. Isolated Interface
TO
SCLK
TO
SDIN
TO
SYNC
TO
LDAC
10485-167
GALVANICALLY ISOLATED INTERFACE
AD5686R/AD5685R/AD5684R
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
4
5
8
0.50
0.40
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
08-16-2010-E
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. 0 | Page 30 of 32
0.75
0.60
0.45
Data Sheet
AD5686R/AD5685R/AD5684R
ORDERING GUIDE
Model 1
AD5686RACPZ-RL7
AD5686RBCPZ-RL7
AD5686RARUZ
AD5686RARUZ-RL7
AD5686RBRUZ
AD5686RBRUZ-RL7
AD5685RBCPZ-RL7
AD5685RARUZ
AD5685RARUZ-RL7
AD5685RBRUZ
AD5685RBRUZ-RL7
AD5684RBCPZ-RL7
AD5684RARUZ
AD5684RARUZ-RL7
AD5684RBRUZ
AD5684RBRUZ-RL7
EVAL-AD5686RSDZ
Resolution
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±8 LSB INL
±2 LSB INL
±8 LSB INL
±8 LSB INL
±2 LSB INL
±2 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±2 LSB INL
±2 LSB INL
±1 LSB INL
±1 LSB INL
Reference
Tempco
(ppm/°C)
±5 (typ)
±5 (max)
±5 (typ)
±5 (typ)
±5 (max)
±5 (max)
±5 (max)
±5 (typ)
±5 (typ)
±5 (max)
±5 (max)
±5 (max)
±5 (typ)
±5 (typ)
±5 (max)
±5 (max)
EVAL-AD5684RSDZ
1
Z = RoHS Compliant Part.
Rev. 0 | Page 31 of 32
Package
Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
AD5686R TSSOP
Evaluation Board
AD5684R TSSOP
Evaluation Board
Package
Option
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
RU-16
RU-16
RU-16
RU-16
Branding
DJM
DJN
DJK
DJG
AD5686R/AD5685R/AD5684R
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10485-0-4/12(0)
Rev. 0 | Page 32 of 32

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