MOTOROLA MC44864M Pll tuning circuit with 1.3 ghz prescaler and d/a converter Datasheet

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! The MC44864 is a tuning circuit for TV applications. This device contains
a PLL section and a DAC section and is MCU controlled through an I2C Bus.
The PLL section contains all the functions required to control the VCO of a
TV tuner. The IC generates the tuning voltage and the additional control
signals, such as band switching voltages.
The D/A section generates three additional varactor voltages to feed all of
the varactors of the tuner with individually optimized control voltages
(automatic tuner adjustment). The MC44864 is manufactured on a single
silicon chip using Motorola’s high density bipolar process, MOSIAC
(Motorola Oxide Self–Aligned Implanted Circuits).
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PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND D/A CONVERTERS
SEMICONDUCTOR
TECHNICAL DATA
Complete Single Chip System for MPU Control
Selectable ÷8 Prescaler Accepts Frequencies up to 1.3 GHz
15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
20
Programmable Reference Divider
1
3–State Phase/Frequency Comparator
Operational Amplifier for Direct Varactor Control with Low Saturation
Voltage
Four Output Buffers (15 mA)
M SUFFIX
PLASTIC PACKAGE
CASE 967
(EIAJ–20)
Output Options for 62.5 kHz, Reference Frequency and the
Programmable Divider
The HF Input is Symmetrical
Three 6 Bit DACs for Automatic Tuner Adjustment Allowing Use of
Non–Matched Varactors
Better Tuner Performances Through Optimum Filter Response
I2C Bus Controlled
PIN CONNECTIONS
XTAL
1
20 Gnd
Four Chip Addresses for the PLL Section
PHO
2
19 SDA
Four Chip Addresses for the D/A Section
Amp In
3
18 SCL
VCC2
VTUN
DA1
4
17 B7
16 B5
DA2
7
15 B3
14 B1
DA3
8
13 CA
VCC1
9
12 Gnd
HF1 10
11 HF2
ESD Protected to MIL–STD–883C, Method 3015.7
(2,000 V, 1.5 kΩ, 150 pF)
MOSAIC is a trademark of Motorola, Inc.
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltage (VCC1)
Pin
Value
Unit
9
6.0
V
Band Buffer “Off” Voltage
14 – 17
15
V
Band Buffer “On” Current
14 – 17
20
mA
4
36
V
5–8
Continuous
S
Storage Temperature
–
– 65 to +150
°C
Operating Temperature Range
–
0 to +70
°C
Operational Amplifier Power Supply
Voltage (VCC2)
Operational Amplifier Short Circuit Duration
(0 to VCC2)
NOTE:
ESD data available upon request.
5
6
(Top View)
ORDERING INFORMATION
Device
MC44864M
Operating
Temperature Range
Package
TA = 0° to +70°C
EIAJ–20
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Rev 2
1
MC44864
Representative Block Diagram
B7 B5 B3 B1
17 16 15 14
B7 B5 B3
DA3
DA2
8
Amp 4
B1
DA1
7
Amp 3
VCC2 33 V
4
VTUN
5
6
Amp 2
Amp 1
Buffers
Bias
Test
Logic
Fout
VCC1
5.0 V
9
D/A 3
6 Bit
D/A 2
6 Bit
D/A 1
6 Bit
Ref
Voltage
Latches
Latches
Latches
Latches
2
Fref
Decoder
Phase
Comp
Shift Register
8 Bit
Fout
SCL
SDA
Gnd
PHO
F1
DTC
CA
3 Amp
In
Fref
13
DTB
Latches
Ref
Divider
FUN
18
CL
I2C Bus
Receiver
Data
19
F1
62.5 kHz
Shift Register
15 Bit
4.0 MHz
Osc
AD1
AD2
12
DTF
1
20
Latches A
XTAL
Gnd
TDI
Latches B
HF1
HF2
10
Preamp 1
÷8
Presc
11
Program Divider
15 Bit
Fout
Latch
Control
AVA
Preamp 2
This device contains 3,551 active transistors.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44864
ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 32 V, TA = 25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
Unit
VCC1 Supply Voltage Range
9
4.5
5.0
5.5
V
VCC1 Supply Current (VCC1 = 5.0 V)(1)(2)
9
–
50
70
mA
VCC2 Supply Voltage Range
4
25
30
35
V
mA
4
–
1.3
2.5(4)
Band Buffer Leakage Current when “Off” at 12 V
14 – 17
–
0.01
1.0
µA
Band Buffer Saturation Voltage when “On” at 15 mA
14 – 17
–
1.8
2.0
V
Data/Clock Current at 0 V
VCC2 Supply Current (Output Open)
18, 19
–10
–
0
µA
Clock Current at 5.0 V
18
0
–
1.0
µA
Data Current at 5.0 V Acknowledge “Off”
19
0
–
1.0
µA
Data Saturation Voltage at 15 mA Acknowledge “On”
19
–
1.2
–
V
Data/Clock Input Voltage Low
18, 19
–
–
1.5
V
Data/Clock Input Voltage High
18, 19
3.0
–
–
V
18
–
–
100
kHz
Clock Frequency Range
Phase Detector Current in High Impedance State
2
–15
–
15
nA
1, 2
3.5
4.0
4.1
MHz
Phase Detector High–State Source Current (@ 1.5 V)
2
–2.5
–
–0.5
mA
Phase Detector Low–State Sink Current (@ 4.0 V)
2
0.5
–
2.5
mA
Operational Amplifier Internal Reference Voltage
–
2.0
2.5
3.0
V
Operational Amplifier Input Current
3
–15
–
15
nA
DC Open Loop Gain
–
2000
–
–
V/V
Gain Bandwidth Product
–
–
0.2
–
MHz
Oscillator Frequency Range
Phase Margin
–
–
50
–
Deg.
Vout Low, Sinking 50 µA
6–8
–
0.2
0.5
V
Vout High, Sourcing 50 µA (VCC2 – Vout High)
6–8
–
–
1.5
V
Tuning Voltage (DC)
5–8
–
–
30
V
D/A Converters Step Size(3)
6–8
0.5
–
1.5
LSB
D/A Converters Temperature Drift
6–8
–
1.0
–
LSB
DAC Offset at VTUN = 2.5 V
–
–50
–
50
mV
DAC Offset at VTUN = 25 V
–
–700
–
700
mV
6–8
–
–
33
V
DAC Voltages (DC)
NOTES: 1. When prescaler “Off”, typical supply current is decreased by 10 mA.
2. Band Buffers “Off”, 2.4 mA more when one buffer is on.
3. For definition of the LSB, see Figure 9 in the D/A section.
4. 2.5 mA as long as the analog outputs are not in saturation high, which means VTUN, VDAC (Pins 5, 6, 7, 8) lower than VCC2 – 1.5 V. When all
outputs are in saturation high the maximum VCC2 current is 5.0 mA.
MOTOROLA ANALOG IC DEVICE DATA
3
MC44864
HF CHARACTERISTICS (See Figure 1)
Pin
Min
Typ
Max
Unit
DC Bias
10, 11
–
1.55
–
V
Input Voltage Range
10–150 MHz (Prescaler “Off”)
80–1000 MHz
1000–1300 MHz
10, 11
10, 11
10, 11
20
20
50
–
–
–
315
315
315
Characteristic
mVrms
Figure 1. HF Sensitivity Test Circuit
ÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇ
I2C Bus
Bus Controller
+5.0 V
12 V
18, 19
VCC1
9
3.9 k
MC44864
11
10
12
1
17
B7
In
Frequency
Counter
HF Generator
HF Out
1.0 nF
Gnd
1.0 nF
22 pF
50 Ω Cable
4.0 MHz
50 Ω
Device is in test mode: B7 is “On”, R2 = 1 and R3 = 0 (see Bus section).
Sensitivity is the level of the HF generator on 50 Ω load (without MC44864 load).
Figure 2. Typical HF Input Impedance
–j
+j
0
0.5
0.5
0.5
ZO = 50 Ω
1.3 GHz
1
1
1
1.0 GHz
2
2
2
500 MHz
50 MHz
4
MOTOROLA ANALOG IC DEVICE DATA
MC44864
PIN FUNCTION DESCRIPTION
Pin
6, 7, 8
9
Symbol
Description
DA1, DA2, DA3
D/A output control voltages
VCC1
Positive supply of the circuit (except DACs)
10, 11
HF1, HF2
HF input from local oscillator
12, 20
Gnd
Ground
13
CA
Chip Address
14, 15, 16, 17
B1, B3, B5, B7
Band buffer output can drive 15 mA
18
SCL
Clock input (supplied by the microprocessor via Bus)
19
SDA
Data input (bus)
1
XTAL
Crystal oscillator (typically 4.0 MHz)
2
PHO
Phase comparator output
3
Amp In
Negative operational amplifier input
4
VCC2
Operational amplifier positive supply
5
VTUN
Operational amplifier output which provides the tuning voltage
MOTOROLA ANALOG IC DEVICE DATA
5
MC44864
Figure 3. Pin Circuit Schematic
20 V
20 V
DA1
6
VTUN
5
Amp
Out
Amp
Out
20 V
DA2
7
VCC2
4
20 V
Amp
Out
IB
Comp
600 k
DA3
8
Amp
In
3
10 k
20 V
5.5 V
20 V
VCC1
9
PHO
2
5.5 V
VCC1
20 V
5.5 V
HF1
10
10 k
VCC1 1.0 k
5.5 V
20 V
XTAL
1
5.5 V
5.5 V
1.0 k
1.0 k
20 k
HF2
11
20 V
2.0 k
1.5 k
100
Gnd
20
50
SDA
19
VCC1
5.5 V
2.0 k
1.1 mA
Gnd
12
100 k
0.4 mA
130 k
VCC1
5.0 µA
VCC1
25 k
20 V
ACK
40 k
150 k
500
10 k
CA
13
20 k
20 V
50 k
B1
14
20 V
B3
15
20 V
100 k
15 k
SCL
18
Buffer
B7
17
Buffer
B5
16
VCC1
2.5 k
Buffer
On/Off
Buffer
6
MOTOROLA ANALOG IC DEVICE DATA
MC44864
FUNCTIONAL DESCRIPTION
optimum value of the other varactor voltages. The digital
word for each voltage value is stored in a nonvolatile memory
(NVM). Hence, for each frequency point to be adjusted, three
times 6 bits of information have to be stored (plus 2 bits for
the DAC range).
The information stored in the NVM reflects the
characteristic of the individual tuner. For this reason, the
NVM is preferably situated inside the tuner and is also
controlled by the I2C Bus.
A representative block diagram and a typical system
application are shown in Figures 4 and 5. A discussion of the
features and function of the internal blocks is given below.
Automatic Tuner Alignment
The circuit generates the tuning voltage through the PLL.
The output voltages of the D/A converters are equal to the
tuning voltage plus a positive or negative offset of up to 31
steps. During the automatic alignment one first lets the PLL
lock to the appropriate frequency and then searches for the
Figure 4. Block Diagram
DA3
DA2
DA1
VTUN
1.0 n
1.0 n
1.0 n
39 n
180 n
18 k
1.0 n
Bands and
Controls Out
17
16
15
B7 B5 B3
8
14
7
Amp 4
B1
6
Amp 3
VCC2 33 V
4
5
Amp 2
Amp
3 In
Amp 1
Buffers
Bias
10 k
Test
Logic
Fout
VCC1
5.0 V
9
D/A 3
6 Bit
D/A 2
6 Bit
D/A 1
6 Bit
Ref
Voltage
Latches
Latches
Latches
Latches
1.0 n
10 k
2
Fref
PHO
F1
Decoder
Phase
Comp
Shift Register
8 Bit
DTC
10 k
Fout
(1)
15 k
CA
13
DTB
SCL
SDA
Gnd
Fref
Latches
Ref
Divider
FUN
18
CL
I2C Bus
Receiver
19
Data
F1
62.5 kHz
Shift Register
15 Bit
4.0 MHz
Osc
AD1
AD2
12
DTF
1 XTAL
20 Gnd
(2)
Latches A
TDI
Latches B
HF1
HF2
10
Preamp 1
÷8
Presc
11
Program Divider
15 Bit
Fout
Latch
Control
AVA
Preamp 2
NOTES: 1. Pin 13: Short to VCC
Resistors ±10%
Open or 1.0 nF to Gnd
Short to Gnd
for addresses CC, CE
for addresses C8, CA (values 10 k and 15 k) for test only
for addresses C4, C6
for addresses C0, C2
2. The crystal may be connected to Pin 20 with no connection to external Gnd.
MOTOROLA ANALOG IC DEVICE DATA
7
MC44864
Figure 5. TV Tuner for Automatic Alignment
IF
12 V
VCC3
UHF VHF
BIII
Band Buffers
AGC
Filter
33 V
VCC2
Mixer
Filter
5.0 V
VCC1
Antenna
MC44864
PLL–D/A IC
HF Input
DA3
SDA
Data
XTAL
Local
Oscillator
SCL
Clock
VTUN
Amp In
D–to–A
Converters
Phase Cmp
DA1
DA2
NVM
Figure 6. Definition of Bytes
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
CA1_PLL Chip Address
CO_Control Information
BA_Band Information
FM_Frequency Information (with MSB)
FL_Frequency Information (with LSB)
1
1
0
0
A3
A2
A1
A0 = 0
ACK
1
R6
T
P
R3
R2
R1
R0
ACK
B7
X
B5
X
B3
X
B1
X
ACK
0
N14
N13
N12
N11
N10
N9
N8
ACK
N7
N6
N5
N4
N3
N2
N1
N0
ACK
Chip Addresses
The chip address is programmable by Pin CA.
The PLL addresses C0, C2, C4, C6 are officially allocated
to PLL–IC’s.
The addresses C8, CA, CC, CE are not officially allocated.
Care has to be taken in the application that no conflict occurs
with other devices on the same I2C Bus when using the
addresses C8 to CE.
CA Pin (13)
A3
A2
A1
A0
Address
Function
–0.04 VCC1 to
0.1 VCC1
0
0
0
0
0
1
0
0
C0
C2
1st PLL
1st DAC
Open or 0.2
VCC1 to 0.3 VCC1
0
0
1
1
0
1
0
0
C4
C6
2nd PLL
2nd DAC
0.42 VCC1 to
0.75 VCC1
1
1
0
0
0
1
0
0
C8
CA
3rd PLL
3rd DAC
0.9 VCC1 to 1.2
VCC1
1
1
1
1
0
1
0
0
CC
CE
4th PLL
4th DAC
8
PLL SECTION
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via I2C Bus. The incoming information is treated in the bus
receiver. The definition of the permissible bus protocol is
shown in the four examples below:
Ex. 1 STA CA1 CO
BA STO
Ex. 2 STA CA1 FM
FL STO
Ex. 3 STA CA1 CO
BA FM
FL
STO
Ex. 4 STA CA1 FM
FL CO
BA
STO
STA = Start Condition
STO = Stop Condition
CA1 = Chip Address Byte of the PLL Section
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information (MSB’s)
FL = Data Byte for Frequency Information (LSB’s)
Figure 6 shows the five bytes of information that are
needed for circuit operation: there is a chip address, two
bytes of control and band information and two bytes of
frequency information.
MOTOROLA ANALOG IC DEVICE DATA
MC44864
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third data byte
is ignored. If five or more data bytes are received, the fifth
and following data bytes are ignored and the last
acknowledge pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit F. If
the function bit F= 0, frequency information is acknowledged
and if F = 1, control/band information is acknowledged.
If the address is correct (signal AD1) the information is
loaded into latches.
A function bit in the first and third data byte is used to pass
this data either into the latches of the programmable divider
(signal DTF) or into the latches for band and control information
(signal DTB). The data transfer to the latches (signals DTF and
DTB) is initiated after the 2nd and 4th data bytes.
A second string of latches is used for the data transfer into
the programmable divider to inhibit the transfer during the
preset operation (signal TDI, signal AVA is an internal
“address valid” command).
The switching levels of clock and data (Pins 18 and 19) are
0.5 x VCC1.
The control and band information bits have the following
functions.
Bits R0, R1: Controls Reference Divider Division Ratio
R0
R1
Division Ratio
0
1
0
1
0
0
1
1
2048
1024
512
256
Bits R2, R3: Switches Internal Signals to the Buffer
Outputs
R2
R3
Pin 16
Pin 17
0
0
1
1
0
1
0
1
–
62.5 kHz
Fref
–
–
–
FBY2
–
Bit B5 has to be “one” when Pin 16 is used to output 62.5
kHz. Bits B5 and B7 have to be “one” to output Fref and FBY2.
FBY2 is the programmable divider output frequency divided
by two.
Bits R2, R6, T: Controls the Phase Comparator Output
Stage
R2
R6
T
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output State
Normal Operation
“Off” (High Impedance)
High
Low
Normal Operation
“Off”
Normal Operation
“Off”
The Band Buffers
The band buffers are open collector transistors and are
active “low” at Bn = 1. They are designed for 15 mA with
typical on–voltage of 1.8 V. These buffers are designed to
withstand relative high output voltage in the off–state (15 V).
B5 and B7 buffers (Pins 16 and 17) may also be used to
output internal IC signals (reference frequency and
programmable divider output frequency divided by 2) for test
purposes.
MOTOROLA ANALOG IC DEVICE DATA
Buffer B5 may also be used to output a 62.5 kHz frequency
from an intermediate stage of the reference divider. The bits
B5 and B7 have to be “one” if the buffers are used for these
additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
Minimum Ratio 256
where N0 … N14 are the different bits for frequency
information.
The counter reloads correctly as long as its output
frequency does not exceed 1.0 MHz.
Division ratios of < 256 are not allowed. At power–up the
counter bit N8 is preset to “1”. All other bits are undetermined.
In this way, the counter always starts with a division ratio of
256 or higher.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the bus.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The prescaler has a preamplifier and may be bypassed
(Bit P). The signal then passes through preamplifier 2.
The table on the following page shows the frequency
ranges which may be synthesized with and without prescaler.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier for the tuning voltage is designed
for low noise, low input bias current and high power supply
rejection. The positive input is biased internally. The
operational amplifier needs 30 V supply (VCC2) as minimum
voltage for a guaranteed maximum tuning voltage of 28.5 V.
Figure 4 shows the usual filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 4 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The crystal is driven through a 1.6 kΩ resistor on chip.
The voltage at Pin 16 “crystal”, has low amplitude and low
harmonic distortion.
The negative resistance of the oscillator at Pin 1 (XTAL) is
about 3.0 kΩ.
9
MC44864
With Int. Prescaler
P=0
Without Prescaler
P=1
Input Data
R0
R1
Reff Divider
Ref.
R
Di id
Div. Ratio
Reff Freq.
Freq
Ref.
R
F
Hz(1)
Frequency
Steps kHz
Max Input
Max.
Freq. MHz
Frequency
Steps kHz
Max Imput
Max.
Freq. MHz
0
1
0
1
0
0
1
1
2048
1024
512
256
1953.125
3906.25
7812.5
15625.0
15.625
31.25
62.5
125.0
512
1024
1300(2)
1300(2)
1.953125
3.90625
7.8125
15.625
64
128
165(3)
165(3)
NOTES: 1. With 4.0 MHz Crystal
2. Limit of Prescaler
3. Limit of Programmable Divider
For satellite tuner applications the circuit may be used with an external /4 prescaler and a reference divider ration of 1024 (R0 = 1, R1 = 0). In this way,
frequencies up to 4.0 GHz can be synthesized with 125 kHz resolution (4.0 MHz crystal).
The same result can be achieved with an external /32 prescaler when the internal prescaler is bypassed (P = 1).
C3 contain the address for the individual converter and the 6
bits to be converted. Bit D5 is the sign (log “1” for positive
offset, log “0” for negative offset) and the bits D0 to D4
determine the number of steps to be made as an offset from
the tuning voltage. The bits S0 and S1 in the data byte RA
define the step size (Vstep) and the range of the converters
(see Figures 8 and 9). The range is the same for all
converters.
After the chip address (CA2) is acknowledged, up to four
data bytes may be received by the IC. If more than four bytes
are received, the fifth and following bytes are ignored and the
last acknowledge pulse is sent after the fourth data byte. The
data transfer to the converters (signal DTC) is initiated each
time a complete data byte is received.
The following shows some examples of the permissible
bus protocols of the D–to–A section. The data bytes may be
sent to the IC in random order with up to four in one
sequence. The same converter may be loaded up to four
times as shown in example 6. Below are 6 examples of
permissible bus protocols.
The Reference Divider
The reference divider of the MC44864 is programmable
(Bits R0 and R1) for ratios of 2048, 1024, 512 and 256. This
feature makes the circuit versatile.
Bit P: Controls the Prescaler
P
0
1
Prescaler Function
Prescaler Active
Prescaler Bypassed
Prescaler Power Supply “Off”
Bits B1, B3, B5, B7: Controls the Band Buffers
B1, B3, B5, B7 = 0
B0, B1, B, B73 = 1
Buffer “Off”
Buffer “On”
D/A SECTION
Basic Function
The D/A section has four separate chip addresses from
the PLL section. Three D–to–A converters that have a
resolution of 6 bits (5 bits plus sign) are on chip. The analog
output voltages are dc. The converters are buffered to the
analog outputs DA1, DA2 and DA3 by operational amplifiers
with an output voltage range that is equal to the tuning
voltage range (about 0 to 30 V). The operational amplifiers
are arranged such that a positive or negative offset can be
generated from the tuning voltage.
Ex. 1
Ex. 2
Ex. 3
Ex. 4
Ex. 5
Ex. 6
STA
STA
STA
STA
STA
STA
CA2
CA2
CA2
CA2
CA2
CA2
C1
C1
C1
C1
RA
C1
STO
C2
C2
C2
C1
C1
STO
C3
C3
C2
C1
STO
RA
STO
C3
STO
C1
STO
STA = Start Condition
STO = Stop Condition
CA2 = Chip Address Byte for D/A Section
C1, C2, C3 = Data Bytes for D/A Converters
RA = Data Byte for Range
Data Format and Bus Protocols
The D–to–A information consists of the D/A chip address
(CA2) and four data bytes. The first two bits of the data bytes
are used as the function address. Thus the bytes C1, C2 and
Figure 7. Definition of Bytes
CA2_D/A Chip Address
C1_Converter 1
C2_Converter 2
C3_Converter 3
RA_Range Selection
10
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1
1
0
0
A2
A1
A0 = 0
ACK
0
0
D5
D4
D3
D2
D1
D0
ACK
0
1
D5
D4
D3
D2
D1
D0
ACK
1
0
D5
D4
D3
D2
D1
D0
ACK
1
1
X
X
X
X
S1
S0
ACK
MOTOROLA ANALOG IC DEVICE DATA
MC44864
Figure 8. Output Voltage (D/A Converters)
VDA = VTUN ± Vstep (D0 +2 D1 +4 D2 +8 D3 + 16 D4)
D5 = 1 positive sign; D5 = 0 negative sign
VTUN: Tuning Voltage set by PLL
Vstep: Voltage Step (LSB) of the D/A Converters
Figure 9. Range Selection of the D/A Converters
Input Data
S0
S1
Typ. Step Size
Vstep
0
1
0
1
0
0
1
1
225 mV
125 mV
70 mV
40 mV
Guaranteed
Range 31
Steps
6.25 V
3.40 V
1.90 V
1.05 V
The D/A Converters
The D/A converters convert 5 bit into analog current of
which the polarity is switched by the sixth bit. The reference
voltage of the converters is programmed by two bits (S0, S1
of the RA–byte) to determine the scaling factor. The analog
currents are then converted into voltages and added to their
respective operational amplifier nominal bias. The resulting
voltages at Pins 6, 7 and 8 are the tuning voltages (VTUN, see
Figure 4) at Pin 5 plus any offset provided by information in
the D/A converters.
If the data bits D0 to D4 are all “0”, the three D/A output
voltages on Pins 6, 7 and 8 are equal to the tuning voltage
(Pin 5) within the DAC offset voltages.
The four amplifiers have the same output characteristics
with the maximum output voltage being 1.5 V lower than
VCC2 in the worst case. The four analog outputs are
short–circuit protected. At power–up, the D/A outputs are
undetermined.
The D/A converters are guaranteed to be monotonic with a
voltage step variation of ±0.5 LSB.
The D/A converters work correctly as long as the PLL loop
is active. VTUN is then between 0.3 V and VCC2 – 1.5 V. If the
loop saturates, the DACs do not work.
The DAC–OFFSET is defined as the difference between
the DAC output voltage (with bits D0 to D4 = 0) and the tuning
voltage (PLL active). The DAC operation is guaranteed from
0.3 V to VCC2 – 1.5 V. On typical samples, the DACs will
operate down to 0.2 V.
Figure 10. Definition of DAC Offset
DAC Offset
(VDAC – VTUN)
±700 mVmax
±50 mVmax
10
MOTOROLA ANALOG IC DEVICE DATA
20
30 V
VTUN
11
MC44864
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC PACKAGE
CASE 967–01
(EIAJ–20)
ISSUE O
20
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5 THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
M_
E HE
1
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
0.10 (0.004)
M
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.81
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.032
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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12
◊
MOTOROLA ANALOG IC DEVICE DATA
*MC44864/D*
MC44864/D