ON MAC15S Sensitive gate triacs silicon bidirectional thyristor Datasheet

MAC15SD, MAC15SM,
MAC15SN
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for industrial and consumer applications for full wave
control of AC loads such as appliance controls, heater controls, motor
controls, and other power switching applications.
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TRIACS
15 AMPERES RMS
400 thru 800 VOLTS
Features
• Sensitive Gate allows Triggering by Microcontrollers and other
•
•
•
•
•
•
•
•
•
Logic Circuits
High Immunity to dv/dt − 25 V/ms minimum at 110°C
High Commutating di/dt − 8.0 A/ms minimum at 110°C
Maximum Values of IGT, VGT and IH Specified for Ease of Design
On-State Current Rating of 15 Amperes RMS at 70°C
High Surge Current Capability − 120 Amperes
Blocking Voltage to 800 Volts
Rugged, Economical TO−220AB Package
Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3
Pb−Free Packages are Available*
MT2
MARKING
DIAGRAM
MAC15SxG
AYWW
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
2
3
Symbol
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 110°C, Sine Wave, 50 to
60 Hz, Gate Open)
MAC15SD
MAC15SM
MAC15SN
VDRM,
VRRM
On−State RMS Current
(Full Cycle Sine Wave, 60Hz, TJ = 70°C)
IT(RMS)
15
A
ITSM
120
A
I2t
60
A2s
PGM
20
W
PG(AV)
0.5
W
Operating Junction Temperature Range
TJ
−40 to +110
°C
Device
Storage Temperature Range
Tstg
−40 to +150
°C
Circuit Fusing Consideration (t = 8.3 ms)
Peak Gate Power
(Pulse Width ≤ 1.0 ms, TC = 70°C)
Average Gate Power (t = 8.3 ms, TC = 70°C)
Unit
TO−220AB
CASE 221A−09
STYLE 4
Rating
Peak Non-repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
TJ = 110°C)
Value
V
= D, M, or N
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
December, 2005 − Rev. 5
x
A
Y
WW
G
400
600
800
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
© Semiconductor Components Industries, LLC, 2005
MT1
G
1
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
Package
Shipping
MAC15SD
TO−220AB
50 Units / Rail
MAC15SDG
TO−220AB
(Pb−Free)
50 Units / Rail
MAC15SM
TO−220AB
50 Units / Rail
MAC15SMG
TO−220AB
(Pb−Free)
50 Units / Rail
MAC15SN
TO−220AB
50 Units / Rail
MAC15SNG
TO−220AB
(Pb−Free)
50 Units / Rail
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MAC15S/D
MAC15SD, MAC15SM, MAC15SN
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
Junction−to−Case
Junction−to−Ambient
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
Symbol
Value
Unit
RqJC
RqJA
2.0
62.5
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
−
−
−
−
0.01
2.0
−
−
1.8
Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
TJ = 25°C
TJ = 110°C
IDRM,
IRRM
mA
ON CHARACTERISTICS
Peak On-State Voltage (Note 2) (ITM = "21A)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IGT
Hold Current (VD = 12 V, Gate Open, Initiating Current = "150mA)
IH
Latching Current (VD = 24V, IG = 5mA)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IL
−
−
−
2.0
3.0
3.0
5.0
5.0
5.0
−
3.0
10
−
−
−
5.0
10
5.0
15
20
15
0.45
0.45
0.45
0.62
0.60
0.65
1.5
1.5
1.5
(di/dt)c
8.0
10
−
A/ms
dv/dt
25
75
−
V/ms
mA
mA
VGT
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
V
mA
V
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
(VD = 400V, ITM = 3.5A, Commutating dv/dt = 10Vm/sec,
Gate Open, TJ = 110°C, f= 500Hz, Snubber: CS = 0.01 mF, RS =15W, see Figure 15)
Critical Rate of Rise of Off-State Voltage
(VD = Rate VDRM, Exponential Waveform, RGK = 510W, TJ = 110°C)
2. Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.
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2
MAC15SD, MAC15SM, MAC15SN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VTM
VDRM
Peak Repetitive Forward Off State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On State Voltage
IH
Holding Current
on state
IH
IRRM at VRRM
off state
IH
Quadrant 3
MainTerminal 2 −
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
(−) MT2
Quadrant III
Quadrant 1
MainTerminal 2 +
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
+ Voltage
IDRM at VDRM
110
100
a = 30 and 60°
90
a
a
80
a = CONDUCTION ANGLE
120°
70
180°
60
0
2
4
6
8
10
12
IT(RMS), RMS ON−STATE CURRENT (AMPS)
14
DC
16
P(AV), AVERAGE POWER DISSIPATION (WATTS)
T C , MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)
MAC15SD, MAC15SM, MAC15SN
25
DC
a
a
20
60°
10
a = 30°
5
0
0
0.1
0.5
Maximum @
TJ = 110°C
1
1.5
2
2.5
3
3.5
4
VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
4.5
R(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED)
I T, INSTANTANOUS ON-STATE CURRENT (AMPS)
Maximum @
TJ = 25 °C
1
2
16
ZqJC(t) = RqJC(t) r(t)
0.1
0.01
0.1
1
10
100
t, TIME (ms)
1@10 4
1000
Figure 4. Transient Thermal Response
7
9
6
8
I L , LATCHING CURRENT (mA)
I H , HOLDING CURRENT (mA)
14
1
Figure 3. On−State Characteristics
5
MT2 NEGATIVE
4
3
MT2 POSITIVE
2
1
−40
4
6
8
10
12
IT(RMS), RMS ON−STATE CURRENT (AMPS)
Figure 2. Maximum On−State Power Dissipation
Typical @ TJ = 25 °C
10
90°
a = CONDUCTION ANGLE
15
Figure 1. RMS Current Derating
100
180°
120°
7
Q1
6
5
Q3
4
3
−25
−10
5
20
35
50
65
80
TJ, JUNCTION TEMPERATURE (°C)
95
2
−40
110
Figure 5. Typical Holding Current Versus
Junction Temperature
−25
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
80
95
Figure 6. Typical Latching Current Versus
Junction Temperature
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4
110
MAC15SD, MAC15SM, MAC15SN
0.9
V GT, GATE TRIGGER VOLTAGE (VOLTS)
IGT, GATE TRIGGER CURRENT (mA)
7
6
5
Q3
4
3
Q2
2
Q1
1
0
−40
−25
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
80
95
0.8
0.7
Q3
0.6
Q1
0.5
Q2
0.4
0.3
−40
110
−25
Figure 7. Typical Gate Trigger Current
Versus Junction Temperature
80
95
110
Figure 8. Typical Gate Trigger Voltage
Versus Junction Temperature
110
140
TJ = 110°C
VPK = 400V
TJ = 100°C
100
STATIC dv/dt (V/mS)
120
STATIC dv/dt (V/mS)
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
600V
100
800V
90
110°C
80
70
80
120°C
60
RG − MT1 = 510W
60
100
200
300
400
500
600
700
800
RGK, GATE−MT1 RESISTANCE (OHMS)
900
1000
50
400
Figure 9. Typical Exponential Static dv/dt
Versus Gate−MT1 Resistance, MT2(+)
100
160
VPK = 400V
STATIC dv/dt (V/mS)
STATIC dv/dt (V/mS)
180
80
600V
70
800V
60
RG − MT1 = 510W
110
115
TJ, Junction Temperature (°C)
700
750
800
TJ = 100°C
140
120
110°C
100
80
120°C
RG − MT1 = 510W
40
105
550
600
650
VPK, Peak Voltage (Volts)
60
50
40
100
500
Figure 10. Typical Exponential Static dv/dt
Versus Peak Voltage, MT2(+)
110
90
450
120
20
125
Figure 11. Typical Exponential Static dv/dt
Versus Junction Temperature, MT2(+)
400
450
500
550
600
650
VPK, Peak Voltage (Volts)
700
750
Figure 12. Typical Exponential Static dv/dt
Versus Peak Voltage, MT2(*)
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5
800
(dv/dt)c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/m s)
MAC15SD, MAC15SM, MAC15SN
200
100
600V
VPK = 400V
100
800V
50
RG − MT1 = 510W
0
100
105
110
115
TJ, Junction Temperature (°C)
120
125
Figure 13. Typical Exponential Static dv/dt
Versus Junction Temperature, MT2(*)
90°C
10
100°C
f=
1
2 tw
tw
(di/dt)c =
VDRM
6f ITM
1000
1
5
10
15
20
25
(di/dt)c, CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 14. Critical Rate of Rise of
Commutating Voltage
CHARGE
1N4007
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON-POLAR
CL
110°C
1
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
TRIGGER CONTROL
STATIC dv/dt (V/mS)
150
RS
−
CS
MT2
1N914 51 W
ADJUST FOR +
di/dt(c)
200 V
MT1
G
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 15. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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6
MAC15SD, MAC15SM, MAC15SN
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−− 0.080
STYLE 4:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MAC15S/D
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