PD - 95775A IRLR3714ZPbF IRLU3714ZPbF ® HEXFET Power MOSFET Applications l l l High Frequency Synchronous Buck Converters for Computer Processor Power High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Lead-Free VDSS 20V Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current RDS(on) max 15m: D-Pak IRLR3714Z Qg 4.7nC I-Pak IRLU3714Z Absolute Maximum Ratings Parameter Max. Units 20 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 37 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current 144 PD @TC = 25°C Maximum Power Dissipation 35 PD @TC = 100°C Maximum Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range ID @ TC = 25°C ID @ TC = 100°C c f 26 g g A W 18 0.23 -55 to + 175 Soldering Temperature, for 10 seconds W/°C °C 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) RθJA Junction-to-Ambient Notes through www.irf.com g Typ. Max. ––– 4.28 ––– 50 ––– 110 Units °C/W are on page 11 1 12/7/04 IRLR/U3714ZPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance ––– 20 V Conditions ––– ––– VGS = 0V, ID = 250µA ––– 14 ––– ––– 12 15 mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A 20 25 VGS = 4.5V, ID = 12A VGS(th) Gate Threshold Voltage 1.65 2.1 2.55 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.2 ––– mV/°C IDSS Drain-to-Source Leakage Current µA VDS = 16V, VGS = 0V nA VGS = 20V ––– ––– 1.0 ––– ––– 150 IGSS Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 gfs Qg Forward Transconductance 21 ––– ––– e e VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V, TJ = 125°C VGS = -20V S VDS = 10V, ID = 12A Total Gate Charge ––– 4.7 7.1 Qgs1 Pre-Vth Gate-to-Source Charge ––– 1.7 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 0.7 ––– Qgd Gate-to-Drain Charge ––– 1.7 ––– ID = 12A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 0.6 ––– See Fig. 16 Qsw ––– 2.4 ––– Qoss Output Charge ––– 2.6 ––– td(on) Turn-On Delay Time ––– 5.4 ––– VDD = 15V, VGS = 4.5V tr Rise Time ––– 7.6 ––– ID = 12A td(off) Turn-Off Delay Time ––– 9.2 ––– tf Fall Time ––– 4.3 ––– Ciss Input Capacitance ––– 560 ––– Coss Output Capacitance ––– 180 ––– Crss Reverse Transfer Capacitance ––– 95 ––– VDS = 10V nC nC ns VGS = 4.5V VDS = 10V, VGS = 0V e Clamped Inductive Load VGS = 0V pF VDS = 10V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. Max. Units ––– 31 mJ ––– 12 A ––– 3.5 mJ Diode Characteristics Parameter Min. Typ. Max. Units f IS Continuous Source Current ––– ––– 37 ISM (Body Diode) Pulsed Source Current ––– ––– 144 VSD (Body Diode) Diode Forward Voltage ––– ––– 1.0 V trr Reverse Recovery Time ––– 21 32 ns Qrr Reverse Recovery Charge ––– 8.5 13 nC ton Forward Turn-On Time 2 c Conditions MOSFET symbol A showing the integral reverse p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V e TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRLR/U3714ZPbF 1000 1000 VGS 100 10 1 3.0V 60µs PULSE WIDTH Tj = 25°C ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V TOP TOP 100 0.1 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 10 3.0V 60µs PULSE WIDTH Tj = 175°C 1 0.1 0 1 10 100 100 0.1 0 VDS, Drain-to-Source Voltage (V) 1 10 100 100 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 T J = 25°C 100 T J = 175°C 10 VDS = 10V 60µs PULSE WIDTH 1 2.0 4.0 6.0 8.0 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10.0 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 ID, Drain-to-Source Current (Α) VGS ID = 30A VGS = 10V 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRLR/U3714ZPbF 10000 12 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 12A C, Capacitance (pF) C oss = C ds + C gd 1000 Ciss Coss Crss 100 VDS= 20V VDS= 10V 10 8 6 4 2 0 10 1 10 0 100 2 4 6 8 10 12 QG Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000 1000.0 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100.0 T J = 175°C 10.0 1.0 TJ = 25°C 100µsec 10 1msec 1 10msec Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.1 0.1 0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 2.0 0 1 10 100 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U3714ZPbF 2.6 40 VGS(th) Gate threshold Voltage (V) ID , Drain Current (A) LIMITED BY PACKAGE 30 20 10 0 25 50 75 100 125 150 2.4 ID = 250µA 2.2 2.0 1.8 1.6 1.4 1.2 175 -75 -50 -25 T C , Case Temperature (°C) 0 25 50 75 100 125 150 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 τJ R1 R1 τJ τ1 τ1 R2 R2 τ2 τ2 R3 R3 τ3 τC τ τ3 Ri (°C/W) 1.2525 2.423 τi (sec) 0.00015 0.00098 0.6041 0.00984 Ci= τi/Ri Ci= i/Ri 0.01 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3714ZPbF 15V D.U.T RG + V - DD IAS 20V VGS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS, Single Pulse Avalanche Energy (mJ) DRIVER L VDS 140 ID 3.4A 5.4A BOTTOM 12A TOP 120 100 80 60 40 20 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF .3µF D.U.T. + V - DS Fig 14a. Switching Time Test Circuit VDS 90% VGS 3mA IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 10% VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U3714ZPbF D.U.T Driver Gate Drive P.W. + + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period V DD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U3714ZPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ ⎞ ⎞ ⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U3714ZPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASS EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE ASS EMBLY LINE "A" PART NUMBER INTERNATIONAL RECT IFIER LOGO Note: "P" in as sembly line pos ition indicates "Lead-F ree" IRFU120 12 916A 34 ASS EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INT ERNAT IONAL RECT IF IER LOGO IRFU120 12 AS SEMBLY LOT CODE www.irf.com 34 DATE CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = AS SEMBLY S ITE CODE 9 IRLR/U3714ZPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRF U120 WITH AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN THE AS S EMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFU120 919A 56 78 AS S EMBLY LOT CODE Note: "P" in as s embly line pos ition indicates "Lead-Free" DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR PART NUMBE R INT ERNAT IONAL RECTIF IER LOGO IRFU120 56 AS SEMBLY LOT CODE 10 78 DATE CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPTIONAL) YEAR 9 = 1999 WE EK 19 A = ASS EMBLY SIT E CODE www.irf.com IRLR/U3714ZPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.43mH, RG = 25Ω, IAS = 12A. Pulse width ≤ 400µs; duty cycle ≤ 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com 11